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um10398 lpc111x/lpc11cxx user manual rev. 12.1 ? 7 august 2013 user manual document information info content keywords arm cortex-m0, LPC1111, lpc1112, lpc1113, lpc1114, lpc1115, lpc11c12, lpc11c14, lpc1100, lpc1100l, lpc11c00, lpc11c22, lpc11c24, lpc11d14, lpc1100xl abstract lpc111x/lpc11cxx user manual
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 2 of 543 contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com nxp semiconductors um10398 lpc111x/lpc11cxx user manual revision history rev date description 12.1 20130807 lpc111x/lpc11c1x/lpc11c2x user manual modifications: ? remove instruction breakpoints from feature list for swd. see section 27.2 . ? irqlatency register added in syscon block. see ta b l e 3 5 . ? reset value of the c_can canclkdiv register changed to 0x1, see table 275 . ? ram used by isp sizes updated. see section 26.4.8 , section 26.4.9 . ? ssel1_loc register description corrected. see ta b l e 1 5 2 . ? added lpc1115fet48. ? editorial updates. ? updated go command section 26.5.8 . 12 20120924 lpc111x/lpc11c1x/lpc11c2x user manual modifications: ? bod level 0 for reset added. see table 33 . ? description of the temt bit in the uart lsr register updated. see table 196 . 11 20120726 lpc111x/lpc11c1x/lpc11c2x user manual modifications: ? function ssel1 added to pin pi o2_0 in table 170 and figure 28. ? bod level 0 for reset and interrupt removed. 10 20120626 lpc111x/lpc11c1x/lpc11c2x user manual modifications: ? lpc1112fhn24 pinout corrected in table 161 and figure 18. ? description of bypass bit corrected in table 12 s ystem oscillator control register (sysoscctrl, address 0x4004 8020) bit description. 9 20120517 lpc111x/lpc11c1x/lpc11c2x/lpc11d14 user manual modifications: ? lpc11d14/pcf8576d block diagram updated (see figure 5). ? description of interrupt use with i ap calls updated (see section 26.4.7). ? sysrststat register access changed to r/w (table 7). ? frequency values for freqsel bits in the wd toscctrl register corrected (see table 13). ? figure 9 updated (reset changed to internal reset). ? limit number of bytes copied in copy ram to flash isp and iap commands for parts with less than 4 kb sram (see table 381 and table 396). ? figure 14 updated with pseudo open-drain mode. ? part lpc1112fhn24/202 added. ? part ids added for parts lpc1110fd20, LPC1111fdh20/002, lpc1112fd20/102, lpc1112fdh20/102, lpc1112fdh28/102, lpc1114fdh28/102, lpc1114fn28/102. ? sram use by bootloader specified in section 26.3.1. 8 20120308 lpc111x/lpc11c1x/lpc11c2x user manual 7 20110919 lpc111x/lpc11c1x/lpc11c2x user manual 6 20110822 lpc111x/lpc11c1x/lpc11c2x user manual 5 20110621 lpc111x/lpc11c1x/lpc11c2x user manual
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 3 of 543 nxp semiconductors um10398 chapter : 4 20110304 lpc111x/lpc11c1x/lpc11c2x user manual 3 20110114 lpc111x/lpc11c1x/lpc11c2x user manual 2 20101102 lpc111x/lpc11c1x user manual 1 20100721 lpc111x/lpc11c1x user manual revision history ?continued rev date description
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 1 of 543 1.1 introduction the lpc111x/lpc11cxx are a arm cortex-m 0 based, low-cost 32-bit mcu family, designed for 8/16-bit microcontroller applications , offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit architectures. the lpc111x/lpc11cxx operate at cpu frequencies of up to 50 mhz. the peripheral complement of the lpc111x/lpc11cxx includes up to 32 kb of flash memory, up to 8 kb of data memory, one c_can controller (lpc11cxx), one fast-mode plus i 2 c-bus interfac e, one rs-485/eia-485 uart, up to two spi interfaces with ssp features, four general purpose timers, a 10-bit adc, and up to 42 general purpose i/o pins. on-chip c_can drivers and flash in-system programming tools via c_can are included on the lpc11cxx. in addition, parts lp c11c2x are equipped with an on-chip can transceiver. remark: this user manual covers the lpc111x/lpc11cxx parts and the lpc11d14 dual-chip part with pcf8576d lcd controller. the lpc111x/lpc11cxx parts are grouped by the following series and part names (see ta b l e 1 for a feature overview): ? lpc1100 series (parts lpc111x/101/201/301) ? lpc1100l series (parts lpc111x/102/202/302) and part lpc11d14 with lcd controller. ? lpc1100xl series (parts lpc111x/103/203/323/333) ? lpc11c00 series (parts lpc11c1x/301 and lpc11c2x/301) with c_can controller. um10398 chapter 1: lpc111x/lpc11cxx introductory information rev. 12.1 ? 7 august 2013 user manual
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 2 of 543 nxp semiconductors um10398 chapter 1: lpc111x/lpc11cxx introductory information table 1. lpc111x/lpc11cxx feature changes series features overview lpc1100 series ? i2c, ssp, uart, gpio ? timers and watch dog timer ? 10-bit adc ? flash/sram memory ? for a full feature list, see section 1.2 . lpc1100l series lpc1100 series features plus the following additional features: ? power profiles with lower power consumption in active and sleep modes. ? internal pull-up resistors pull up pins to full v dd level. ? programmable pseudo open-drain mode for gpio pins. ? wwdt with clock source lock capability. ? small packages (tssop, so, dip, hvqfn) lpc1100xl series lpc1100l series features plus the following new features: ? flash page erase in-application programming (iap) function. ? timer, uart, and ssp functions pi nned out on a dditional pins. ? one capture function added for each timer. ? capture-clear feature on the 16-bit and 32-bit timers for easy pulse-width measurements. lpc11c00 series lpc1100 series features plus the following additional features: ? can controller. ? on-chip can drivers. ? on-chip can transceiver (lpc11c2x). ? wdt (not windowed) with clock source lock capability. lpc11d14 (lpc1100l series) lpc1100l series with lcd controller pcf8576d in a dual-chip package.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 3 of 543 nxp semiconductors um10398 chapter 1: lpc111x/lpc11cxx introductory information 1.2 features ? system: ? arm cortex-m0 processor, running at frequencies of up to 50 mhz. ? arm cortex-m0 built-in nested vect ored interrupt controller (nvic). ? serial wire debug. ? system tick timer. ? memory: ? on-chip flash programming memory for lpc1100, lpc1100l, and lpc1100c series: 32 kb (lpc1114/lpc11c14), 24 kb (lpc1113), 16 kb (lpc1112/lpc11c12), or 8 kb (LPC1111), 4kb (lpc1110). ? on-chip flash programming memory for lpc1100xl series: 8 kb (LPC1111), 16 kb (lpc1112), 24 kb (lpc1113), 32 kb (lpc1114/203/303), 48 kb (lpc1114/323), 56 kb (lpc1114/333), 64 kb (lpc1115). ? 8 kb, 4 kb, 2 kb, or 1 kb sram. ? in-system programming (isp) and in-application programming (iap) via on-chip bootloader software. ? lpc1100xl series only: page erase iap command. ? digital peripherals: ? up to 42 general purpose i/o (gpio) pins with configurable pull-up/pull-down resistors. number of gpio pins is reduced for smaller packages and lpc11c22/c24. ? gpio pins can be used as edge and level sensitive interrupt sources. ? high-current output driver (20 ma) on one pin. ? high-current sink drivers (20 ma) on two i 2 c-bus pins in fast-mode plus. ? four general purpose timers/counters with a total of four capture inputs and up to 13 match outputs. ? programmable watchdog timer (wdt). ? analog peripherals: ? 10-bit adc with input multip lexing among up to 8 pins. ? serial interfaces: ? uart with fractional baud rate generation, internal fifo, and rs-485 support. ? two spi controllers with ssp features and with fifo and multi-protocol capabilities (second spi on lqfp48 packages only). ? i 2 c-bus interface supporting full i 2 c-bus specification and fast-mode plus with a data rate of 1 mbit/s with multiple address recognition and monitor mode. ? c_can controller (lpc11cxx only). on-c hip can and canopen drivers included. ? on-chip, high-speed can transceiver (parts lpc11c22/c24 only). ? clock generation: ? 12 mhz internal rc oscillato r trimmed to 1% accuracy th at can optionally be used as a system clock. ? crystal oscillator with an opera ting range of 1 mhz to 25 mhz.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 4 of 543 nxp semiconductors um10398 chapter 1: lpc111x/lpc11cxx introductory information ? programmable watchdog oscillator with a fr equency range of 7.8 khz to 1.8 mhz. ? pll allows cpu operation up to the maximum cpu rate without the need for a high-frequency crystal. may be run from t he system oscillator or the internal rc oscillator. ? clock output function with di vider that can refl ect the system oscillator clock, irc clock, cpu clock, and the watchdog clock. ? power control: ? integrated pmu (power management unit) to minimize power consumption during sleep, deep-sleep, and deep power-down modes. ? power profiles residing in boot rom allowing to optimize performance and minimize power consumption for any given application through one simple function call. (on lpc1100l and lpc1100xl parts only). ? three reduced power modes: sleep, deep-sleep, and deep power-down. ? processor wake-up from deep-sleep mode via a dedicated start logic using up to 13 of the functional pins. ? power-on reset (por). ? brownout detect with up to four separate thresholds for interrupt and forced reset. ? unique device serial number for identification. ? single 3.3 v power supply (1.8 v to 3.6 v). ? available as lqfp48 package, hvqfn33 package. ? lpc1100l series also available as hvqf n24, tssop28 package, dip28 package, tssop20 package, and so20 package. ? available as dual-chip module consisting of the lpc1114 single-chip microcontroller combined with a pcf8576d universal lcd driver in a 100-pin lqfp package (part lpc11d14fbd100/302). 1 1. for details on the pcf8576d operation, see ref. 3 .
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 5 of 543 nxp semiconductors um10398 chapter 1: lpc111x/lpc11cxx introductory information 1.3 ordering information table 2. ordering information type number package name description version so20, tssop20, tssop2 8, and dip28 packages lpc1110fd20 so20 so20: plastic small outline pa ckage; 20 leads; body width 7.5 mm sot163-1 LPC1111fdh20/002 tssop20 tssop20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 lpc1112fd20/102 so20 so20: plastic small outline package; 20 leads; body width 7.5 mm sot163-1 lpc1112fdh20/102 tssop20 tssop20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 lpc1112fdh28/102 tssop28 tssop28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm sot361-1 lpc1114fdh28/102 tssop28 tssop28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm sot361-1 lpc1114fn28/102 dip28 dip28: plastic dual in-line package; 28 leads (600 mil) sot117-1 hvqfn24/33 and lqfp48 packages LPC1111fhn33/101 hvqfn33 hvqfn: plastic thermal en hanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a LPC1111fhn33/102 hvqfn33 hvqfn: plastic thermal en hanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a LPC1111fhn33/201 hvqfn33 hvqfn: plastic thermal en hanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a LPC1111fhn33/202 hvqfn33 hvqfn: plastic thermal en hanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a LPC1111fhn33/103 hvqfn33 hvqfn: plastic thermal en hanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a LPC1111fhn33/203 hvqfn33 hvqfn: plastic thermal en hanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1112fhn33/101 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1112fhn33/102 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1112fhn33/201 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1112fhn33/202 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1112fhn24/202 hvqfn24 hvqfn24: plastic therma l enha nced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm sot616-3 lpc1112fhi33/202 hvqfn33 hvqfn: plastic therma l enhanced very thin quad flat package; no leads; 33 terminals; body 5 ? 5 ? 0.85 mm n/a lpc1112fhi33/203 hvqfn33 hvqfn: plastic therma l enhanced very thin quad flat package; no leads; 33 terminals; body 5 ? 5 ? 0.85 mm n/a lpc1112fhn33/103 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1112fhn33/203 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 6 of 543 nxp semiconductors um10398 chapter 1: lpc111x/lpc11cxx introductory information lpc1113fhn33/201 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1113fhn33/202 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1113fhn33/301 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1113fhn33/302 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1113fhn33/203 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1113fhn33/303 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1114fhn33/201 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1114fhn33/202 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1114fhn33/301 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1114fhn33/302 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1114fhi33/302 hvqfn33 hvqfn: plastic therma l enhanced very thin quad flat package; no leads; 33 terminals; body 5 ? 5 ? 0.85 mm n/a lpc1114fhi33/303 hvqfn33 hvqfn: plastic therma l enhanced very thin quad flat package; no leads; 33 terminals; body 5 ? 5 ? 0.85 mm n/a lpc1114fhn33/203 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/ a l p c1114fhn33/303 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1114fhn33/333 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1113fbd48/301 lqfp48 lqfp48: plastic low pr ofile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 lpc1113fbd48/302 lqfp48 lqfp48: plastic low pr ofile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 lpc1113fbd48/303 lqfp48 lqfp48: plastic low pr ofile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 lpc1114fbd48/301 lqfp48 lqfp48: plastic low pr ofile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 lpc1114fbd48/302 lqfp48 lqfp48: plastic low pr ofile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 lpc1114fbd48/303 lqfp48 lqfp48: plastic low pr ofile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 lpc1114fbd48/323 lqfp48 lqfp48: plastic low pr ofile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 table 2. ordering information ?continued type number package name description version
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 7 of 543 nxp semiconductors um10398 chapter 1: lpc111x/lpc11cxx introductory information lpc1114fbd48/333 lqfp48 lqfp48: plastic low pr ofile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 lpc1115fbd48/303 lqfp48 lqfp48: plastic low pr ofile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 lpc1115fet48/303 tfbga48 plastic thin fine-pitch ball grid array package; 48 balls; body 4.5 ? 4.5 ? 0.7 mm sot1155-2 table 2. ordering information ?continued type number package name description version table 3. ordering options type number series flash total sram uart rs-485 i 2 c/ fm+ spi power profiles adc channels gpio c_can package lpc1110 lpc1110fd20 lpc1100l 4 kb 1 kb 1 1 1 yes 5 16 - so20 LPC1111 LPC1111fdh20/002 lpc1100l 8 kb 2 kb 1 1 1 yes 5 16 - tssop20 LPC1111fhn33/101 lpc1100 8 kb 2 kb 1 1 1 no 8 28 - hvqfn33 LPC1111fhn33/102 lpc1100l 8 kb 2 kb 1 1 1 yes 8 28 - hvqfn33 LPC1111fhn33/103 lpc1100xl 8 kb 2 kb 1 1 2 yes 8 28 - hvqfn33 LPC1111fhn33/201 lpc1100 8 kb 4 kb 1 1 1 no 8 28 - hvqfn33 LPC1111fhn33/202 lpc1100l 8 kb 4 kb 1 1 1 yes 8 28 - hvqfn33 LPC1111fhn33/203 lpc1100xl 8 kb 4 kb 1 1 2 yes 8 28 - hvqfn33 lpc1112 lpc1112fd20/102 lpc1100l 16 kb 4 kb 1 1 1 yes 5 16 - so20 lpc1112fdh20/102 lpc1100l 16 kb 4 kb 1 - 1 yes 5 14 - tssop20 lpc1112fdh28/102 lpc1100l 16 kb 4 kb 1 1 1 yes 6 22 - tssop28 lpc1112fhn33/101 lpc1100 16 kb 2 kb 1 1 1 no 8 28 - hvqfn33 lpc1112fhn33/102 lpc1100l 16 kb 2 kb 1 1 1 yes 8 28 - hvqfn33 lpc1112fhn33/103 lpc1100xl 16 kb 2 kb 1 1 2 yes 8 28 - hvqfn33 lpc1112fhn33/201 lpc1100 16 kb 4 kb 1 1 1 no 8 28 - hvqfn33 lpc1112fhn24/202 lpc1100l 16 kb 4 kb 1 1 1 yes 6 19 - hvqfn24 lpc1112fhn33/202 lpc1100l 16 kb 4 kb 1 1 1 yes 8 28 - hvqfn33 lpc1112fhn33/203 lpc1100xl 16 kb 4 kb 1 1 2 yes 8 28 - hvqfn33 lpc1112fhi33/202 lpc1100l 16 kb 4 kb 1 1 1 yes 8 28 - hvqfn33 lpc1112fhi33/203 lpc1100xl 16 kb 4 kb 1 1 2 yes 8 28 - hvqfn33 lpc1113 lpc1113fhn33/201 lpc1100 24 kb 4 kb 1 1 1 no 8 28 - hvqfn33 lpc1113fhn33/202 lpc1100l 24 kb 4 kb 1 1 1 yes 8 28 - hvqfn33 lpc1113fhn33/203 lpc1100xl 24 kb 4 kb 1 1 2 yes 8 28 - hvqfn33 lpc1113fhn33/301 lpc1100 24 kb 8 kb 1 1 1 no 8 28 - hvqfn33
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 8 of 543 nxp semiconductors um10398 chapter 1: lpc111x/lpc11cxx introductory information lpc1113fhn33/302 lpc1100l 24 kb 8 kb 1 1 1 yes 8 28 - hvqfn33 lpc1113fhn33/303 lpc1100xl 24 kb 8 kb 1 1 2 yes 8 28 - hvqfn33 lpc1113fbd48/301 lpc1100 24 kb 8 kb 1 1 2 no 8 42 - lqfp48 lpc1113fbd48/302 lpc1100l 24 kb 8 kb 1 1 2 yes 8 42 - lqfp48 lpc1113fbd48/303 lpc1100xl 24 kb 8 kb 1 1 2 yes 8 42 - lqfp48 lpc1114 lpc1114fdh28/102 lpc1100l 32 kb 4 kb 1 1 1 yes 6 22 tssop28 lpc1114fn28/102 lpc1100l 32 kb 4 kb 1 1 1 yes 6 22 dip28 lpc1114fhn33/201 lpc1100 32 kb 4 kb 1 1 1 no 8 28 - hvqfn33 lpc1114fhn33/202 lpc1100l 32 kb 4 kb 1 1 1 yes 8 28 - hvqfn33 lpc1114fhn33/203 lpc1100xl 32 kb 4 kb 1 1 2 yes 8 lpc1114fhn33/301 lpc1100 32 kb 8 kb 1 1 1 no 8 28 - hvqfn33 lpc1114fhn33/302 lpc1100l 32 kb 8 kb 1 1 1 yes 8 28 - hvqfn33 lpc1114fhn33/303 lpc1100xl 32 kb 8 kb 1 1 2 yes 8 28 - hvqfn33 lpc1114fhn33/333 lpc1100xl 56 kb 8 kb 1 1 2 yes 8 28 - hvqfn33 lpc1114fhi33/302 lpc1100l 32 kb 8 kb 1 1 1 yes 8 28 - hvqfn33 lpc1114fhi33/303 lpc1100xl 32 kb 8 kb 1 1 2 yes 8 28 - hvqfn33 lpc1114fbd48/301 lpc1100 32 kb 8 kb 1 1 2 no 8 42 - lqfp48 lpc1114fbd48/302 lpc1100l 32 kb 8 kb 1 1 2 yes 8 42 - lqfp48 lpc1114fbd48/303 lpc1100xl 32 kb 8 kb 1 1 2 yes 8 42 - lqfp48 lpc1114fbd48/323 lpc1100xl 48 kb 8 kb 1 1 2 yes 8 42 - lqfp48 lpc1114fbd48/333 lpc1100xl 56 kb 8 kb 1 1 2 yes 8 42 - lqfp48 lpc1115 lpc1115fet48/303 lpc1100xl 64 kb 8 kb 1 1 2 yes 8 42 - tfbga48 lpc1115fbd48/303 lpc1100xl 64 kb 8 kb 1 1 2 yes 8 42 - lqfp48 lpc11c12/lpc11c14 lpc11c12fbd48/301 lpc11c00 16 kb 8 kb 1 1 2 no 8 40 1 lqfp48 lpc11c14fbd48/301 lpc11c00 32 kb 8 kb 1 1 2 no 8 40 1 lqfp48 lpc11c22/lpc11c24 with on-chip, high-speed can transceiver lpc11c22fbd48/301 lpc11c00 16 kb 8 kb 1 1 2 no 8 36 1 lqfp48 lpc11c24fbd48/301 lpc11c00 32 kb 8 kb 1 1 2 no 8 36 1 lqfp48 lpc11d14 dual-chip module with pcf8576d lcd driver 1 lpc11d14fbd100/302 lpc1100l 32 kb 8 kb 1 1 2 yes 8 42 - lqfp100 table 3. ordering options ?continued type number series flash total sram uart rs-485 i 2 c/ fm+ spi power profiles adc channels gpio c_can package
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 9 of 543 nxp semiconductors um10398 chapter 1: lpc111x/lpc11cxx introductory information 1.4 block diagram (1) lqfp48 packages only. (2) not on lpc1112fdh20/102. (3) all pins available on lqfp48 and hvqfn33 packages. ct16b1_mat1 not av ailable on tssop28/dip28 packages. ct32b1_mat3, ct16b1_cap0, ct16b1_mat[1:0], ct32b 0_cap0 not available on tssop20/so20 packages. ct16b1_mat[1:0], ct32b0_cap0 not available on the hvqfn 24 package. xtalout not available on lpc1112fhn24. (4) ad[7:0] available on lqfp48 and hvqfn33 packages. ad[5:0 ] available on tssop28/dip28/hvqfn24packages. ad[4:0] available on tssop20/so20 packages. (5) all pins available on lq fp48 packages. rxd, txd, dtr , cts , rts available on hvqfn 33 packages. rxd, txd, cts , rts available on tssop28/dip28 packages. rxd, txd available on t ssop20/so20 packages. fig 1. lpc111x block diagram (lpc1100 and lpc1100l series) sram 1/2/4/8 kb arm cortex-m0 test/debug interface flash 4/8/16/24/32 kb high-speed gpio ahb to apb bridge clock generation, power control, system functions xtalin xtalout (3) reset clocks and controls swd lpc1110/11/12/13/14 002aae696 slave slave slave slave rom slave ahb-lite bus gpio ports pio0/1/2/3 clkout irc por spi0 10-bit adc uart 32-bit counter/timer 0 i 2 c-bus (2) wdt ioconfig ct32b0_mat[3:0] (3) ad[7:0] (4) ct32b0_cap0 (3) sda scl rxd txd dtr, dsr, cts (5) , dcd, ri, rts (5) system control pmu 32-bit counter/timer 1 ct32b1_mat[3:0] (3) ct32b1_cap0 (3) 16-bit counter/timer 1 ct16b1_mat[1:0] (3) ct16b1_cap0 (3) 16-bit counter/timer 0 ct16b0_mat[2:0] (3) ct16b0_cap0 (3) sck0, ssel0 miso0, mosi sck1, ssel1 miso1, mosi spi1 (1) system bus
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 10 of 543 nxp semiconductors um10398 chapter 1: lpc111x/lpc11cxx introductory information (1) available on lqfp packages only. fig 2. lpc111x block diagram (lpc1100xl series) sram 2/4/8 kb arm cortex-m0 test/debug interface flash 8/16/24/32/ 48/56/64 kb high-speed gpio ahb to apb bridge clock generation, power control, system functions xtalin xtalout reset clocks and controls swd LPC1111/12/13/14/15xl 002aag780 slave slave slave slave rom slave ahb-lite bus gpio ports pio0/1/2/3 clkout irc por spi0 10-bit adc uart 32-bit counter/timer 0 i 2 c-bus wwdt ioconfig ct32b0_mat[3:0] ad[7:0] ct32b0_cap[1:0] sda scl rxd txd dtr, dsr (1) , cts, dcd (1) , ri (1) , rts system control pmu 32-bit counter/timer 1 ct32b1_mat[3:0] ct32b1_cap[1:0] 16-bit counter/timer 1 ct16b1_mat[1:0] ct16b1_cap[1:0] 16-bit counter/timer 0 ct16b0_mat[2:0] ct16b0_cap[1:0] sck0, ssel0 miso0, mosi0 sck1, ssel1 miso1, mosi1 spi1 system bus
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 11 of 543 nxp semiconductors um10398 chapter 1: lpc111x/lpc11cxx introductory information (1) not available on lpc11c22/c24. fig 3. lpc11cxx/lpc11d14 block diagram (lpc1100c series and lpc11d14) sram 8 kb arm cortex-m0 test/debug interface flash 16/32 kb high-speed gpio ahb to apb bridge clock generation, power control, system functions xtalin xtalout reset clocks and controls swd lpc11cxx lpc11d14 slave slave slave slave rom slave ahb-lite bus gpio ports pio0/1/2/3 clkout irc por spi0 10-bit adc uart 32-bit counter/timer 0 i 2 c-bus wdt ioconfig ct32b0_mat[3:0] ad[7:0] ct32b0_cap0 sda scl rxd txd dtr, dsr, cts, dcd, ri, rts system control pmu 32-bit counter/timer 1 ct32b1_mat[3:0] ct32b1_cap0 16-bit counter/timer 1 ct16b1_mat[1:0] (1) ct16b1_cap0 16-bit counter/timer 0 ct16b0_mat[2:0] ct16b0_cap0 sck0, ssel0 miso0, mosi0 sck1, ssel1 miso1, mosi1 spi1 system bus c_can (lpc11c12/c14) can_txd can_rxd c_can/ on-chip transceiver (lpc11c22/c24) canl, canh stb v cc , vdd_can
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 12 of 543 nxp semiconductors um10398 chapter 1: lpc111x/lpc11cxx introductory information fig 4. lpc11d14 block diagram scl, sda lcd_scl, lcd_sda v lcd lpc1114 mcu pcf8576d lcd controller pio0, pio1, pio2, pio3 s[39:0] bp[3:0] 002aag449 fig 5. pcf8576d block diagram 40 002aag451 lcd bias generator lcd voltage selector pcf8576d backplane outputs display controller command decoder write data control display ram 40 x 4-bit output bank select and blink control display register display segment outputs data pointer and auto increment subaddress counter clock select and timing oscillator input filters blinker timebase power-on reset i 2 c-bus controller bp0 bp2 bp1 bp3 v dd(lcd) osc sync s0 to s39 lcd_sda lcd_scl clk v ss(lcd) v ss(lcd) v ss(lcd) v ss(lcd) v lcd a0 sa0 a1 a2
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 13 of 543 nxp semiconductors um10398 chapter 1: lpc111x/lpc11cxx introductory information 1.5 arm cortex-m0 processor the arm cortex-m0 processor is described in detail in section 28.3 about the cortex-m0 processor and core peripherals . for the lpc111x/lpc11cxx, the arm cortex-m0 processor core is configured as follows: ? system options: ? the nested vectored interrupt controller (nvic) is included and supports up to 32 interrupts. ? the system tick timer is included. ? debug options: serial wire debug is included with two watchpoints and four breakpoints.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 17 of 543 2.1 how to read this chapter ta b l e 4 and ta b l e 5 show the memory configurations for different lpc111x/lpc11cxx parts. 2.2 memory map figure 6 and figure 7 show the memory and peripheral address space of the lpc111x/lpc11cxx. the ahb peripheral area is 2 mb in size and is divided to allow for up to 128 peripherals. on the lpc111x/lpc11cxx, the gpio port s are the only ahb pe ripherals. the apb peripheral area is 512 kb in size and is divi ded to allow for up to 32 peripherals. each peripheral of either type is allocated 16 kb of space. this allows simplifying the address decoding for each peripheral. all peripheral register addresses are 32-bit word aligned regardless of their size. an implication of this is that word and half-word registers must be accessed all at once. for example, it is not possible to read or write the upper byte of a word register separately. um10398 chapter 2: lpc111x/lpc11cxx memory mapping rev. 12.1 ? 7 august 2013 user manual table 4. lpc111x memory configuration part flash sram suffix /101; /102; /103 /201; /202; /203 /301; /302; /303; /323; /333 LPC1111 8 kb 2 kb 4 kb - lpc1112 16 kb 2 kb 4 kb - lpc1113 24 kb - 4 kb 8 kb lpc1114/lpc11d14 32 kb - 4 kb 8 kb lpc1114/323 48 kb - - 8 kb lpc1114/333 56 kb - - 8 kb lpc1115 64 kb - - 8 kb table 5. lpc11cxx memory configuration part flash sram lpc11c12/301 16 kb 8 kb lpc11c14/301 32 kb 8 kb lpc11c22/301 16 kb 8 kb lpc11c24/301 32 kb 8 kb
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 18 of 543 nxp semiconductors um10398 chapter 2: lpc111x/lpc11cxx memory mapping (1) lqfp100/lqfp48 packages only. (2) lpc11cxxonly. fig 6. lpc111x/lpc11cxx memory map (lpc1100 and lpc1100l series) 0x5000 0000 0x5001 0000 0x5002 0000 0x5020 0000 ahb peripherals 16 - 127 reserved gpio pio1 4-7 0x5003 0000 0x5004 0000 gpio pio2 gpio pio3 8-11 12-15 gpio pio0 0-3 reserved reserved reserved 0x0000 0000 0 gb 0.5 gb 4 gb 1 gb 0x0000 2000 0x1000 2000 0x1000 1000 0x1000 0800 0x1fff 0000 0x1fff 4000 0x2000 0000 0x4000 0000 0x4008 0000 0x5000 0000 0x5020 0000 0xffff ffff reserved reserved reserved apb peripherals ahb peripherals 8 kb sram (lpc1113/14/301/302; lpc11d14; lpc11cxx) 0x1000 0000 4 kb sram (LPC1111/12/13/14/201/202) 2 kb sram (LPC1111/12/101/102) LPC1111/12/13/14 lpc11cxx lpc11d14 8 kb on-chip flash (LPC1111) 0x0000 4000 0x0000 6000 16 kb on-chip flash (lpc1112; lpc11cx2) 0x0000 8000 32 kb on-chip flash (lpc1114; lpc11d14; lpc11cx4) 24 kb on-chip flash (lpc1113) 16 kb boot rom 0x0000 0000 0x0000 00c0 active interrupt vectors reserved apb peripherals 0x4000 4000 0x4000 8000 0x4000 c000 0x4001 0000 0x4001 8000 0x4002 0000 0x4002 8000 0x4003 8000 0x4003 c000 0x4004 0000 0x4004 4000 0x4004 8000 0x4004 c000 0x4005 0000 0x4005 4000 0x4005 8000 0x4005 c000 0x4008 0000 0x4002 4000 0x4001 c000 0x4001 4000 0x4000 0000 wdt 32-bit counter/timer 0 32-bit counter/timer 1 adc uart pmu i 2 c-bus 10 - 13 reserved reserved reserved reserved 23 - 31 reserved 16 15 14 17 18 spi0 16-bit counter/timer 1 16-bit counter/timer 0 ioconfig system control 20 c_can (2) reserved 22 spi1 (1) flash controller 0xe000 0000 0xe010 0000 private peripheral bus
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 19 of 543 nxp semiconductors um10398 chapter 2: lpc111x/lpc11cxx memory mapping fig 7. lpc111x memory map (lpc1100xl series) 0x5000 0000 0x5001 0000 0x5002 0000 0x5020 0000 ahb peripherals 127-16 reserved gpio pio1 4-7 0x5003 0000 0x5004 0000 gpio pio2 gpio pio3 8-11 12-15 gpio pio0 0-3 apb peripherals 0x4000 4000 0x4000 8000 0x4000 c000 0x4001 0000 0x4001 8000 0x4002 0000 0x4002 8000 0x4003 8000 0x4003 c000 0x4004 0000 0x4004 4000 0x4004 8000 0x4004 c000 0x4005 8000 0x4005 c000 0x4008 0000 0x4002 4000 0x4001 c000 0x4001 4000 0x4000 0000 wwdt 32-bit counter/timer 0 32-bit counter/timer 1 adc uart pmu i 2 c-bus 13-10 reserved reserved reserved 21-19 reserved 31-23 reserved 0 1 2 3 4 5 6 7 8 9 16 15 14 17 18 reserved reserved reserved 0x0000 0000 0 gb 0.5 gb 4 gb 1 gb 0x0000 2000 0x1000 2000 0x1000 1000 0x1000 0800 0x1fff 0000 0x1fff 4000 0x2000 0000 0x4000 0000 0x4008 0000 0x5000 0000 0x5020 0000 0xffff ffff reserved reserved reserved apb peripherals ahb peripherals 8 kb sram (lpc1113/14/15/303/323/333) 4 kb sram (LPC1111/12/13/14/203) 2 kb sram (LPC1111/12/103) 0x1000 0000 LPC1111/12/13/14/15xl 8 kb on-chip flash (LPC1111) 0x0000 4000 0x0000 6000 16 kb on-chip flash (lpc1112) 0x0000 8000 32 kb on-chip flash (lpc1114) 24 kb on-chip flash (lpc1113) 0x0000 c000 0x0000 e000 48 kb on-chip flash (lpc1114/323) 0x0001 0000 64 kb on-chip flash (lpc1115) 56 kb on-chip flash (lpc1114/333) 16 kb boot rom 0x0000 0000 0x0000 00c0 active interrupt vectors 002aag788 reserved spi0 16-bit counter/timer 1 16-bit counter/timer 0 ioconfig system control 22 spi1 flash controller 0xe000 0000 0xe010 0000 private peripheral bus
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 20 of 543 3.1 how to read this chapter the following functions of the system configuration block dep end on the specific part number: device_id register the device_id register is valid 0x4004 83f4 for parts of the lpc1100, lpc1100c, and lpc1100l series only. the device id cannot be read through the syscon block for the lpc1100xl series. use the isp part id command ( ta b l e 4 0 0 ) to obtain the device id for the lpc1100xl parts. c_can controller the c_can clock control bit 17 in the sysahbclkctrl register ( ta b l e 2 1 ) and the c_can reset control bit 3 in the presetctrl register ( ta b l e 9 ) are only functional for parts lpc11cxx/101/201/301. entering deep power-down mode status of the irc before entering deep power-down mode (see section 3.9.4.2 ): ? irc must be enabled for parts lpc111x/101/201/301 and parts lpc11cxx/101/201/301. ? irc status has no effect for parts in the lpc1100l and lpc1100xl series. enabling sequence for uart clock requirements for enabling the uart peripheral clock: ? the uart pins must be configured in the ioco n block before the uart clock can be enabled in the in the sysahbclkctrl register ( ta b l e 2 1 ) for parts lpc111x/101/201/301. ? the sequence of configuring the uart pins and the uart clock has no effect for parts in the lpc1100l and lpc1100xl series and parts lpc1100c series. nmi source selection register the nmi source selection register is only available on parts in the lpc1100xl series. 3.2 general description the system configuration block controls oscillato rs, start logic, and cl ock generation of the lpc111x/lpc11cxx. also included in this blo ck is a register for remapping flash, sram, and rom memory areas. 3.3 pin description ta b l e 6 shows pins that are associated with system control block functions. um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) rev. 12.1 ? 7 august 2013 user manual
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 21 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) 3.4 clock generation see figure 8 for an overview of the lpc111x/lpc11cxx clock generation unit (cgu). the lpc111x/lpc11cxx include three indepe ndent oscillators. th ese are the system oscillator, the internal rc oscillator (irc), an d the watchdog oscillator. each oscillator can be used for more than one purpose as required in a particular application. following reset, the lpc111x/lpc11cxx will oper ate from the internal rc oscillator until switched by software. this a llows systems to operate without any external crystal and the bootloader code to operate at a known frequency. the sysahbclkctrl register gates the system clock to the various peripherals and memories. uart, the wdt, and spi0/1 have indi vidual clock dividers to derive peripheral clocks from the main clock. the main clock and the clock outputs from the irc, the system oscillator, and the watchdog oscillator can be observed directly on the clkout pin. for details on power control see section 3.9 . table 6. pin summary pin name pin direction pin description clkout o clockout pin pio0_0 to pio0_11 i start logic wake-up pins port 0 pio1_0 i start logic wake-up pin port 1
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 22 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) 3.5 register description all registers, regardless of si ze, are on word address boundaries. details of the registers appear in the description of each function. see section 3.12 for the flash access timing register, which can be re-configured as part the system setup. this register is not part of the system configuration block. fig 8. lpc111x/lpc11cxx cgu block diagram system pll irc oscillator system oscillator watchdog oscillator irc oscillator watchdog oscillator mainclksel (main clock select) syspllclksel (system pll clock select) system clock divider sysahbclkctrl[1:18] spi0 peripheral clock divider spi0_pclk spi1 peripheral clock divider spi1_pclk uart peripheral clock divider uart_pclk wdt clock divider wdclk wdtuen (wdt clock update enable) watchdog oscillator irc oscillator system oscillator clkout pin clock divider clkout pin clkoutuen (clkout update enable) main clock system clock irc oscillator ahb clocks 1 to 18 (memories and peripherals) 18 sys_pllclkout sys_pllclkin arm cortex-m0 sysahbclkdiv table 7. register overview: system control block (base address 0x4004 8000) name access address offset description reset value reference sysmemremap r/w 0x000 system memory remap 0x002 ta b l e 8 presetctrl r/w 0x004 periphe ral reset control 0x000 ta b l e 9 syspllctrl r/w 0x008 system pll control 0x000 ta b l e 1 0 syspllstat r 0x00c system pll status 0x000 ta b l e 11 - - 0x010 - 0x01c reserved - -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 23 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) sysoscctrl r/w 0x020 system oscillator control 0x000 ta b l e 1 2 wdtoscctrl r/w 0x024 watchdog oscillator control 0x000 ta b l e 1 3 ircctrl r/w 0x028 irc control 0x080 ta b l e 1 4 - - 0x02c reserved - - sysrststat r/w 0x030 system re set status register 0x000 ta b l e 1 5 - - 0x034 - 0x03c reserved - - syspllclksel r/w 0x040 system pll clock source select 0x000 ta b l e 1 6 syspllclkuen r/w 0x044 system pll cl ock source updat e enable 0x000 ta b l e 1 7 - - 0x048 - 0x06c reserved - - mainclksel r/w 0x070 main cl ock source select 0x000 ta b l e 1 8 mainclkuen r/w 0x074 main clock source update enable 0x000 ta b l e 1 9 sysahbclkdiv r/w 0x078 system ahb clock divider 0x001 ta b l e 2 0 - - 0x07c reserved - - sysahbclkctrl r/w 0x080 system ahb clock control 0x85f ta b l e 2 1 - - 0x084 - 0x090 reserved - - ssp0clkdiv r/w 0x094 spi0 clock divider 0x000 ta b l e 2 2 uartclkdiv r/w 0x098 uart clock divder 0x000 ta b l e 2 3 ssp1clkdiv r/w 0x09c spi1 clock divder 0x000 ta b l e 2 4 - - 0x0a0-0x0cc reserved - - wdtclksel r/w 0x0d0 wdt clock source select 0x000 ta b l e 2 5 wdtclkuen r/w 0x0d4 wdt clock source update enable 0x000 ta b l e 2 6 wdtclkdiv r/w 0x0d8 wdt clock divider 0x000 ta b l e 2 7 - - 0x0dc reserved - - clkoutclksel r/w 0x0e0 clkout clock source select 0x000 ta b l e 2 8 clkoutuen r/w 0x0e4 clkout clock source update enable 0x000 ta b l e 2 9 clkoutclkdiv r/w 0x0e8 clko ut clock divider 0x000 ta b l e 3 0 - - 0x0ec - 0x0fc reserved - - pioporcap0 r 0x100 por captured pio status 0 user dependent ta b l e 3 1 pioporcap1 r 0x104 por captured pio status 1 user dependent ta b l e 3 2 - r 0x108 - 0x14c reserved - - bodctrl r/w 0x150 bod control 0x000 ta b l e 3 3 systckcal r/w 0x154 system tick counter calibration 0x004 ta b l e 3 4 - - 0x158 - 0x16c reserved - - irqlatency r/w 0x170 iqr delay. allows trade-off between interrupt latency and determinism. 0x10 ta b l e 3 5 nmisrc r/w 0x174 nmi source selection 0x000 ta b l e 3 6 - - 0x178 - 0x1fc reserved - - startaprp0 r/w 0x200 start logic edge control register 0 ta b l e 3 7 starterp0 r/w 0x204 start logic signal enable register 0 ta b l e 3 8 table 7. register overview: system control block (base address 0x4004 8000) ?continued name access address offset description reset value reference
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 24 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) 3.5.1 system memory remap register the system memory remap register selects whether the arm interrupt vectors are read from the boot rom, the flash, or the sram. by default, the flash memory is mapped to address 0x0000 0000. when the map bits in the sysmemremap register are set to 0x0 or 0x1, the boot rom or ram respectively are mapped to the bottom 512 bytes of the memory map (addresses 0x0000 0000 to 0x0000 0200). 3.5.2 peripheral reset control register this register allows software to reset the spi and i2c peripherals. writing a zero to the ssp0/1_rst_n or i2c_rst_n bi ts resets the spi0/1 or i2 c peripheral. writing a one de-asserts the reset. remark: before accessing the spi and i2c peripherals, write a one to this register to ensure that the reset signals to the spi and i2c are de-asserted. startrsrp0clr w 0x208 start logic reset register 0 n/a ta b l e 3 9 startsrp0 r 0x20c start logic status register 0 n/a ta b l e 4 0 - - 0x210 - 0x22c reserved - - pdsleepcfg r/w 0x230 power-down states in deep-sleep mode 0x0000 0000 ta b l e 4 2 pdawakecfg r/w 0x234 power-down states after wake-up from deep-sleep mode 0x0000 edf0 ta b l e 4 3 pdruncfg r/w 0x238 power-down conf iguration register 0x0000 edf0 ta b l e 4 4 - - 0x23c - 0x3f0 reserved - - device_id r 0x3f4 device id re gister 0 for parts lpc1100, lpc1100c, lpc1100l. part dependent ta b l e 4 5 table 7. register overview: system control block (base address 0x4004 8000) ?continued name access address offset description reset value reference table 8. system memory remap register (sysmemremap, address 0x4004 8000) bit description bit symbol value description reset value 1:0 map system memory remap 10 0x0 boot loader mode. interrupt vectors are re-mapped to boot rom. 0x1 user ram mode. interrupt ve ctors are re-mapped to static ram. 0x2 user flash mode. interrupt vectors are not re-mapped and reside in flash. 31:2 - - reserved 0x00
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 25 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) 3.5.3 system pll control register this register connects and enables the system pll and configures the pll multiplier and divider values. the pll accepts an input frequency from 10 mhz to 25 mhz from various clock sources. the input frequen cy is multiplied up to a high frequency, then divided down to provide the actual clock used by the cp u, peripherals, and memories. the pll can produce a clock up to the maximum allowed for the cpu. 3.5.4 system pll status register this register is a read-only register and supplies the pll lock status (see section 3.11.1 ). table 9. peripheral reset control register (presetct rl, address 0x4004 8004) bit description bit symbol value description reset value 0 ssp0_rst_n spi0 reset control 0 0 resets the spi0 peripheral. 1 spi0 reset de-asserted. 1 i2c_rst_n i2c reset control 0 0 resets the i2c peripheral. 1 i2c reset de-asserted. 2 ssp1_rst_n spi1 reset control 0 0 resets the spi1 peripheral. 1 spi1 reset de-asserted. 3 can_rst_n c_can reset control. see section 3.1 for part specific details. 0 0 resets the c_can peripheral. 1 c_can reset de-asserted. 31:4 - - reserved 0x00 table 10. system pll control register (syspllctrl, addres s 0x4004 8008) bit description bit symbol value description reset value 4:0 msel feedback divider value. the division value m is the programmed msel value + 1. 00000: division ratio m = 1 to 11111: division ratio m = 32. 0x000 6:5 psel post divider ratio p. the division ratio is 2 ? p. 0x00 0x0 p = 1 0x1 p = 2 0x2 p = 4 0x3 p = 8 31:7 - - reserved. do not write ones to reserved bits. 0x0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 26 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) 3.5.5 system oscillator control register this register conf igures the freque ncy range for the system oscillator. 3.5.6 watchdog oscillator control register this register configures the watchdog oscillator. the osc illator consists of an analog and a digital part. the analog part contains the osc illator function and gene rates an analog clock (fclkana). with the digital part, the analog output clock (fclkana) can be divided to the required output clock frequency wdt_osc_clk. the analog output frequency (fclkana) can be adjusted with the freqsel bits between 6 00 khz and 4.6 mhz. with the digital part fclkana will be divided (divider ratios = 2, 4,...,64) to wd t_osc_clk using the divsel bits. the output clock fr equency of the watchdog oscillator can be calculated as wdt_osc_clk = fclkana/(2 ? (1 + divsel)) = 9.3 khz to 2.3 mhz (nominal values). remark: any setting of the freqsel bits will yield a fclkana value within ? 40% of the listed frequency value. the wa tchdog oscillator is the clock source with the lowest power consumption. if accura te timing is required, use the irc or system oscillator. remark: the frequency of the watchd og oscillator is undefined after reset. the watchdog oscillator frequency must be programmed by writing to the wdtoscctrl register before using the watchdog oscillator. table 11. system pll status register (sysplls tat, address 0x4004 800c) bit description bit symbol value description reset value 0 lock pll lock status 0x0 0 pll not locked 1 pll locked 31:1 - - reserved 0x00 table 12. system oscillator control register (sysoscctrl , address 0x40 04 8020) bit description bit symbol value description reset value 0 bypass bypass system oscillator 0x0 0 oscillator is not bypassed. 1 bypass enabled. pll input (sys_osc_clk) is fed directly from the xtalin pin bypassing the oscillator. use this mode when using an external clock source instead of the crystal oscillator. 1 freqrange determines frequency range for low-power oscillator. 0x0 0 1 - 20 mhz frequency range. 1 15 - 25 mhz frequency range 31:2 - - reserved 0x00
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 27 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) 3.5.7 internal resonant crystal control register this register is used to trim the on-chip 12 mhz oscillator. th e trim value is factory-preset and written by the boot code on start-up. 3.5.8 system reset status register the sysrststat register shows the source of the latest reset event. write a one to clear the reset. the por event clears all other bits in this register. if any reset signal - for example extrst - remains asserted after the por signal is negated, then its bit is set to detected in this register. table 13. watchdog oscillator control regi ster (wdtoscctrl, address 0x4004 8024) bit description bit symbol value description reset value 4:0 divsel select divider for fclkana. wdt_osc_clk = fclkana/ (2 ? (1 + divsel)) 00000: 2 ? (1 + divsel) = 2 00001: 2 ? (1 + divsel) = 4 to 11111: 2 ? (1 + divsel) = 64 0 8:5 freqsel select watchdog osc illator analog output frequency (fclkana). 0x00 0x1 0.6 mhz 0x2 1.05 mhz 0x3 1.4 mhz 0x4 1.75 mhz 0x5 2.1 mhz 0x6 2.4 mhz 0x7 2.7 mhz 0x8 3.0 mhz 0x9 3.25 mhz 0xa 3.5 mhz 0xb 3.75 mhz 0xc 4.0 mhz 0xd 4.2 mhz 0xe 4.4 mhz 0xf 4.6 mhz 31:9 - - reserved 0x00 table 14. internal resonant crystal control register (ircctrl, address 0x4004 8028) bit description bit symbol description reset value 7:0 trim trim value 0x1000 0000, then flash will reprogram 31:8 - reserved 0x00
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 28 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) the reset value given in ta b l e 1 5 applies to the por reset. 3.5.9 system pll clock source select register this register selects the cl ock source for the system pll. the syspllclkuen register (see section 3.5.10 ) must be toggled from low to high for the update to take effect. remark: when switching clock sources, both cl ocks must be running before the clock source is updated. remark: when using the c_can controller with baudrates above 100 kbit/s, the system oscillator must be selected. table 15. system reset status register (sys rststat, address 0x4004 8030) bit description bit symbol value description reset value 0 por por reset status 0x0 0 no por detected. 1 por detected. writing a one clears this reset. 1 extrst status of the external reset pin. 0x0 0 no reset event detected. 1 reset detected. writing a one clears this reset. 2 wdt status of the watchdog reset 0x0 0 no wdt reset detected. 1 wdt reset detected. writing a one clears this reset. 3 bod status of the brown-out detect reset 0x0 0 no bod reset detected. 1 bod reset detected. writin g a one clears this reset. 4 sysrst status of the software system reset 0x0 0 no system reset detected. 1 system reset detected. writing a one clears this reset. 31:5 - - reserved 0x0 table 16. system pll clock source select register (syspllclksel, address 0x4004 8040) bit description bit symbol value description reset value 1:0 sel system pll clock source 0x00 0x0 irc oscillator 0x1 system oscillator 0x2 reserved 0x3 reserved 31:2 - - reserved 0x00
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 29 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) 3.5.10 system pll clock source update enable register this register updates the clock source of the system pll with the new input clock after the syspllclksel register has been wr itten to. in order for the upd ate to take effect, first write a zero to the sysplluen register and then write a one to sysplluen. remark: when switching clock sources, both cl ocks must be running before the clock source is updated. 3.5.11 main clock source select register this register selects the main system clock which can be either an y input to the system pll, the output from the system pll (sys_pllclkout) , or the watchdog or irc oscillators directly. the main system clock clocks t he core, the peripherals, and the memories. the mainclkuen register (see section 3.5.12 ) must be toggled from low to high for the update to take effect. remark: when switching clock sources, both cl ocks must be running before the clock source is updated. remark: when using the c_can controller with baudrates above 100 kbit/s, the system oscillator must be selected. 3.5.12 main clock source update enable register this register updates the cloc k source of the main clock with the new input clock after the mainclksel register has been written to. in order for the update to take effect, first write a zero to the mainclkuen register and then write a one to mainclkuen. remark: when switching clock sources, both cl ocks must be running before the clock source is updated. table 17. system pll clock source update enable regist er (syspllclkuen, address 0x4004 8044) bit description bit symbol value description reset value 0 ena enable system pll clock source update 0x0 0 no change 1 update clock source 31:1 - - reserved 0x00 table 18. main clock source select regist er (mainclksel, address 0x4004 8070) bit description bit symbol value description reset value 1:0 sel clock source for main clock 0x00 0x0 irc oscillator 0x1 input clock to system pll 0x2 wdt oscillator 0x3 system pll clock out 31:2 - - reserved 0x00
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 30 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) 3.5.13 system ahb clock divider register this register divides the main clock to pr ovide the system clock to the core, memories, and the peripherals. the system clock can be shut down completely by setting the div bits to 0x0. 3.5.14 system ahb cl ock control register the ahbclkctrl register enables the clocks to individual system and peripheral blocks. the system clock (sys_ahb_clk[0], bit 0 in th e ahbclkctrl register) provides the clock for the ahb to apb bridge, the ahb matrix, the arm cortex-m0, the syscon block, and the pmu. this clock cannot be disabled. table 19. main clock source update enable register (mainclkuen, address 0x4004 8074) bit description bit symbol value description reset value 0 ena enable main clo ck source update 0x0 0 no change 1 update clock source 31:1 - - reserved 0x00 table 20. system ahb clock divider regist er (sysahbclkdiv, address 0x4004 8078) bit description bit symbol description reset value 7:0 div system ahb clock divider values 0: system clock disabled. 1: divide by 1. to 255: divide by 255. 0x01 31:8 - reserved 0x00 table 21. system ahb clock control register (sysahbclkctrl, address 0x4004 8080) bit description bit symbol value description reset value 0 sys enables clock for ahb to apb bridge, to the ahb matrix, to the cortex-m0 fclk and hclk, to the syscon, and to the pmu. this bit is read only. 1 0 reserved 1 enable 1 rom enables clock for rom. 1 0 disable 1 enable 2 ram enables clock for ram. 1 0 disable 1 enable 3 flashreg enables clock for flash register interface. 1 0 disabled 1 enabled
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 31 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) 4 flasharray enables clock for flash array access. 1 0 disabled 1 enabled 5 i2c enables clock for i2c. 0 0 disable 1 enable 6 gpio enables clock for gpio. 1 0 disable 1 enable 7 ct16b0 enables clock for 16-bit counter/timer 0. 0 0 disable 1 enable 8 ct16b1 enables clock for 16-bit counter/timer 1. 0 0 disable 1 enable 9 ct32b0 enables clock for 32-bit counter/timer 0. 0 0 disable 1 enable 10 ct32b1 enables clock for 32-bit counter/timer 1. 0 0 disable 1 enable 11 ssp0 enables clock for spi0. 1 0 disable 1 enable 12 uart enables clock for uart. see section 3.1 for part specific details. 0 0 disable 1 enable 13 adc enables clock for adc. 0 0 disable 1 enable 14 - reserved 0 15 wdt enables clock for wdt. 0 0 disable 1 enable 16 iocon enables clock for i/o configuration block. 0 0 disable 1 enable table 21. system ahb clock control register (sysahbclkctrl, address 0x4004 8080) bit description ?continued bit symbol value description reset value
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 32 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) 3.5.15 spi0 clock divider register this register configures the spi0 peripheral clock spi0_pclk. the spi0_pclk can be shut down by setting the div bits to 0x0. 3.5.16 uart clock divider register this register configures the uart periph eral clock uart_pclk. the uart_pclk can be shut down by setting the div bits to 0x0. remark: note that for some parts the uart pins must be configured in the iocon block before the uart clock can be enabled. see section 3.1 for part specific details. 3.5.17 spi1 clock divider register this register configures the spi1 peripheral clock spi1_pclk. the spi1_pclk can be shut down by setting the div bits to 0x0. 17 can enables clock for c_can. see section 3.1 for part specific details. 0 0 disable 1 enable 18 ssp1 enables clock for spi1. 0 0 disable 1 enable 31:19 - - reserved 0x00 table 21. system ahb clock control register (sysahbclkctrl, address 0x4004 8080) bit description ?continued bit symbol value description reset value table 22. spi0 clock divider re gister (ssp0clkdiv, address 0x4004 8094) bit description bit symbol description reset value 7:0 div spi0_pclk clock divider values 0: disable spi0_pclk. 1: divide by 1. to 255: divide by 255. 0x00 31:8 - reserved 0x00 table 23. uart clock divider register (uart clkdiv, address 0x4004 8098) bit description bit symbol description reset value 7:0 div uart_pclk clock divider values 0: disable uart_pclk. 1: divide by 1. to 255: divide by 255. 0x00 31:8 - reserved 0x00
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 33 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) 3.5.18 wdt clock sour ce select register this register selects the clock source for the watchdog timer. th e wdtclkuen register (see section 3.5.19 ) must be toggled from low to high for the update to take effect. remark: when switching clock sources, both cl ocks must be running before the clock source is updated. 3.5.19 wdt clock source update enable register this register updates the clock source of th e watchdog timer with the new input clock after the wdtclksel register has been written to. in order for the update to take effect at the input of the watchdog timer, first write a ze ro to the wdtclkuen register and then write a one to wdtclkuen. remark: when switching clock sources, both cl ocks must be running before the clock source is updated. 3.5.20 wdt clock divider register this register determines the divider values for the watchdog clock wdt_clk. table 24. spi1 clock divider re gister (ssp1clkdiv, address 0x4004 809c) bit description bit symbol description reset value 7:0 div spi1_pclk clock divider values 0: disable spi1_pclk. 1: divide by 1. to 255: divide by 255. 0x00 31:8 - reserved 0x00 table 25. wdt clock source select register (wdtclksel, address 0x4004 80d0) bit description bit symbol value description reset value 1:0 sel wdt clock source 0x00 0x0 irc oscillator 0x1 main clock 0x2 watchdog oscillator 0x3 reserved 31:2 - - reserved 0x00 table 26. wdt clock source update enable register (wdtclkuen, address 0x4004 80d4) bit description bit symbol value description reset value 0 ena enable wdt clock source update 0x0 0 no change 1 update clock source 31:1 - - reserved 0x00
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 34 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) 3.5.21 clkout clock source select register this register configures the clkout_clk signal to be output on the clkout pin. all three oscillators and the main clock can be selected for the clkout_clk clock. the clkoutclkuen register (see section 3.5.22 ) must be toggled from low to high for the update to take effect. remark: when switching clock sources, both cl ocks must be running before the clock source is updated. 3.5.22 clkout clock source update enable register this register updates the clock source of the clkout pin with the new clock after the clkoutclksel register has been written to. in order for the update to take effect at the input of the clkout pin, first write a zero to the clkclkuen register and then write a one to clkclkuen. remark: when switching clock sources, both cl ocks must be running before the clock source is updated. table 27. wdt clock divider register (wdtcl kdiv, address 0x4004 80d8) bit description bit symbol description reset value 7:0 div wdt clock divider values 0: disable wdclk. 1: divide by 1. to 255: divide by 255. 0x00 31:8 - reserved 0x00 table 28. clkout clock source select register (clkoutclksel, address 0x4004 80e0) bit description bit symbol value description reset value 1:0 sel clkout clock source 0x00 0x0 irc oscillator 0x1 system oscillator 0x2 watchdog oscillator 0x3 main clock 31:2 - - reserved 0x00 table 29. clkout clock source update enable register (clkoutuen, address 0x4004 80e4) bit description bit symbol value description reset value 0 ena enable clkout clock source update 0x0 0 no change 1 update clock source 31:1 - - reserved 0x00
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 35 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) 3.5.23 clkout clock divider register this register determines the divider value for the clock output signal on the clkout pin. 3.5.24 por captured pio status register 0 the pioporcap0 register captures the state (high or low) of the pio pins of ports 0,1, and 2 (pins pio2_0 to pio2_7) at power-on-reset. each bit represents the reset state of one gpio pin. this register is a read-only status register. 3.5.25 por captured pio status register 1 the pioporcap1 register captures the state (high or low) of the pio pins of port 2 (pio2_8 to pio2_11) and port 3 at power-on-re set. each bit represents the reset state of one pio pin. this register is a read-only status register. table 30. clkout clock divider registers (clkoutclkdiv, address 0x4004 80e8) bit description bit symbol description reset value 7:0 div clock output divider values 0: disable clkout. 1: divide by 1. to 255: divide by 255. 0x00 31:8 - reserved 0x00 table 31. por captured pio status register s 0 (pioporcap0, address 0x4004 8100) bit description bit symbol description reset value 11:0 cappio0_n raw reset status inpu t pio0_n: pio0_11 to pio0_0 user implementation dependent 23:12 cappio1_n raw reset status inpu t pio1_n: pio1_11 to pio1_0 user implementation dependent 31:24 cappio2_n raw reset status inpu t pio2_n: pio2_7 to pio2_0 user implementation dependent table 32. por captured pio status register s 1 (pioporcap1, address 0x4004 8104) bit description bit symbol description reset value 0 cappio2_8 raw reset stat us input pio2_8 user implementation dependent 1 cappio2_9 raw reset stat us input pio2_9 user implementation dependent 2 cappio2_10 raw reset status input pio2_10 user impl ementation dependent 3 cappio2_11 raw reset status input pio2_11 user implementation dependent 4 cappio3_0 raw reset stat us input pio3_0 user implementation dependent 5 cappio3_1 raw reset stat us input pio3_1 user implementation dependent 6 cappio3_2 raw reset stat us input pio3_2 user implementation dependent 7 cappio3_3 raw reset stat us input pio3_3 user implementation dependent 8 cappio3_4 raw reset stat us input pio3_4 user implementation dependent 9 cappio3_5 raw reset stat us input pio3_5 user implementation dependent 31:10 - reserved -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 36 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) 3.5.26 bod control register the bod control register selects up to four separate threshold values for sending a bod interrupt to the nvic and for forced reset. reset and interrupt threshold values listed are typical values. 3.5.27 system tick count er calibration register this register determin es the value of the syst _calib register (see table 361 ). 3.5.28 irq late ncy register the irqlatency register is an eight-bit regi ster which specifies the minimum number of cycles (0-255) permitted for the system to respond to an interr upt request. the intent of this register is to allow the user to select a trade-off between interrupt response time and determinism. table 33. bod control register (bodctrl, address 0x4004 8150) bit description bit symbol value description reset value 1:0 bodrstlev bod reset level 00 0x0 level 0: the reset assertion threshold voltage is 1.46 v; the reset de-assertion threshold voltage is 1.63 v. 0x1 level 1: the reset assertion threshold voltage is 2.06 v; the reset de-assertion threshold voltage is 2.15 v. 0x2 level 2: the reset assertion threshold voltage is 2.35 v; the reset de-assertion threshold voltage is 2.43 v. 0x3 level 3: the reset assertion threshold voltage is 2.63 v; the reset de-assertion threshold voltage is 2.71 v. 3:2 bodintval bod interrupt level 00 0x0 level 0: reserved. 0x1 level 1:the interrupt assertion threshold voltage is 2.22 v; the interrupt de-assertion threshold voltage is 2.35 v. 0x2 level 2: the interrupt asserti on threshold voltage is 2.52 v; the interrupt de-assertion threshold voltage is 2.66 v. 0x3 level 3: the interrupt asserti on threshold voltage is 2.80 v; the interrupt de-assertion threshold voltage is 2.90 v. 4 bodrstena bod reset enable 0 0 disable reset function. 1 enable reset function. 31:5 - - reserved 0x00 table 34. system tick timer ca libration register (systckcal , address 0x4004 8154) bit description bit symbol description reset value 25:0 cal system tick timer calibration value 0x04 31:26 - reserved 0x00
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 37 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) setting this parameter to a very low valu e (e.g. zero) will guarant ee the best possible interrupt performance but will al so introduce a significant degree of uncertainty and jitter. requiring the system to always ta ke a larger number of cycles (whether it needs it or not) will reduce the amount of uncertainty bu t may not necessarily eliminate it. theoretically, the arm cortex-m0 core should always be able to service an interrupt request within 15 cycles. system factors external to the cpu, however, bus latencies, peripheral response times, etc. can increase the time required to complete a previous instruction before an interrupt can be serv iced. therefore, accurately specifying a minimum number of cycles that will ensure determinism will depend on the application. the default setting for this register is 0x010. 3.5.29 nmi source selection register the nmi source selection register selects a peripheral interrupts as source for the nmi interrupt of the arm cortex-m0 core. for a list of all peripheral interrupts and their irq numbers see table 55 . for a description of the nmi functionality, see section 28.4.3.2 . remark: see section 3.1 for lpc111x parts using this register. note: if the nmisrc register is used to select an interrupt as the source of non-maskable interrupts, and the selected interrupt is enabled, one interrupt request can result in both a non-maskable and a normal interrupt. avoid this situation by disabling the normal interrupt in the nvic, as described in section 28.6.2 . 3.5.30 start logic edge control register 0 the startaprp0 register controls the start lo gic inputs of ports 0 (pio0_0 to pio0_11) and 1 (pio1_0). this register selects a fa lling or rising edge on the corresponding pio input to produce a falling or rising clock edge, respectively, for the start logic (see section 3.10.2 ). every bit in the startaprp0 register contro ls one port input and is connected to one wake-up interrupt in the nvic. bit 0 in the startaprp0 register corresponds to interrupt 0, bit 1 to interrupt 1, etc. (see table 55 ), up to a total of 13 interrupts. table 35. irq latency register (irqlatency, address 0x4004 8170) bit description bit symbol description reset value 7:0 latency 8-bit latency value 0x010 31:8 - reserved - table 36. nmi source selection register (nmisrc, address 0x4004 8174) bit description bit symbol description reset value 4:0 irqno the irq number of the interrupt that acts as the non-maskable interrupt (nmi) if bit 31 in this register is 1. see table 55 for the list of interrupt sources and their irq numbers. 0 30:5 - reserved - 31 nmien write a 1 to this bit to enable the non-maskable interrupt (nmi) source selected by bits 4:0. 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 38 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) remark: each interrupt connected to a start logic input must be enabled in the nvic if the corresponding pio pin is used to wake up the chip from deep-sleep mode. 3.5.31 start logic signal enable register 0 this starterp0 register enables or disables th e start signal bits in the start logic. the bit assignment is identical to table 37 . 3.5.32 start logic reset register 0 writing a one to a bit in the startrsrp0clr r egister resets the start logic state. the bit assignment is identical to ta b l e 3 7 . the start-up logic uses the input signals to generate a clock edge for registering a start signal. this cl ock edge (falling or risi ng) sets the interrupt for waking up from deep-sleep mode. therefore, the start-up logic states must be cleared before being used. table 37. start logic edge control register 0 (startaprp0, address 0x4004 8200) bit description bit symbol description reset value 11:0 aprpio0_n edge select for start logic input pio0_n: pio0_11 to pio0_0 0 = falling edge 1 = rising edge 0x0 12 aprpio1_0 edge select for start logic input pio1_0 0 = falling edge 1 = rising edge 0x0 31:13 - reserved. do not write a 1 to reserved bits in this register. 0x0 table 38. start logic signal enable register 0 (starterp0, address 0x4004 8204) bit description bit symbol description reset value 11:0 erpio0_n enable start signal for start logic input pio0_n: pio0_11 to pio0_0 0 = disabled 1 = enabled 0x0 12 erpio1_0 enable start signal for start logic input pio1_0 0 = disabled 1 = enabled 0x0 31:13 - reserved. do not write a 1 to reserved bits in this register. 0x0 table 39. start logic reset register 0 (startrsrp0clr, address 0x4004 8208) bit description bit symbol description reset value 11:0 rsrpio0_n start signal reset for start logic input pio0_n:pio0_11 to pio0_0 0 = do nothing. 1 = writing 1 resets the start signal. n/a 12 rsrpio1_0 start signal reset for start logic input pio1_0 0 = do nothing. 1 = writing 1 resets the start signal. n/a 31:13 - reserved. do not write a 1 to reserved bits in this register. n/a
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 39 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) 3.5.33 start logic status register 0 this register reflects the status of the e nabled start signal bits. the bit assignment is identical to ta b l e 3 7 . each bit (if enabled) reflects the st ate of the start logic, i.e. whether or not a wake-up signal has been received for a given pin. 3.5.34 deep-sleep mode configuration register this register controls the behavior of the watchdog (w d) oscillator and the bod circuit when the device enters deep-sleep mode. this register must be initialized at least once before entering deep-sleep mode with one of the four values shown in ta b l e 4 1 : remark: failure to initialize and prog ram this register correctly may result in undefined behavior of the microcontroller. the values listed in ta b l e 4 1 are the only values allowed for pdsleepcfg register. to select the appropriate power configur ation for deep-sleep mode, consider the following: ? bod: leaving the bod circuit enabled will pr otect the part from a low voltage event occurring while the part is in deep-sleep mode. however, the bod circuit causes an additional current drain in deep-sleep mode. ? wd oscillator: the watchdog oscillator ca n be left running in deep-sleep mode to provide a clock for the watchdog timer or a general purpose timer if they are needed for timing a wake-up event (see section 3.10.3 for details). in this case, the watchdog oscillator analog output frequency must be set to its lowest value (bits freqsel in the wdtoscctrl = 0001, see ta b l e 1 3 ) and all peripheral clocks other than the timer clock must be disabled in the sysahbclkctrl register (see ta b l e 2 1 ) before entering deep-sleep mode. the watchdog oscillator, if running, co ntributes an additiona l current drain in deep-sleep mode. remark: reserved bits in this register must alwa ys be written as indicated. this register must be initialized correctly before entering deep-sleep mode. table 40. start logic status register 0 (startsrp0, address 0x4004 820c) bit description bit symbol description reset value 11:0 srpio0_n start signal status for start logic input pio0_n: pio0_11 to pio0_0 0 = no start signal received. 1 = start signal pending. n/a 12 srpio1_0 start signal status for start logic input pio1_0 0 = no start signal received. 1 = start signal pending. n/a 31:13 - reserved n/a table 41. allowed values fo r pdsleepcfg register configuration wd oscillator on wd oscillator off bod on pdsleepcfg = 0x0000 18b7 pdsleepcfg = 0x0000 18f7 bod off pdsleepcfg = 0x0000 18bf pdsleepcfg = 0x0000 18ff
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 40 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) 3.5.35 wake-up configuration register the bits in this register determine the state the chip enters when it is waking up from deep-sleep mode. by default, the irc and flash memory are powered and running and the bod circuit is enabled when the chip wakes up from deep-sleep mode. remark: reserved bits must be always written as indicated. table 42. deep-sleep configuration regist er (pdsleepcfg, address 0x4004 8230) bit description bit symbol value description reset value 2:0 notused reserved. always write these bits as 111. 0 3 bod_pd bod power-down control in deep-sleep mode, see table 41 . 0 0 powered 1 powered down 5:4 notused reserved. always write these bits as 11. 0 6 wdtosc_pd watchdog oscillator power control in deep-sleep mode, see table 41 . 0 0 powered 1 powered down 7 notused reserved. always write this bit as 1. 0 10:8 notused reserved. always write these bits as 000. 0 12:11 notused reserved. always write these bits as 11. 0 31:13 - 0 reserved 0 table 43. wake-up configuration register (pdawakecfg, address 0x4004 8234) bit description bit symbol value description reset value 0 ircout_pd irc oscillator ou tput wake-up configuration 0 0 powered 1 powered down 1 irc_pd irc oscillator power-down wake-up configuration 0 0 powered 1 powered down 2 flash_pd flash wake-up configuration 0 0 powered 1 powered down 3 bod_pd bod wake-up configuration 0 0 powered 1 powered down
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 41 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) 3.5.36 power-down configuration register the bits in the pdruncfg register control th e power to the various analog blocks. this register can be written to at any time while the chip is running, and a write will take effect immediately with the exception of th e power-down signal to the irc. to avoid glitches when powering down the irc, the irc clock is automa tically switched off at a clean point. therefore, for the irc a delay is possible before the power-down state takes effect. by default, the irc and flash memory are powered and running and the bod circuit is enabled. remark: reserved bits must be always written as indicated. 4 adc_pd adc wake-up configuration 1 0 powered 1 powered down 5 sysosc_pd system oscillato r wake-up configuration 1 0 powered 1 powered down 6 wdtosc_pd watchdog oscillator wake-up configuration 1 0 powered 1 powered down 7 syspll_pd system pll wake-up configuration 1 0 powered 1 powered down 8 - reserved. always write this bit as 1. 1 9 - reserved. always write this bit as 0. 0 10 - reserved. always write this bit as 1. 1 11 - reserved. always write this bit as 1. 1 12 - reserved. always write this bit as 0. 0 15:13 - reserved. always write these bits as 111. 111 31:16 - - reserved - table 43. wake-up configuration register (pdawakecfg, address 0x4004 8234) bit description ?continued bit symbol value description reset value table 44. power-down configuration regi ster (pdruncfg, address 0x4004 8238) bit description bit symbol value description reset value 0 ircout_pd irc oscillator output power-down 0 0 powered 1 powered down
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 42 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) 3.5.37 device id register this device id register is a read-only re gister and contains the part id for each lpc111x/lpc11cxx part. this register is also read by the isp/iap commands ( section 26.5.11 ). remark: this register returns the part id for parts of the lpc1100, lpc1100c, and lpc1100l series only. use isp/iap to obtain the part id for the lpc1100xl series. the part ids for the various parts are show n in the following list. some parts have two valid part ids. ? lpc1110 ? 0x0a07 102b = lpc1110fd20 1 irc_pd irc oscillator power-down 0 0 powered 1 powered down 2 flash_pd flash power-down 0 0 powered 1 powered down 3 bod_pd bod power-down 0 0 powered 1 powered down 4 adc_pd adc power-down 1 0 powered 1 powered down 5 sysosc_pd system oscillator power-down 1 0 powered 1 powered down 6 wdtosc_pd watchdog oscillator power-down 1 0 powered 1 powered down 7 syspll_pd system pll power-down 1 0 powered 1 powered down 8 - reserved. always write this bit as 1. 1 9 - reserved. always write this bit as 0. 0 10 - reserved. always write this bit as 1. 1 11 - reserved. always write this bit as 1. 1 12 - reserved. always write this bit as 0. 0 15:13 - reserved. always write these bits as 111. 111 31:16 - - reserved - table 44. power-down configuration regi ster (pdruncfg, address 0x4004 8238) bit description ?continued bit symbol value description reset value
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 43 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) ? 0x1a07 102b = lpc1110fd20 ? LPC1111 ? 0x0a16 d02b = LPC1111fdh20/002 ? 0x1a16 d02b = LPC1111fdh20/002 ? 0x041e 502b = LPC1111fhn33/101 ? 0x2516 d02b = LPC1111fhn33/101; LPC1111fhn33/102 ? 0x0416 502b = LPC1111fhn33/201 ? 0x2516 902b = LPC1111fhn33/201; LPC1111fhn33/202 ? lpc1112 ? 0x0a24 902b = lpc1112fd20/102; lpc1112fdh20/102; lpc1112fdh28/102 ? 0x1a24 902b = lpc1112fd20/102; lpc1112fdh20/102; lpc1112fdh28/102 ? 0x042d 502b = lpc1112fhn33/101 ? 0x2524 d02b = lpc1112fhn33/101; lpc1112fhn33/102 ? 0x0425 502b = lpc1112fhn33/201 ? 0x2524 902b = lpc1112fhn33/201; lpc1112fhn33/202; lpc1112fhi33/202; lpc1112fhn24/202 ? lpc1113 ? 0x0434 502b = lpc1113fhn33/201 ? 0x2532 902b = lpc1113fhn33/201; lpc1113fhn33/202 ? 0x0434 102b = lpc1113fhn33/301; lpc1113fbd48/301 ? 0x2532 102b = lpc1113fhn33/301; lp c1113fhn33/302; lpc1113fbd48/301; lpc1113fbd48/302 ? lpc1114 ? 0x0a40 902b = lpc1114fdh28/102; lpc1114fn28/102 ? 0x1a40 902b = lpc1114fdh28/102; lpc1114fn28/102 ? 0x0444 502b = lpc1114fhn33/201 ? 0x2540 902b = lpc1114fhn33/201; lpc1114fhn33/202 ? 0x0444 102b = lpc1114fhn33/301; lpc1114fbd48/301 ? 0x2540 102b = lpc1114fhn33/301; lpc1114fhn33/302; lpc1114fhi33/302; lpc1114fbd48/301; lpc1114fbd48/302; lpc11d14fbd100/302 ? lpc11cxx ? 0x1440 102b = lpc11c14/fbd48/301 ? 0x1431 102b = lpc11c22/fbd48/301 ? 0x1430 102b = lpc11c24/fbd48/301 table 45. device id register (device_id, address 0x4004 83f4) bit description bit symbol description reset value 31:0 deviceid part id numbers for lpc111x/lpc11cxx parts part-dependent
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 44 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) 3.6 reset reset has four sour ces on the lpc111x/ lpc11cxx: the reset pin, watchdog reset, power-on reset (por), and brown out dete ct (bod). in addition, there is an arm software reset. the reset pin is a schmitt trigger input pin. asse rtion of chip reset by any source, once the operating voltage attains a usable level, starts the irc causing reset to remain asserted until the external rese t is de-asserted, the oscillato r is running, and the flash controller has complete d its initialization. on the assertion of any reset source (arm software reset, por, bod reset, external reset, and watchdog reset), the following processes are initiated: 1. the irc starts up. after the irc-start-up time (maximum of 6 ? s on power-up), the irc provides a stable clock output. 2. the flash is powered up. this takes approximately 100 ? s. then the flash initialization sequence is started. 3. the boot code in the rom starts. the boot code performs the boot tasks and may jump to the flash. when the internal reset is removed, the proc essor begins executing at address 0, which is initially the reset vector mapped from the bo ot block. at that point, all of the processor and peripheral registers have been in itialized to predetermined values. 3.7 start-up behavior see figure 9 for the start-up timing after reset. th e irc is the default clock at reset and provides a clean system clock shortly after the supply voltage reaches the threshold value of 1.8 v.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 45 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) 3.8 brown-out detection the lpc111x/lpc11cxx includes up to four le vels for monitoring the voltage on the v dd pin. if this voltage falls below one of the selected levels, the bod asserts an interrupt signal to the nvic. this signal can be enabled for interrupt in the interrupt enable register in the nvic in order to cause a cpu interrupt; if not, software can monitor the signal by reading the nvic status register (see ta b l e 5 5 ). four threshold levels can be selected to cause a forced reset of the chip (see ta b l e 3 3 ). 3.9 power management the lpc111x/lpc11cxx support a variety of power control features. in active mode, when the chip is running, po wer and clocks to selected peripherals can be optimized for power consumption. in addition, there are three special modes of processor power reduction: sleep mode, deep-sleep mode, and deep power-down mode. remark: the debug mode is not supported in sl eep, deep-sleep, or deep power-down modes. 3.9.1 active mode in active mode, the arm cortex-m0 core and memories are clocked by the system clock, and peripherals are clocked by the system clock or a dedicated peripheral clock. fig 9. start-up timing valid threshold = 1.8v processor status v dd irc status internal reset gnd 80 s 101 s boot time user code boot code execution finishes; user code starts irc starts supply ramp-up time 55 s
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 46 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) the chip is in active mode after reset and the default power configuration is determined by the reset values of the pdruncfg and sysahbclkctrl regi sters. the power configuration can be changed during run time. 3.9.1.1 power configuration in active mode power consumption in active mode is determi ned by the following configuration choices: ? the sysahbclkctrl register controls which memories and peripherals are running ( table 21 ). ? the power to various analog blocks (pll, oscillators, the adc, the bod circuit, and the flash block) can be controlled at any time individually through the pdruncfg register ( table 44 ). ? the clock source for the system clock can be selected from the irc (default), the system oscillator, or the watchdog oscillator (see figure 8 and related registers). ? the system clock frequency can be selected by the syspllctrl ( ta b l e 1 0 ) and the sysahbclkdiv register ( ta b l e 2 0 ). ? selected peripherals (uart, spi0/1, wdt) us e individual peripheral clocks with their own clock dividers. the peripheral clocks can be shut down through the corresponding clock divider registers ( ta b l e 2 2 to table 24 ). 3.9.2 sleep mode in sleep mode, the system clock to the arm cortex-m0 core is stopped, and execution of instructions is suspended until either a reset or an enabled interrupt occurs. peripheral functions, if selected to be clocked in the sysahbclkctrl register, continue operation during sleep mode and may generate interrupts to cause the processor to resume execution. sleep mode eliminates dynamic power used by the processor itself, memory systems and their related controllers, and internal buses. the processor state and registers, peripheral registers, and internal sram values are maintained, and the logic levels of the pins remain static. 3.9.2.1 power configuration in sleep mode power consumption in sleep mode is configured by the same settings as in active mode: ? the clock remains running. ? the system clock frequency remains the same as in active mode, but the processor is not clocked. ? analog and digital peripherals are selected as in active mode. 3.9.2.2 programming sleep mode the following steps must be performed to enter sleep mode: 1. the dpden bit in the pcon register must be set to zero ( table 50 ). 2. the sleepdeep bit in the arm cortex-m0 sc r register must be set to zero, see ( table 453 ). 3. use the arm cortex-m0 wait-for-interrupt (wfi) instruction.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 47 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) 3.9.2.3 wake-up from sleep mode sleep mode is exited automatically when an in terrupt enabled by the nvic arrives at the processor or a reset occurs. after wake-up due to an interrupt, the microcontroller returns to its original power config uration defined by the cont ents of the pdruncfg and the sysahbclkdiv registers. if a reset occurs, the microcontr oller enters the default configuration in active mode. 3.9.3 deep-sleep mode in deep-sleep mode, the system clock to the processor is disabled as in sleep mode. all analog blocks are powered down , except for the bod circuit and the watchdog oscillator, which must be sele cted or deselected during de ep-sleep mode in the pdsleepcfg register. deep-sleep mode eliminates all power used by the flash and analog peripherals and all dynamic power used by the processor itself, memory systems and their related controllers, and internal buses. the processor state and registers, peripheral registers, and internal sram values are maintained, and the logic levels of the pins remain static. 3.9.3.1 power configuration in deep-sleep mode power consumption in deep-sleep mode is determined by the deep-sleep power configuration setting in the pdsleepcfg ( ta b l e 4 2 ) register: ? the only clock source available in deep-sl eep mode is the watc hdog oscillator. the watchdog oscillator can be left running in deep-sleep mode if required for timer-controlled wake-up (see section 3.10.3 ). all other clock sources (the irc and system oscillator) and the syst em pll are shut down. the watchdog oscillator analog output frequency must be set to the lowest value of its analog clock output (bits freqsel in the wdtoscctrl = 0001, see ta b l e 1 3 ). ? the bod circuit can be left running in deep-sleep mode if required by the application. ? if the watchdog oscillator is running in deep-sleep mode, only th e watchdog timer or one of the general-purpose timers should be enabled in sysahbclkctrl register to minimize power consumption. 3.9.3.2 programming deep-sleep mode the following steps must be performed to enter deep-sleep mode: 1. the dpden bit in the pcon register must be set to zero ( table 50 ). 2. select the power config uration in deep-sleep mo de in the pdsleepcfg ( ta b l e 4 2 ) register. a. if a timer-controlled wake-up is needed, ensure that the wa tchdog oscillator is powered in the pdruncfg register and swit ch the clock source to wd oscillator in the mainclksel register ( table 18 ). b. if no timer-cont rolled wake-up is needed and the watchdog oscillator is shut down, ensure that the irc is po wered in the pdruncfg regist er and switch the clock source to irc in the mainclksel register ( ta b l e 1 8 ). this ensures that the system clock is shut down glitch-free. 3. select the power configuration after wake-up in the pdawakecfg ( ta b l e 4 3 ) register.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 48 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) 4. if an external pin is used for wake-up, en able and clear the wake-up pin in the start logic registers ( table 37 to ta b l e 4 0 ), and enable the start logic interrupt in the nvic. 5. in the sysahbclkctrl register ( table 21 ), disable all peripherals except counter/timer or wdt if needed. 6. write one to the sleepdeep bit in the arm cortex-m0 scr register ( table 453 ). 7. use the arm wfi instruction. 3.9.3.3 wake-up from deep-sleep mode the microcontroller can wake up from deep-sleep mode in the following ways: ? signal on an external pin. for this purpose, pins pio0_0 to pio0_11 and pio1_0 can be enabled as inputs to the start logic. the start logic does not require any clocks and generates the interrupt if enabled in the nvic to wake up from deep-sleep mode. ? input signal to the start logic created by a match event on one of the general purpose timer external match outputs. the pin ho lding the timer match function must be enabled as start logic input in the nvic, the corresponding timer must be enabled in the sysahbclkctrl register, and the watc hdog oscillator must be running in deep-sleep mode (for details see section 3.10.3 ). ? reset from the bod circuit. in this case , the bod circuit must be enabled in the pdsleepcfg register, and the bod rese t must be enabled in the bodctrl register ( table 33 ). ? reset from the watchdog timer. in this ca se, the watchdog oscillator must be running in deep-sleep mode (see pdsleepcfg register), and the wdt must be enabled in the sysahbclkctrl register. ? a reset signal from the external reset pin. remark: if the watchdog oscillator is running in deep-sleep m ode, its frequency determines the wake-up time causing the wake-up time to be longer than waking up with the irc. 3.9.4 deep power-down mode in deep power-down mode, power and clocks are shut off to the entire chip with the exception of the wakeup pin. during deep power-down mode, the contents of the sram and registers are not retained except for a small amount of data which can be stored in the five 32-bit general purpose registers of the pmu block. all functional pins are tri-st ated in deep power-down mo de except for the wakeup pin. 3.9.4.1 power configuration in deep power-down mode deep power-down mode has no configuratio n options. all clocks, the core, and all peripherals are powere d down. only the wakeup pin is powered. 3.9.4.2 programming deep power-down mode the following steps must be performed to enter deep power-down mode: 1. write one to the dpden bit in the pcon register (see table 50 ).
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 49 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) 2. store data to be retained in the general purpose registers ( ta b l e 5 1 ). 3. write one to the sleepdeep bit in the arm cortex-m0 scr register ( table 453 ). 4. ensure that the irc is po wered by setting bits ircout _pd and irc_pd to zero in the pdruncfg register before entering deep power-down mode. remark: this step is part dependent. see section 3.1 for part specific details. 5. use the arm wfi instruction. remark: the wakeup pin must be pulled high externally before entering deep power-down mode. 3.9.4.3 wake-up from deep power-down mode pulling the wakeup pin low wakes up the lpc111x/lpc11cxx from deep power-down, and the chip goes through the entire reset process ( section 3.6 ). the minimum pulse width for the high-to-low transiti on on the wakeup pin is 50 ns. follow these steps to wake up the chip from deep power-down mode: 1. a wake-up signal is generated when a high-t o-low transition occurs externally on the wakeup pin with a pulse length of at least 50 ns while the part is in deep power-down mode. ? the pmu will turn on the on-chip voltage r egulator. when the core voltage reaches the power-on-reset (por) trip point, a s ystem reset will be trig gered and the chip re-boots. ? all registers except the gpreg0 to gpreg4and pcon will be in their reset state. 2. once the chip has booted, read the deep power-down flag in the pcon register ( ta b l e 5 0 ) to verify that the reset was caused by a wake-up event from deep power-down. 3. clear the deep power-down flag in the pcon register ( ta b l e 5 0 ). 4. (optional) read the stored data in the general purpose registers ( ta b l e 5 1 and ta b l e 5 2 ). 5. set up the pmu for the next deep power-down cycle. remark: the reset pin has no functionality in deep power-down mode. 3.10 deep-sleep mode details 3.10.1 irc oscillator the irc is the only oscillator on the lpc1 11x/lpc11cxx that can always shut down glitch-free. therefore it is recommended that the user switches the clock source to irc before the chip ente rs deep-sleep mode. 3.10.2 start logic the deep-sleep mode is exited when the start logic indicates an interrupt to the arm core. the port pins pio0_0 to pio0_11 and pio1_0 are connected to the start logic and serve as wake-up pins. the user must progra m the start logic registers for each input to set the appropriate edge polarity for the corr esponding wake-up event. furthermore, the interrupts corresponding to each input must be enabled in the nvic. interrupts 0 to 12 in
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 50 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) the nvic correspond to 13 pio pins (see section 3.5.30 ). the start logic does not require a clock to r un because it uses the input signals on the enabled pins to generate a clock edge when enabled. therefore, the start logic signals should be cleared (see ta b l e 3 9 ) before use. the start logic can also be used in active mode to provide a vectored interrupt using the lpc111x/lpc11cxxs input pins. 3.10.3 using the general purpose count er/timers to create a self-wake-up event if enabled in deep-sleep mode through the sysahbclkcfg register, th e counter/timers can count clock cycles of the watchdog os cillator and create a match event when the number of cycles equals a preset matc h value. the match event causes the corresponding match output pin to go high, low, or toggle. the state of the match output pin is also monitored by the start logic and can trigger a wake-up interrupt if that pin is enabled in the nvic and the start logic trig ger is configured accordingly in the start logic edge control register (see ta b l e 3 7 ). the following steps must be performed to configure the counter/timer and create a timed deep-sleep self-wake-up event: 1. configure the port pin as match output in the ioconfig block. select from pins pio0_1 or pio0_8 to pio0_11, which are inputs to the start logic and also hold a match output function. 2. in the corresponding counte r/timer, set the match val ue, and configure the match output for the selected pin. 3. select the watchdog osc illator to run in deep-sleep mode in the pdsleepcfg register. 4. switch the clock source to the watchd og oscillator in the mainclksel register ( ta b l e 1 8 ) and ensure the watchdog oscillator is powered in the pdruncfg register. 5. enable the pin, configure its edge detect function, and reset the start logic in the start logic registers ( table 37 to ta b l e 4 0 ), and enable the interrupt in the nvic. 6. disable all other peripherals in the sysahbclkctrl register. 7. ensure that the dpden bit in the pcon register is set to zero ( ta b l e 5 0 ). 8. write one to the sleepdeep bit in the arm cortex-m0 scr register ( table 453 ). 9. start the counter/timer. 10. use the arm wfi instruction to enter deep-sleep mode. 3.11 system pll fun ctional description the lpc111x/lpc11cxx uses the system pll to create the clocks for the core and peripherals.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 51 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) the block diagram of this pll is shown in figure 10 . the input frequency range is 10 mhz to 25 mhz. the input clock is fed directly to the phase-frequency detector (pfd). this block compares the phase and frequency of its inputs, and generates a control signal when phase and/ or frequency do not match. t he loop filter filters these control signals and drives the current contro lled oscillator (cco), which ge nerates the ma in clock and optionally two additional phases. the cco frequency range is 156 mhz to 320 mhz.these clocks are either divided by 2 ? p by the programmable post divider to create the output clock(s), or are sent directly to the output(s). the main output clock is then divided by m by the programmable feedback divider to generate the feedback clock. the output signal of the phase- frequency detector is also monitored by the lock detector, to signal when the pll has locked on to the input clock. remark: the divider values for p and m must be selected so that the pll output clock frequency fclkout is lower than 100 mhz. 3.11.1 lock detector the lock detector measures the phase differen ce between the rising edges of the input and feedback clocks. only when this difference is smaller than the so called lock criterion for more than eight consecutive i nput clock periods, the lock output switches from low to high. a single too large phase difference immediately resets the counter and causes the lock signal to drop (if it was high). requiring eight phase measurements in a row to be below a certain figure ensures that the lock detector will not indicate lock until both the phase and frequency of the input and feedback clocks are very well aligned. this effectively prevents false lock indications, and thus ensures a glitch free lock signal. 3.11.2 power-down control to reduce the power consumption when th e pll clock is not needed, a power-down mode has been inco rporated. this m ode is enabled by setting the syspll_pd bits to one in the power-down configuration register ( ta b l e 4 4 ). in this mode, th e internal current reference will be turned off, the oscillato r and the phase-fre quency detector will be fig 10. system pll block diagram lock detect pfd fclkout pd analog section pd cd /m /2p cd psel<1:0> pd 2 msel<4:0> 5 irc_osc_clk sys_osc_clk syspllclksel fclkin fcco lock
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 52 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) stopped and the dividers will enter a reset st ate. while in power- down mode, the lock output will be low to indicate that the pll is not in lock. when th e power-down mode is terminated by setting the syspll_pd bits to zero, the pll will resume its normal operation and will make the lock signal high on ce it has regained lo ck on the input clock. 3.11.3 divider ratio programming post divider the division ratio of the post divider is controlled by the psel bits. the division ratio is two times the value of p selected by psel bits as shown in ta b l e 1 0 . this guarantees an output clock with a 50% duty cycle. feedback divider the feedback dividers division ratio is cont rolled by the msel bits. the division ratio between the plls output clock and the input cl ock is the decimal value on msel bits plus one, as specified in table 10 . changing the divider values changing the divider ratio while the pll is running is not recommended. as there is no way to synchronize the change of the msel and psel values with the dividers, the risk exists that the counter will read in an undef ined value, which coul d lead to unwanted spikes or drops in the frequency of the ou tput clock. the recommended way of changing between divider settings is to power down the pl l, adjust the divider settings and then let the pll start up again. 3.11.4 frequency selection the pll frequency equations use the following parameters (also see figure 8 ): 3.11.4.1 normal mode in normal mode the post divider is enabled, giving a 50% duty cycle clock with the following frequency relations: (1) to select the appropriate values for m and p, it is recommended to follow these steps: table 46. pll frequency parameters parameter system pll fclkin frequency of sys_pllclkin (input clock to the system pll) from the syspllclksel multiplexer (see section 3.5.9 ). fcco frequency of the current controll ed oscillator (cco); 156 to 320 mhz. fclkout frequency of sys_pllclkout. fclkout must be < 100 mhz. p system pll post divider ratio; psel bits in syspllctrl (see section 3.5.3 ). m system pll feedback divider regist er; msel bits in syspllctrl (see section 3.5.3 ). fclkout m fclkin ? fcco ?? 2p ? ?? ? ==
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 53 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) 1. specify the input clock frequency fclkin. 2. calculate m to obtain the desir ed output frequency fclkout with m = fclkout / fclkin. 3. find a value so that fcco = 2 ? p ? fclkout. 4. verify that all frequencies and divider values conform to the limits specified in ta b l e 1 0 . 5. ensure that fclkout < 100 mhz. ta b l e 4 7 shows how to configure the pll for a 12 mhz crystal oscillator using the syspllctrl register ( ta b l e 1 0 ). the main clock is equivalent to the system clock if the system clock divider sysahbclk div is set to one (see table 20 ). 3.11.4.2 power-down mode in this mode, the internal current reference is turned off, the oscillator and the phase-frequency detector are stopped, and the dividers enter a reset state. while in power-down mode, the lock output is be low to indicate that the pll is not in lock. when the power-down mode is terminated by setting the syspll_pd bit to zero in the power-down configuration register ( table 44 ), the pll resumes its normal operation and asserts the lock signal high once it has regained lock on the input clock. 3.12 flash memory access depending on the system clock frequency, access to the flash memory can be configured with various access times by writing to th e flashcfg register at address 0x4003 c010. this register is part of the flash configuration block (see figure 6 ). remark: improper setting of this register may result in incorrect operation of the lpc111x/lpc11cxx flash memory. do not ma nipulate the flashcfg register when using power profiles (set_power() and/or set_pll() apis). table 47. pll configuration examples pll input clock sys_pllclkin (fclkin) main clock (fclkout) msel bits table 10 m divider value psel bits table 10 p divider value fcco frequency 12 mhz 48 mhz 00011 4 01 2 192 mhz 12 mhz 36 mhz 00010 3 10 4 288 mhz 12 mhz 24 mhz 00001 2 10 4 192 mhz
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 54 of 543 nxp semiconductors um10398 chapter 3: lpc111x/lpc11cxx system configuration (syscon) table 48. flash configuration register (flas hcfg, address 0x4003 c010) bit description bit symbol value description reset value 1:0 flashtim flash memory access ti me. flashtim +1 is equal to the number of system clocks used for flash access. 10 00 1 system clock flash access time (for system clock frequencies of up to 20 mhz). 01 2 system clocks flash acce ss time (for system clock frequencies of up to 40 mhz). 10 3 system clocks flash ac cess time (for system clock frequencies of up to 50 mhz). 11 reserved. 31:2 - - reserved. user software must not change the value of these bits. bits 31:2 must be written back exactly as read . -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 55 of 543 4.1 how to read this chapter remark: for parts lpc11(d)1x/102/202/302, also refer to chapter 5 for power control. 4.2 introduction the pmu controls the deep power-down mode. four general purpose register in the pmu can be used to retain data during deep power-down mode. 4.3 register description 4.3.1 power control register the power control register selects whether one of the arm cortex-m0 controlled power-down modes (sleep mode or deep-sleep mode) or the deep power-down mode is entered and provides the flags for sleep or deep-sleep modes and deep power-down modes respectively. see section 3.9 for details on how to enter the power-down modes. um10398 chapter 4: lpc111x/lpc11cxx power monitor unit (pmu) rev. 12.1 ? 7 august 2013 user manual table 49. register overview: pmu (base address 0x4003 8000) name access address offset description reset value pcon r/w 0x000 power co ntrol register 0x0 gpreg0 r/w 0x004 general purpose register 0 0x0 gpreg1 r/w 0x008 general purpose register 1 0x0 gpreg2 r/w 0x00c general purpose register 2 0x0 gpreg3 r/w 0x010 general purpose register 3 0x0 gpreg4 r/w 0x014 general purpose register 4 0x0 table 50. power control register (pcon, address 0x4003 8000) bit description bit symbol value description reset value 0 - - reserved. do not write 1 to this bit. 0x0 1 dpden deep power-down mode enable 0 0 arm wfi will enter sleep or deep-sleep mode (clock to arm cortex-m0 core turned off). 1 arm wfi will enter deep-power down mode (arm cortex-m0 core powered-down). 7:2 - - reserved. do not writ e ones to this bit. 0x0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 56 of 543 nxp semiconductors um10398 chapter 4: lpc111x/lpc11cxx power monitor unit (pmu) 4.3.2 general purpose registers 0 to 3 the general purpose registers retain data through the deep power-down mode when power is still applied to the v dd pin but the chip has entered deep power-down mode. only a cold boot when all power has been completely re moved from the chip will reset the general purpose registers. 4.3.3 general purpose register 4 the general purpose register 4 retains data through the deep power-down mode when power is still applied to the v dd pin but the chip has entered deep power-down mode. only a cold boot, when a ll power has been completely re moved from the chip, will reset the general purpose registers. remark: if there is a possibility that the external voltage applied on pin v dd drops below 2.2 v during deep power-down, the hysteres is of the wakeup input pin has to be disabled in this register before entering deep power-down mode in order for the chip to wake up. 8 sleepflag sleep mode flag 0 0 read: no power-down mode entered. lpc111x/lpc11cxx is in active mode. write: no effect. 1 read: sleep/deep-sleep or deep power-down mode entered. write: writing a 1 clears the sleepflag bit to 0. 10:9 - - reserved. do not write ones to this bit. 0x0 11 dpdflag deep power-down flag 0x0 0 read: deep power-down mode not entered. write: no effect. 0x0 1 read: deep power-down mode entered. write: clear the deep power-down flag. 0x0 31:12 - - reserved. do not wr ite ones to this bit. 0x0 table 50. power control register (pcon, address 0x4003 8000) bit description ?continued bit symbol value description reset value table 51. general purpose registers 0 to 3 (gpreg0 - gpreg3, address 0x4003 8004 to 0x4003 8010) bit description bit symbol description reset value 31:0 gpdata data retained during deep power-down mode. 0x0 table 52. general purpose register 4 (gpr eg4, address 0x4003 8014) bit description bit symbol value description reset value 9:0 - - reserved. do not write ones to this bit. 0x0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 57 of 543 nxp semiconductors um10398 chapter 4: lpc111x/lpc11cxx power monitor unit (pmu) 4.4 functional description for details of entering and exiting deep power-down mode, see section 3.9.4 . 10 wakeuphys wakeup pin hysteresis enable 0x0 1 hysteresis for wakeup pin enabled. 0 hysteresis for wakup pin disabled. 31:11 gpdata data retained during deep power-down mode. 0x0 table 52. general purpose register 4 (gpr eg4, address 0x4003 8014) bit description bit symbol value description reset value
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 58 of 543 5.1 how to read this chapter the power profiles are available for parts lpc11(d)1x/102/202/302 only (lpc1100l series). 5.2 features ? includes rom-based application services ? power management services ? clocking services 5.3 description the api calls to the rom are performed by executing functions which are pointed by a pointer within the ro m driver table. figure 11 shows the pointer structure used to call the power profiles api. um10398 chapter 5: lpc111x/lpc11cxx power profiles rev. 12.1 ? 7 august 2013 user manual fig 11. power profiles pointer structure ptr to rom driver table ptr to device table 2 ptr to device table 1 ptr to device table 0 ptr to device table n set_pll set_power ptr to function 2 ptr to function 0 ptr to function 1 ptr to function n power api function table device n rom driver table 0x1fff 2004 0x1fff 1ff8 0x1fff 1ffc 0x1fff 2000 0x1fff 2004 ptr to powerapi table
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 59 of 543 nxp semiconductors um10398 chapter 5: lpc111x/lpc11cxx power profiles 5.4 definitions the following elements have to be defined in an application that uses the power profiles: typedef struct _pwrd { void (*set_pll)(unsigned int cmd[], unsigned int resp[]); void (*set_power)(unsigned int cmd[], unsigned int resp[]); } pwrd; typedef struct _rom { const pwrd * pwrd; } rom; rom ** rom = (rom **) (0x1fff1ff8 + 3 * sizeof(rom**)); unsigned int command[4], result[2]; 5.5 clocking routine 5.5.1 set_pll this routine sets up the system pll accordin g to the calling argument s. if the expected clock can be obtained by simply dividing the system pll input, bypasses the pll to lower system power consumption. remark: before this routine is invoked, the pll clock source (irc/system oscillator) must be selected ( table 16 ), the main clock source must be set to the input clock to the system pll ( table 18 ) and the system/ahb clock divider must be set to 1 ( ta b l e 2 0 ). attempts to find a pll setup that matches the calling parameters. once a combination of a feedback divider value (syspllctrl, m), a post divider ratio (syspllctrl, p) and the system/ahb clock divider (sysahbclkdiv) is found, applies the selected values and switches the main clock source selection to the system pll clock out (if necessary). fig 12. lpc111x/102/202/302 clock configuration for power api use sys pll irc_osc_clk sys_osc_clk irc_osc_clk wdt_osc_clk mainclksel syspllclksel clock divider sysahbclkctrl[1] (rom enable) sysahbclkctrl[18] (spi1 enable) clock divider peripherals main clock system clock sys_pllclkin sys_pllclkout 7 arm cortex-m0 rom spi1 sysahbclkdiv
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 60 of 543 nxp semiconductors um10398 chapter 5: lpc111x/lpc11cxx power profiles the routine returns a result code that indi cates if the system pl l was successfully set (pll_cmd_success) or not (in wh ich case the result code id entifies what went wrong). the current system frequency value is also returned. the application should use this information to adjust other clocks in the de vice (the ssp, uart, and wdt clocks, and/or clockout). the following definitions are needed when making set_pll power routine calls: /* set_pll mode options */ #define cpu_freq_equ 0 #define cpu_freq_lte 1 #define cpu_freq_gte 2 #define cpu_freq_approx 3 /* set_pll result0 options */ #define pll_cmd_success 0 #define pll_in va l i d _ f r e q 1 #define pll_invalid_mode 2 #define pll_freq_not_found 3 #define pll_not_locked 4 for a simplified clock configuration scheme see figure 12 . for more details see figure 8 . 5.5.1.1 param0: system pll input frequency and param1: expected system clock set_pll looks for a setup in which the system pll clock does not exceed 50 mhz. it easily finds a solution when the ratio between th e expected system clock and the system pll input frequency is an integer value, but it can also find solutions in other cases. the system pll input frequency ( ) must be between 10000 to 25000 khz (10 mhz to 25 mhz) inclusive. the expected system clock ( ) must be between 1 and 50000 khz inclusive. if either of these requirements is not met, returns pll_invalid_freq and returns as since the pll setting is unchanged. 5.5.1.2 param2: mode the first priority of is to find a setup that generates the system clock at exactly the rate specified in . if it is unlikely that an exact match can be found, input parameter mode ( ) should be used to specify if the actu al system clock can be less than or equal, greater than or equal or approximatel y the value specified as the expected system clock ( ). a call specifying cpu_freq_equ will only succeed if th e pll can output exactly the frequency requested in . table 53. set_pll routine routine set_pll input param0: system pll input frequency (in khz) param1: expected system clock (in khz) param2: mode (cpu_freq_equ, cpu_ freq_lte, cpu_freq_gte, cpu_freq_approx) param3: system pll lock time-out result result0: pll_cmd_success | pll_invalid_ freq | pll_invalid_mode | pll_freq_not_found | pll_not_locked result1: system clock (in khz)
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 61 of 543 nxp semiconductors um10398 chapter 5: lpc111x/lpc11cxx power profiles cpu_freq_lte can be used if the requested frequency should not be exceeded (such as overall current consumption and/or power budget reasons). cpu_freq_gte helps applications that nee d a minimum level of cpu processing capabilities. cpu_freq_approx results in a system clock that is as close as possible to the requested value (it may be greater than or less than the requested value). if an illegal mode is specified, set_pll returns pll_invalid_mode. if the expected system clock is out of the range supported by this routine, set_pll returns pll_freq_not_found. in these cases the current pll setting is not changed and param0 is returned as result1 . 5.5.1.3 param3: system pll lock time-out it should take no more than 100 ? s for the system pll to lock if a valid configuration is selected. if param3 is zero, set_pll will wait indefinitely for t he pll to lock. a non-zero value indicates how many times the code will check for a successful pll lock event before it returns pll_not_locked. in this case the pll settings are unchanged and param0 is returned as result1 . remark: the time it takes the pll to lock depends on the selected pll input clock source (irc/system oscillator) and its characteristics. the selected source can experience more or less jitter depending on the operating conditions such as power supply and/or ambient temperature. this is why it is suggested that when a good known clock source is used and a pll_not_locked response is received , the set_pll routine should be invoked several ti mes before declaring the selected pll clock source invalid. hint: setting param3 equal to the system pll frequency [hz] divided by 10000 will provide more than enough pll lock-polling cycles. 5.5.1.4 code examples the following examples illustrate some of the features of set_pll discussed above. 5.5.1.4.1 invalid frequency (device maximum clock rate exceeded) command[0] = 12000; command[1] = 60000; command[2] = cpu_freq_equ; command[3] = 0; (*rom)->pwrd->set_pll(command, result); the above code specifies a 12 mhz pll in put clock and a system clock of exactly 60 mhz. the application was ready to infinitely wait for the pll to lock. but the expected system clock of 60 mhz exceeds the maximum of 50 mhz. therefore set_pll returns pll_invalid_freq in result[0] and 12000 in result[1] without changing the pll settings. 5.5.1.4.2 invalid frequency selection (system clock divider restrictions) command[0] = 12000; command[1] = 40; command[2] = cpu_freq_lte;
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 62 of 543 nxp semiconductors um10398 chapter 5: lpc111x/lpc11cxx power profiles command[3] = 0; (*rom)->pwrd->set_pll(command, result); the above code specifies a 12 mhz pll input clock, a system clock of no more than 40 khz and no time-out while wa iting for the pll to lock. since the maximum divider value for the system clock is 255 and running at 40 khz would need a divide by value of 300, returns pll_invalid_freq in and 12000 in without changing the pll settings. 5.5.1.4.3 exact solution cannot be found (pll) command[0] = 12000; command[1] = 25000; command[2] = cpu_freq_equ; command[3] = 0; (*rom)->pwrd->set_pll(command, result); the above code specifies a 12 mhz pll in put clock and a system clock of exactly 25 mhz. the application was ready to infinitely wait for the pll to lock. since there is no valid pll setup within earlie r mentioned restrictions, returns pll_freq_not_found in and 12000 in without changing the pll settings. 5.5.1.4.4 system clock less than or equal to the expected value command[0] = 12000; command[1] = 25000; command[2] = cpu_freq_lte; command[3] = 0; (*rom)->pwrd->set_pll(command, result); the above code specifies a 12 mhz pll input clock, a system clock of no more than 25 mhz and no locking time-out. returns pll_cmd_success in and 24000 in . the new system clock is 24 mhz. 5.5.1.4.5 system clock greater than or equal to the expected value command[0] = 12000; command[1] = 25000; command[2] = cpu_freq_gte; command[3] = 0; (*rom)->pwrd->set_pll(command, result); the above code specifies a 12 mhz pll input clock, a system clock of at least 25 mhz and no locking time-out. returns pll_cmd_success in and 36000 in . the new system clock is 36 mhz. 5.5.1.4.6 system clock approximately equal to the expected value command[0] = 12000; command[1] = 16500; command[2] = cpu_freq_approx; command[3] = 0; (*rom)->pwrd->set_pll(command, result);
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 63 of 543 nxp semiconductors um10398 chapter 5: lpc111x/lpc11cxx power profiles the above code specifies a 12 mhz pll input clock, a system clock of approximately 16.5 mhz and no locking time-out. set_pll returns pll_cmd_success in result[0] and 16000 in result[1] . the new system clock is 16 mhz. 5.6 power routine 5.6.1 set_power this routine configures the de vices internal power control settings according to the calling arguments. the goal is to reduce active pow er consumption while ma intaining the feature of interest to the application close to its optimum. remark: the set_power routine was designed for systems employing the configuration of sysahbclkdiv = 1 (system clock divider register, see ta b l e 2 0 and figure 12 ). using this routine in an application with the system cl ock divider not equal to 1 might not improve microcontrollers performance as much as in setups when the main clock and the system clock are running at the same rate. set_power returns a result code that reports whether the power setting was successfully changed or not. fig 13. power profiles usage using power profiles and changing system clock current_clock, new_clock , new_mode use power routine call to change mode to default use either clocking routine call or custom code to change system clock from current_clock to new _clock use power routine call to change mode to new_mode end
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 64 of 543 nxp semiconductors um10398 chapter 5: lpc111x/lpc11cxx power profiles the following definitions are needed for set_power routine calls: /* set_power mode options */ #define pwr_default 0 #define pwr_cpu_performance 1 #define pwr_efficiency 2 #define pwr_low_current 3 /* set_power result0 options */ #define pwr_cmd_success 0 #define pwr_invalid_freq 1 #define pwr_invalid_mode 2 for a simplified clock configuration scheme see figure 12 . for more details see figure 8 . 5.6.1.1 param0: main clock the main clock is the clock rate the microcontroller uses to source the systems and the peripherals clock. it is configured by either a successful execution of the clocking routine call or a similar code provided by the user. this operand must be an integer between 1 to 50 mhz inclusive. if a value out of this range is supplied, returns pwr_invalid_freq and does not change the power control system. 5.6.1.2 param1: mode the input parameter mode ( ) specifies one of four available power settings. if an illegal selection is provided, returns pwr_invalid_mode and does not change the power control system. pwr_default keeps the device in a baseline power setting similar to its reset state. pwr_cpu_performance configures the microc ontroller so that it can provide more processing capability to the application. cp u performance is 30% be tter than the default option. pwr_efficiency setting was designed to find a balance between active current and the cpus ability to execute code and process data. in this mode the device outperforms the default mode both in terms of providing higher cpu performance and lowering active current. pwr_low_current is intended for those solutions that focus on lowering power consumption rather than cpu performance. 5.6.1.3 param2: system clock the system clock is the clock rate at whic h the microcontroller co re is running when is called. this parameter is an integer between from 1 and 50 mhz inclusive. table 54. set_power routine routine set_power input param0: main clock (in mhz) param1: mode (pwr_default, pwr_cpu_performance, pwr_ efficiency, pwr_low_current) param2: system clock (in mhz) result result0: pwr_cmd_success | pw r_invalid_freq | pwr_invalid_mode
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 65 of 543 nxp semiconductors um10398 chapter 5: lpc111x/lpc11cxx power profiles 5.6.1.4 code examples the following examples illu strate some of the set_power features discussed above. 5.6.1.4.1 invalid frequency (device maximum clock rate exceeded) command[0] = 60; command[1] = pwr_cpu_performance; command[2] = 60; (*rom)->pwrd->set_powe r(command, result); the above setup would be used in a system running at the main and system clock of 60 mhz, with a need for maximum cpu proces sing power. since the specified 60 mhz clock is above the 50 mhz maximum, set_power returns pwr_invalid_freq in result[0] without changing anything in the existing power setup. 5.6.1.4.2 an applicable power setup command[0] = 24; command[1] = pwr_cpu_efficiency; command[2] = 24; (*rom)->pwrd->set_powe r(command, result); the above code specifies that an application is running at the main and system clock of 24 mhz with emphasis on efficiency. set_power returns pwr_cmd_success in result[0] after configuring the microcontroller s internal power control features.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 66 of 543 6.1 how to read this chapter the c_can controller interrupt is available on parts lpc11cxx only. 6.2 introduction the nested vectored in terrupt controller (nvic) is an integral part of the cortex-m0. the tight coupling to the cpu allows for low interr upt latency and efficient processing of late arriving interrupts. 6.3 features ? nested vectored interrupt controller that is an integral part of the arm cortex-m0 ? tightly coupled interrupt controller provides low interrupt latency ? controls system exceptions and peripheral interrupts ? the nvic supports 32 vectored interrupts ? 4 programmable interrupt priority levels with hardware priority level masking ? software interr upt generation 6.4 interrupt sources ta b l e 5 5 lists the interrupt sources for each peripheral function. each peripheral device may have one or more interrupt lines to the vectored interrupt controller. each line may represent more than one interrupt source. there is no significance or priority about what line is connected where, except for certain standards from arm. see section 28.6.2 for the nvic register bit descriptions. um10398 chapter 6: lpc111x/lpc11cxx ne sted vectored interrupt controller (nvic) rev. 12.1 ? 7 august 2013 user manual table 55. connection of interrupt sources to the vectored interrupt controller exception number vector offset function flag(s) 12 to 0 start logic wake-up interrupts each interrupt is connected to a pio input pin serving as wake-up pin from deep-sleep mode; interrupt 0 to 11 correspond to pio0_0 to pio0_11 and interrupt 12 corresponds to pio1_0; see section 3.5.30 . 13 c_can c_can interrupt 14 spi/ssp1 tx fifo half empty rx fifo half full rx timeout rx overrun 15 i 2 c si (state change)
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 67 of 543 nxp semiconductors um10398 chapter 6: lpc111x/lpc11cxx nested vectored interrupt controller 16 ct16b0 match 0 - 2 capture 0 17 ct16b1 match 0 - 1 capture 0 18 ct32b0 match 0 - 3 capture 0 19 ct32b1 match 0 - 3 capture 0 20 spi/ssp0 tx fifo half empty rx fifo half full rx timeout rx overrun 21 uart rx line status (rls) transmit holding register empty (thre) rx data available (rda) character time-out indicator (cti) end of auto-baud (abeo) auto-baud time-out (abto) 22 - reserved 23 - reserved 24 adc a/d converter end of conversion 25 wdt watchdog interrupt (wdint) 26 bod brown-out detect 27 - reserved 28 pio_3 gpio interrupt status of port 3 29 pio_2 gpio interrupt status of port 2 30 pio_1 gpio interrupt status of port 1 31 pio_0 gpio interrupt status of port 0 table 55. connection of interrupt sources to the vectored interrupt controller exception number vector offset function flag(s)
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 68 of 543 7.1 how to read this chapter remark: this chapter applies to parts in the following series (see ta b l e 1 ): ? lpc1100 ? lpc1100l ? lpc1100c ? lpc11d14 pin configuration the implementation of the i/o configuration registers varies for different lpc111x/lpc11cxx parts and packages. table 57 shows which iocon registers are used on the different packages. c_can pins ? for the lpc11c12/c14, functions pio3_4 and pio3_5 are not available. instead, two pins are dedicated to the c_can re ceive and transmit functions (see ta b l e 5 7 ) without pull-up or pull-down resistors. the c_can pins have no programmable pin configuration. ? for the lpc11c22/c24, pins pio1_9, pio2_4, pi o2_5, and pio2_9 are not available and are replaced by the on-chip can transceiver pins. the can transceiver pins have no programmable pin configuration. pseudo open-drain function for the lpc11(d)1x/102/202/302, a pseudo open-drain mode can be selected in the iocon registers for each digital pin except the i2c pins (see figure 14 ). the open-drain mode is not available for the lpc111x/101/201/301 parts. pull-up level if the pull-up resistor is enabled (default), all non-i2c pins are pulled up to 2.6 v for lpc111x/101/201/301 parts and pulled up to 3.3 v for lpc11cxx parts and lpc111x/102/202/302 (v dd = 3.3 v). 7.2 features the i/o configuration registers control the el ectrical characterist ics of the pads. the following features are programmable: ? pin function. ? internal pull-up/pull-down resistor or bus keeper function. ? hysteresis. ? analog input or digital mode for pads hosting the adc inputs. ? i 2 c mode for pads hosting the i 2 c-bus function. um10398 chapter 7: lpc1100/lpc1100c /lpc1100l series: i/o configuration (ioconfig) rev. 12.1 ? 7 august 2013 user manual
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 69 of 543 nxp semiconductors um10398 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration ? pseudo open-drain mode for non-i2c pins (see section 7.1 for part specific details). 7.3 general description the iocon registers control the function (gpi o or peripheral function), the input mode, and the hysteresis of all pion_m pins. in addition, the i 2 c-bus pins can be configured for different i 2 c-bus modes. if a pin is used as input pin for the adc, an analog input mode can be selected. 7.3.1 pin function the func bits in the iocon registers can be set to gpio (func = 000) or to a peripheral function. if the pins are gpio pins, the gpiondir registers determine whether the pin is configured as an input or output (see section 12.3.2 ). for any peripheral function, the pin direction is controlled automa tically depending on the pins functionality. the gpiondir registers have no effect for peripheral functions. for open-drain mode, see section 7.1 . fig 14. standard i/o pin configuration pin v dd v dd esd v ss esd strong pull-up strong pull-down v dd weak pull-up weak pull-down open-drain enable output enable repeater mode enable pull-up enable pull-down enable data output data input analog input select analog input 002aah159 pin configured as digital output driver pin configured as digital input pin configured as analog input
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 70 of 543 nxp semiconductors um10398 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration 7.3.2 pin mode the mode bits in the iocon re gister allow the selection of on-chip pull-up or pull-down resistors for each pin or select the repeater mode. the possible on-chip resistor configurations are pull-up enabled, pull-down enabled, or no pull-up/pull-down. the default value is pull-up enabled. see section 7.1 for part specific details. the repeater mode enables the pull-up resistor if the pin is at a logic high and enables the pull-down resistor if the pin is at a logic low. this causes the pin to retain its last known state if it is configured as an input a nd is not driven externally. the state retention is not applicable to the deep power-down mode. repeater mode may typically be used to prevent a pin from floating (and potentially us ing significant power if it floats to an indeterminate state) if it is temporarily not driven. 7.3.3 hysteresis the input buffer for digital functions can be configured with hysteresis or as plain buffer through the iocon registers (see the lpc111x and lpc11cx data sheets for details). if the external pad supply voltage v dd is between 2.5 v and 3.6 v, the hysteresis buffer can be enabled or disabled. if v dd is below 2.5 v, the hysteresis buffer must be disabled to use the pin in input mode. 7.3.4 a/d-mode in a/d-mode, the digital receiver is disconne cted to obtain an accu rate input voltage for analog-to-digital conversions. this mode can be selected in those iocon registers that control pins with an analog function. hys and mode should be zero when ad mode is used. for pins without analog functions, th e a/d-mode setting has no effect. 7.3.5 i 2 c mode if the i 2 c function is selected by the func bits of registers iocon_pio0_4 ( ta b l e 6 8 ) and iocon_pio0_5 ( ta b l e 6 9 ), then the i 2 c-bus pins can be configured for different i 2 c-modes: ? standard mode/fast-mode i 2 c with input glitch filter (this includes an open-drain output according to the i 2 c-bus specification). ? fast-mode plus with input glitch filter (this includes an open-drain output according to the i 2 c-bus specification). in this mode, th e pins function as high-current sinks. ? standard open-drain i/o functionality without input filter. remark: either standard mode/fast-mode i 2 c or standard i/o functionality should be selected if the pin is used as gpio pin.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 71 of 543 nxp semiconductors um10398 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration 7.3.6 open-drain mode when output is selected, either by selecting a special function in the func field, or by selecting gpio function for a pin having a 1 in its gpiodir register, a 1 in the od bit selects open-drain operation, that is, a 1 disables the high-drive transistor. this option has no effect on the primary i 2 c pins. remark: the open-drain mode is not available on all parts (see section 7.1 ). 7.4 register description the i/o configuration registers control the pi o port pins, the inputs and outputs of all peripherals and functional blocks, the i 2 c-bus pins, and the adc input pins. each port pin pion_m has one iocon register assigned to control the pins function and electrical characteristics. some input functions (sck0, dsr , dcd , and ri ) are multiplexed to several physical pins. the iocon_loc registers select the pin location for each of these functions. remark: the iocon registers are listed in order of their memory locations in ta b l e 5 6 , which correspond to the order of their physical pin numbers in the lqfp48 package starting at the upper left corner with pin 1 (pio2_6). see table 57 for a listing of iocon registers ordered by port number. the iocon location registers are used to select a physical pin for multiplexed functions. remark: note that once the pin location has be en selected, the function still must be configured in the corresponding iocon registers for the function to be usable on that pin. table 56. register overview: i/o configuration (base address 0x4004 4000) name access address offset description reset value reference iocon_pio2_6 r/w 0x000 i/o configuration for pin pio2_6 0xd0 ta b l e 5 8 - r/w 0x004 reserved - - iocon_pio2_0 r/w 0x008 i/o configuration for pin pio2_0/dtr /ssel1 0xd0 ta b l e 5 9 iocon_reset_pio0_0 r/w 0x00c i/o configuration for pin reset /pio0_0 0xd0 ta b l e 6 0 iocon_pio0_1 r/w 0x010 i/o configuration for pin pio0_1/clkout/ct32b0_mat2 0xd0 ta b l e 6 1 iocon_pio1_8 r/w 0x014 i/o configuration for pin pio1_8/ct16b1_cap0 0xd0 ta b l e 6 2 - r/w 0x018 reserved - - iocon_pio0_2 r/w 0x01c i/o configuration for pin pio0_2/ssel0/ct16b0_cap0 0xd0 ta b l e 6 3 iocon_pio2_7 r/w 0x020 i/o configuration for pin pio2_7 0xd0 ta b l e 6 4 iocon_pio2_8 r/w 0x024 i/o configuration for pin pio2_8 0xd0 ta b l e 6 5 iocon_pio2_1 r/w 0x028 i/o configuration for pin pio2_1/dsr/ sck1 0xd0 ta b l e 6 6 iocon_pio0_3 r/w 0x02c i/o configuration for pin pio0_3 0xd0 ta b l e 6 7 iocon_pio0_4 r/w 0x030 i/o configuration for pin pio0_4/scl 0x00 ta b l e 6 8
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 72 of 543 nxp semiconductors um10398 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration iocon_pio0_5 r/w 0x034 i/o configuration for pin pio0_5/sda 0x00 ta b l e 6 9 iocon_pio1_9 r/w 0x038 i/o configuration for pin pio1_9/ct16b1_mat0 0xd0 ta b l e 7 0 iocon_pio3_4 r/w 0x03c i/o configuration for pin pio3_4 0xd0 ta b l e 7 1 iocon_pio2_4 r/w 0x040 i/o configuration for pin pio2_4 0xd0 ta b l e 7 2 iocon_pio2_5 r/w 0x044 i/o configuration for pin pio2_5 0xd0 ta b l e 7 3 iocon_pio3_5 r/w 0x048 i/o configuration for pin pio3_5 0xd0 ta b l e 7 4 iocon_pio0_6 r/w 0x04c i/o configuration for pin pio0_6/sck0 0xd0 ta b l e 7 5 iocon_pio0_7 r/w 0x050 i/o configuration for pin pio0_7/cts 0xd0 ta b l e 7 6 iocon_pio2_9 r/w 0x054 i/o configuration for pin pio2_9 0xd0 ta b l e 7 7 iocon_pio2_10 r/w 0x058 i/o configuration for pin pio2_10 0xd0 ta b l e 7 8 iocon_pio2_2 r/w 0x05c i/o configuration for pin pio2_2/dcd /miso1 0xd0 ta b l e 7 9 iocon_pio0_8 r/w 0x060 i/o configuration for pin pio0_8/miso0/ct16b0_mat0 0xd0 ta b l e 8 0 iocon_pio0_9 r/w 0x064 i/o configuration for pin pio0_9/mosi0/ct16b0_mat1 0xd0 ta b l e 8 1 iocon_swclk_pio0_10 r/w 0x068 i/o configuration for pin swclk/pio0_10/ sck0/ct16b0_mat2 0xd0 ta b l e 8 2 iocon_pio1_10 r/w 0x06c i/o configuration for pin pio1_10/ad6/ct16b1_mat1 0xd0 ta b l e 8 3 iocon_pio2_11 r/w 0x070 i/o configuration for pin pio2_11/sck0 0xd0 ta b l e 8 4 iocon_r_pio0_11 r/w 0x074 i/o configuration for pin r/pio0_11/ad0/ct32b0_mat3 0xd0 ta b l e 8 5 iocon_r_pio1_0 r/w 0x078 i/o configuration for pin r/pio1_0/ad1/ct32b1_cap0 0xd0 ta b l e 8 6 iocon_r_pio1_1 r/w 0x07c i/o configuration for pin r/pio1_1/ad2/ct32b1_mat0 0xd0 ta b l e 8 7 iocon_r_pio1_2 r/w 0x080 i/o configuration for pin r/pio1_2/ad3/ct32b1_mat1 0xd0 ta b l e 8 8 iocon_pio3_0 r/w 0x084 i/o configuration for pin pio3_0/dtr 0xd0 ta b l e 8 9 iocon_pio3_1 r/w 0x088 i/o configuration for pin pio3_1/dsr 0xd0 ta b l e 9 0 iocon_pio2_3 r/w 0x08c i/o configuration for pin pio2_3/ri /mosi1 0xd0 ta b l e 9 1 iocon_swdio_pio1_3 r/w 0x090 i/o configuration for pin swdio/pio1_3/ad4/ct32b1_mat2 0xd0 ta b l e 9 2 iocon_pio1_4 r/w 0x094 i/o configuration for pin pio1_4/ad5/ct32b1_mat3 0xd0 ta b l e 9 3 iocon_pio1_11 r/w 0x098 i/o configuration for pin pio1_11/ad7 0xd0 ta b l e 9 4 iocon_pio3_2 r/w 0x09c i/o configuration for pin pio3_2/dcd 0xd0 ta b l e 9 5 iocon_pio1_5 r/w 0x0a0 i/o configuration for pin pio1_5/rts /ct32b0_cap0 0xd0 ta b l e 9 6 table 56. register overview: i/o configuration (base address 0x4004 4000) name access address offset description reset value reference
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 73 of 543 nxp semiconductors um10398 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration iocon_pio1_6 r/w 0x0a4 i/o configuration for pin pio1_6/rxd/ct32b0_mat0 0xd0 ta b l e 9 7 iocon_pio1_7 r/w 0x0a8 i/o configuration for pin pio1_7/txd/ct32b0_mat1 0xd0 ta b l e 9 8 iocon_pio3_3 r/w 0x0ac i/o configuration for pin pio3_3/ri 0xd0 ta b l e 9 9 iocon_sck_loc r/w 0x0b0 sck pin location select register 0x00 ta b l e 1 0 0 iocon_dsr_loc r/w 0x0b4 dsr pin location select register 0x00 ta b l e 1 0 1 iocon_dcd_loc r/w 0x0b8 dcd pin location select register 0x00 ta b l e 1 0 2 iocon_ri_loc r/w 0x0bc ri pin location register 0x00 ta b l e 1 0 3 table 56. register overview: i/o configuration (base address 0x4004 4000) name access address offset description reset value reference table 57. i/o configuration registers ordered by port number port pin register name lpc1112 LPC1111/ 12/13/14 lpc1113/ 14 lpc11c12 / c14 lpc11c22/ c24 reference hvqfn24 hvqfn33 lqfp48 lqfp48 lqfp48 pio0_0 iocon_reset_pio0_0 yes yes yes yes yes ta b l e 6 0 pio0_1 iocon_pio0_1 yes yes yes yes yes ta b l e 5 8 pio0_2 iocon_pio0_2 yes yes yes yes yes ta b l e 6 3 pio0_3 iocon_pio0_3 no yes yes yes yes ta b l e 6 7 pio0_4 iocon_pio0_4 yes yes yes yes yes ta b l e 6 8 pio0_5 iocon_pio0_5 yes yes yes yes yes ta b l e 6 9 pio0_6 iocon_pio0_6 yes yes yes yes yes ta b l e 7 5 pio0_7 iocon_pio0_7 yes yes yes yes yes ta b l e 7 6 pio0_8 iocon_pio0_8 yes yes yes yes yes ta b l e 8 0 pio0_9 iocon_pio0_9 yes yes yes yes yes ta b l e 8 1 pio0_10 iocon_swclk_pio0_10 yes yes yes yes yes ta b l e 8 2 pio0_11 iocon_r_pio0_11 yes yes yes yes yes ta b l e 8 5 pio1_0 iocon_r_pio1_0 yes yes yes yes yes ta b l e 8 6 pio1_1 iocon_r_pio1_1 yes yes yes yes yes ta b l e 8 7 pio1_2 iocon_r_pio1_2 yes yes yes yes yes ta b l e 8 8 pio1_3 iocon_swdio_pio1_3 yes yes yes yes yes ta b l e 9 2 pio1_4 iocon_pio1_4 yes yes yes yes yes ta b l e 9 3 pio1_5 iocon_pio1_5 no yes yes yes yes ta b l e 9 6 pio1_6 iocon_pio1_6 yes yes yes yes yes ta b l e 9 7 pio1_7 iocon_pio1_7 yes yes yes yes yes ta b l e 9 8 pio1_8 iocon_pio1_8 yes yes yes yes yes ta b l e 6 2 pio1_9 iocon_pio1_9 no yes yes yes no ta b l e 7 0 pio1_10 iocon_pio1_10 no yes yes yes yes ta b l e 8 3 pio1_11 iocon_pio1_11 no yes yes yes yes ta b l e 9 4 pio2_0 iocon_pio2_0 no yes yes yes yes ta b l e 5 9 pio2_1 iocon_pio2_1 no no yes yes yes ta b l e 6 6
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 74 of 543 nxp semiconductors um10398 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration 7.4.1 iocon_pio2_6 pio2_2 iocon_pio2_2 no no yes yes yes ta b l e 7 9 pio2_3 iocon_pio2_3 no no yes yes yes ta b l e 9 1 pio2_4 iocon_pio2_4 no no yes yes no ta b l e 7 2 pio2_5 iocon_pio2_5 no no yes yes no ta b l e 7 3 pio2_6 iocon_pio2_6 no no yes yes yes ta b l e 5 8 pio2_7 iocon_pio2_7 no no yes yes yes ta b l e 6 4 pio2_8 iocon_pio2_8 no no yes yes yes ta b l e 6 5 pio2_9 iocon_pio2_9 no no yes yes no ta b l e 7 7 pio2_10 iocon_pio2_10 no no yes yes yes ta b l e 7 8 pio2_11 iocon_pio2_11 no no yes yes yes ta b l e 8 4 pio3_0 iocon_pio3_0 no no yes yes yes ta b l e 8 9 pio3_1 iocon_pio3_1 no no yes yes yes ta b l e 9 0 pio3_2 iocon_pio3_2 no yes yes yes yes ta b l e 9 5 pio3_3 iocon_pio3_3 no no yes yes yes ta b l e 9 9 pio3_4 iocon_pio3_4 no yes yes no no ta b l e 7 1 pio3_5 iocon_pio3_5 no yes yes no no ta b l e 7 4 - iocon_sck_loc no yes (sckloc = 01 reserved) yes yes yes table 100 - iocon_dsr_loc no no yes yes yes table 101 - iocon_dcd_loc no no yes yes yes table 102 - iocon_ri_loc no no yes yes yes table 103 table 57. i/o configuration registers ordered by port number port pin register name lpc1112 LPC1111/ 12/13/14 lpc1113/ 14 lpc11c12 / c14 lpc11c22/ c24 reference hvqfn24 hvqfn33 lqfp48 lqfp48 lqfp48 table 58. iocon_pio2_6 register (iocon_pio2_ 6, address 0x4004 4000) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio2_6. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 75 of 543 nxp semiconductors um10398 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration 7.4.2 iocon_pio2_0 7.4.3 iocon_pio_reset_pio0_0 10 od selects pseudo open-drain mode. see section 7.1 for part specific details. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 58. iocon_pio2_6 register (iocon_pio2_ 6, address 0x4004 4000) bit description bit symbol value description reset value table 59. iocon_pio2_0 register (iocon_pio2_ 0, address 0x4004 4008) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio2_0. 0x1 select function dtr . 0x2 select function ssel1. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. see section 7.1 for part specific details. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 60. iocon_reset_pio0_0 register (iocon_reset_pio0_0, address 0x4004 400c) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function reset . 0x1 selects function pio0_0.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 76 of 543 nxp semiconductors um10398 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration 7.4.4 iocon_pio0_1 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. see section 7.1 for part specific details. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 60. iocon_reset_pio0_0 register (iocon_reset_pio0_0, address 0x4004 400c) bit description bit symbol value description reset value table 61. iocon_pio0_1 register (iocon_pio0_ 1, address 0x4004 4010) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio0_1. 0x1 selects function clkout. 0x2 selects function ct32b0_mat2. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. see section 7.1 for part specific details. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 77 of 543 nxp semiconductors um10398 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration 7.4.5 iocon_pio1_8 7.4.6 iocon_pio0_2 table 62. iocon_pio1_8 register (iocon_pio1_ 8, address 0x4004 4014) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio1_8. 0x1 selects function ct16b1_cap0. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. see section 7.1 for part specific details. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 63. iocon_pio0_2 register (iocon_pio 0_2, address 0x4004 401c) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio0_2. 0x1 selects function ssel0. 0x2 selects function ct16b0_cap0. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 78 of 543 nxp semiconductors um10398 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration 7.4.7 iocon_pio2_7 7.4.8 iocon_pio2_8 10 od selects pseudo open-drain mode. see section 7.1 for part specific details. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 63. iocon_pio0_2 register (iocon_pio 0_2, address 0x4004 401c) bit description bit symbol value description reset value table 64. iocon_pio2_7 register (iocon_pio2_ 7, address 0x4004 4020) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio2_7. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. see section 7.1 for part specific details. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 65. iocon_pio2_8 register (iocon_pio2_ 8, address 0x4004 4024) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio2_8. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 79 of 543 nxp semiconductors um10398 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration 7.4.9 iocon_pio2_1 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. see section 7.1 for part specific details. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 65. iocon_pio2_8 register (iocon_pio2_ 8, address 0x4004 4024) bit description bit symbol value description reset value table 66. iocon_pio2_1 register (iocon_pio2_ 1, address 0x4004 4028) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio2_1. 0x1 select function dsr . 0x2 select function sck1. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. see section 7.1 for part specific details. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 80 of 543 nxp semiconductors um10398 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration 7.4.10 iocon_pio0_3 7.4.11 iocon_pio0_4 table 67. iocon_pio0_3 register (iocon_pio 0_3, address 0x4004 402c) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio0_3. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 68. iocon_pio0_4 register (iocon_pio0_ 4, address 0x4004 4030) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pi o0_4 (open-drain pin). 0x1 selects i2c function scl (open-drain pin). 7:3 - reserved. 00000 9:8 i2cmode selects i2c mode. select standard mode (i2cmode = 00, default) or standard i/o functi onality (i2cmode = 01) if the pin function is gpio (func = 000). 00 0x0 standard mode/ fast-mode i2c. 0x1 standard i/o functionality 0x2 fast-mode plus i2c 0x3 reserved. 31:10 - - reserved. -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 81 of 543 nxp semiconductors um10398 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration 7.4.12 iocon_pio0_5 7.4.13 iocon_pio1_9 remark: see section 7.1 for part specific details. 7.4.14 iocon_pio3_4 remark: see section 7.1 for part specific details. table 69. iocon_pio0_5 register (iocon_pio0_ 5, address 0x4004 4034) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio0_5 (open-drain pin). 0x1 selects i2c function sda (open-drain pin). 7:3 - reserved. 00000 9:8 i2cmode selects i2c mode. select standard mode (i2cmode = 00, default) or standard i/o functi onality (i2cmode = 01) if the pin function is gpio (func = 000). 00 0x0 standard mode/ fast-mode i2c. 0x1 standard i/o functionality 0x2 fast-mode plus i2c 0x3 reserved. 31:10 - - reserved. - table 70. iocon_pio1_9 register (iocon_pio1_ 9, address 0x4004 4038) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio1_9. 0x1 selects function ct16b1_mat0. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. see section 7.1 for part specific details. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 82 of 543 nxp semiconductors um10398 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration 7.4.15 iocon_pio2_4 remark: see section 7.1 for part specific details. table 71. iocon_pio3_4 register (iocon_pio3_ 4, address 0x4004 403c) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio3_4. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. see section 7.1 for part specific details. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 72. iocon_pio2_4 register (iocon_pio2_ 4, address 0x4004 4040) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio2_4. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. see section 7.1 for part specific details. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 83 of 543 nxp semiconductors um10398 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration 7.4.16 iocon_pio2_5 remark: see section 7.1 for part specific details. 7.4.17 iocon_pio3_5 remark: see section 7.1 for part specific details. table 73. iocon_pio2_5 register (iocon_pio2_ 5, address 0x4004 4044) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio2_5. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 74. iocon_pio3_5 register (iocon_pio3_ 5, address 0x4004 4048) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio3_5. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 84 of 543 nxp semiconductors um10398 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration 7.4.18 iocon_pio0_6 7.4.19 iocon_pio0_7 10 od selects pseudo open-drain mode. see section 7.1 for part specific details. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 74. iocon_pio3_5 register (iocon_pio3_ 5, address 0x4004 4048) bit description bit symbol value description reset value table 75. iocon_pio0_6 register (iocon_pio0_ 6, address 0x4004 404c) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio0_6. 0x1 reserved. 0x2 selects function sck0 (only if pin pio0_6/sck0 selected in ta b l e 1 0 0 ). 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. see section 7.1 for part specific details. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 76. iocon_pio0_7 register (iocon_pio0_ 7, address 0x4004 4050) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio0_7. 0x1 select function cts .
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 85 of 543 nxp semiconductors um10398 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration 7.4.20 iocon_pio2_9 remark: see section 7.1 for part specific details. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. see section 7.1 for part specific details. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 76. iocon_pio0_7 register (iocon_pio0_ 7, address 0x4004 4050) bit description bit symbol value description reset value table 77. iocon_pio2_9 register (iocon_pio2_ 9, address 0x4004 4054) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio2_9. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. see section 7.1 for part specific details. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 86 of 543 nxp semiconductors um10398 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration 7.4.21 iocon_pio2_10 7.4.22 iocon_pio2_2 table 78. iocon_pio2_10 register (iocon_pio2_10, address 0x4004 4058) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio2_10. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. see section 7.1 for part specific details. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 79. iocon_pio2_2 register (iocon_pio2_ 2, address 0x4004 405c) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio2_2. 0x1 select function dcd . 0x2 select function miso1. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 87 of 543 nxp semiconductors um10398 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration 7.4.23 iocon_pio0_8 7.4.24 iocon_pio0_9 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 79. iocon_pio2_2 register (iocon_pio2_ 2, address 0x4004 405c) bit description bit symbol value description reset value table 80. iocon_pio0_8 register (iocon_pio0_ 8, address 0x4004 4060) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio0_8. 0x1 selects function miso0. 0x2 selects function ct16b0_mat0. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. see section 7.1 for part specific details. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 81. iocon_pio0_9 register (iocon_pio0_ 9, address 0x4004 4064) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio0_9. 0x1 selects function mosi0. 0x2 selects function ct16b0_mat1.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 88 of 543 nxp semiconductors um10398 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration 7.4.25 iocon_swclk_pio0_10 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. see section 7.1 for part specific details. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 81. iocon_pio0_9 register (iocon_pio0_ 9, address 0x4004 4064) bit description bit symbol value description reset value table 82. iocon_swclk_pio0_10 register (iocon_swclk_pio0_10, address 0x4004 4068) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function swclk. 0x1 selects function pio0_10. 0x2 selects function sck0 (only if pin swclk/pio0_10/sck0/ct16b0_mat2 selected in table 100 ). 0x3 selects function ct16b0_mat2. 4:3 mode selects function mode (on-chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 89 of 543 nxp semiconductors um10398 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration 7.4.26 iocon_pio1_10 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 82. iocon_swclk_pio0_10 register (iocon_swclk_pio0_10, address 0x4004 4068) bit description ?continued bit symbol value description reset value table 83. iocon_pio1_10 register (iocon_pio1_10, address 0x4004 406c) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio1_10. 0x1 selects function ad6. 0x2 selects function ct16b1_mat1. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 6 - - reserved 1 7 admode selects analog/digital mode 1 0 analog input mode 1 digital functional mode 9:8 - - reserved 00 10 od selects pseudo open-drain mode. see section 7.1 for part specific details. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 90 of 543 nxp semiconductors um10398 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration 7.4.27 iocon_pio2_11 7.4.28 iocon_r_pio0_11 table 84. iocon_pio2_11 register (iocon_pio 2_11, address 0x4004 4070) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio2_11. 0x1 select function sck0 (only if pin pio2_11/sck0 selected in ta b l e 1 0 0 ). 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. see section 7.1 for part specific details. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 85. iocon_r_pio0_11 re gister (iocon_r_pio0_11, address 0x4004 4074) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function r. this func tion is reserved. select one of the alternate functions below. 0x1 selects function pio0_11. 0x2 selects function ad0. 0x3 selects function ct32b0_mat3. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 91 of 543 nxp semiconductors um10398 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration 7.4.29 iocon_r_pio1_0 6 - - reserved 1 7 admode selects analog/digital mode 1 0 analog input mode 1 digital functional mode 9:8 - - reserved 00 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 85. iocon_r_pio0_11 re gister (iocon_r_pio0_11, address 0x4004 4074) bit description ?continued bit symbol value description reset value table 86. iocon_r_pio1_0 re gister (iocon_r_pio1_0, address 0x4004 4078) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function r. this func tion is reserved. select one of the alternate functions below. 0x1 selects function pio1_0. 0x2 selects function ad1. 0x3 selects function ct32b1_cap0. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 6 - - reserved 1 7 admode selects analog/digital mode 1 0 analog input mode 1 digital functional mode 9:8 - - reserved 00 10 od selects pseudo open-drain mode. see section 7.1 for part specific details. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 92 of 543 nxp semiconductors um10398 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration 7.4.30 iocon_r_pio1_1 7.4.31 iocon_r_pio1_2 table 87. iocon_r_pio1_1 re gister (iocon_r_pio1_1, address 0x4004 407c) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function r. this func tion is reserved. select one of the alternate functions below. 0x1 selects function pio1_1. 0x2 selects function ad2. 0x3 selects function ct32b1_mat0. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 6 - - reserved 1 7 admode selects analog/digital mode 1 0 analog input mode 1 digital functional mode 9:8 - - reserved 00 10 od selects pseudo open-drain mode. see section 7.1 for part specific details. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 88. iocon_r_pio1_2 re gister (iocon_r_pio1_2, address 0x4004 4080) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function r. this func tion is reserved. select one of the alternate functions below. 0x1 selects function pio1_2. 0x2 selects function ad3. 0x3 selects function ct32b1_mat1.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 93 of 543 nxp semiconductors um10398 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration 7.4.32 iocon_pio3_0 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 6 - - reserved 1 7 admode selects analog/digital mode 1 0 analog input mode 1 digital functional mode 9:8 - - reserved 00 10 od selects pseudo open-drain mode. see section 7.1 for part specific details. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 88. iocon_r_pio1_2 re gister (iocon_r_pio1_2, address 0x4004 4080) bit description ?continued bit symbol value description reset value table 89. iocon_pio3_0 register (iocon_pio3_ 0, address 0x4004 4084) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio3_0. 0x1 selects function dtr . 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 94 of 543 nxp semiconductors um10398 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration 7.4.33 iocon_pio3_1 7.4.34 iocon_pio2_3 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 89. iocon_pio3_0 register (iocon_pio3_ 0, address 0x4004 4084) bit description bit symbol value description reset value table 90. iocon_pio3_1 register (iocon_pio3_ 1, address 0x4004 4088) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio3_1. 0x1 selects function dsr . 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. see section 7.1 for part specific details. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 91. iocon_pio2_3 register (iocon_pio2_ 3, address 0x4004 408c) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio2_3. 0x1 selects function ri . 0x2 selects function mosi1.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 95 of 543 nxp semiconductors um10398 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration 7.4.35 iocon_swdio_pio1_3 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. see section 7.1 for part specific details. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 91. iocon_pio2_3 register (iocon_pio2_ 3, address 0x4004 408c) bit description bit symbol value description reset value table 92. iocon_swdio_pio1_3 register (ioc on_swdio_pio1_3, address 0x4004 4090) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function swdio. 0x1 selects function pio1_3. 0x2 selects function ad4. 0x3 selects function ct32b1_mat2. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 6 - - reserved 1 7 admode selects analog/digital mode 1 0 analog input mode 1 digital functional mode 9:8 - - reserved 00
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 96 of 543 nxp semiconductors um10398 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration 7.4.36 iocon_pio1_4 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 92. iocon_swdio_pio1_3 register (ioc on_swdio_pio1_3, address 0x4004 4090) bit description ?continued bit symbol value description reset value table 93. iocon_pio1_4 register (iocon_pio1_ 4, address 0x4004 4094) bit description bit symbol value description reset value 2:0 func selects pin func tion. this pin functions as wakeup pin if the lpc111x/lpc11cxx is in deep power-down mode regardless of the value of func. all other values are reserved. 000 0x0 selects function pio1_4. 0x1 selects function ad5. 0x2 selects function ct32b1_mat3. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 6 - - reserved 1 7 admode selects analog/digital mode 1 0 analog input mode 1 digital functional mode 9:8 - - reserved 00 10 od selects pseudo open-drain mode. see section 7.1 for part specific details. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 97 of 543 nxp semiconductors um10398 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration 7.4.37 iocon_pio1_11 7.4.38 iocon_pio3_2 table 94. iocon_pio1_11 register (iocon_pio 1_11, address 0x4004 4098) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio1_11. 0x1 selects function ad7. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 6 - - reserved 1 7 admode selects analog/digital mode 1 0 analog input mode 1 digital functional mode 9:8 - - reserved 00 10 od selects pseudo open-drain mode. see section 7.1 for part specific details. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 95. iocon_pio3_2 register (iocon_pio3_ 2, address 0x4004 409c) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio3_2. 0x1 selects function dcd . 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 98 of 543 nxp semiconductors um10398 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration 7.4.39 iocon_pio1_5 7.4.40 iocon_pio1_6 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 95. iocon_pio3_2 register (iocon_pio 3_2, address 0x4004 409c) bit description bit symbol value description reset value table 96. iocon_pio1_5 register (iocon_pio 1_5, address 0x4004 40a0) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio1_5. 0x1 selects function rts . 0x2 selects function ct32b0_cap0. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. see section 7.1 for part specific details. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 97. iocon_pio1_6 register (iocon_pio 1_6, address 0x4004 40a4) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio1_6. 0x1 selects function rxd. 0x2 selects function ct32b0_mat0.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 99 of 543 nxp semiconductors um10398 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration 7.4.41 iocon_pio1_7 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. see section 7.1 for part specific details. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 97. iocon_pio1_6 register (iocon_pio 1_6, address 0x4004 40a4) bit description bit symbol value description reset value table 98. iocon_pio1_7 register (iocon_pio 1_7, address 0x4004 40a8) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio1_7. 0x1 selects function txd. 0x2 selects function ct32b0_mat1. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. see section 7.1 for part specific details. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 100 of 543 nxp semiconductors um10398 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration 7.4.42 iocon_pio3_3 7.4.43 iocon_sck_loc table 99. iocon_pio3_3 register (iocon_pio 3_3, address 0x4004 40ac) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio3_3. 0x1 selects function ri . 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. see section 7.1 for part specific details. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 100. iocon sck location register ( iocon_sck_loc, address 0x4004 40b0) bit description bit symbol value description reset value 1:0 sckloc selects pin location for sck0 function. 00 0x0 selects sck0 function in pin location swclk/pio0_10/sck0/ct16b0_mat2 (see ta b l e 8 2 ). 0x1 selects sck0 function in pin location pio2_11/sck0 (see ta b l e 8 4 . 0x2 selects sck0 function in pin location pio0_6/sck0 (see ta b l e 7 5 ). 0x3 reserved. 31:2 - - reserved. -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 101 of 543 nxp semiconductors um10398 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration 7.4.44 iocon_dsr_loc 7.4.45 iocon_dcd_loc 7.4.46 iocon_ri_loc table 101. iocon dsr location register (iocon_dsr_loc, address 0x4004 40b4) bit description bit symbol value description reset value 1:0 dsrloc selects pin location for dsr function. 00 0x0 selects dsr function in pin location pio2_1/dsr/ sck1. 0x1 selects dsr function in pin location pio3_1/dsr . 0x2 reserved. 0x3 reserved. 31:2 - - reserved. - table 102. iocon dcd location register (iocon_dcd_loc, address 0x4004 40b8) bit description bit symbol value description reset value 1:0 dcdloc selects pin location for dcd function. 00 0x0 selects dcd function in pin location pio2_2/dcd /miso1. 0x1 selects dcd function in pin location pio3_2/dcd . 0x2 reserved. 0x3 reserved. 31:2 - - reserved. - table 103. iocon ri location register (iocon_ri_loc, address 0x4004 40bc) bit description bit symbol value description reset value 1:0 riloc selects pin locati on for ri function. 00 0x0 selects ri function in pin location pio2_3/ri /mosi1. 0x1 selects ri function in pin location pio3_3/ri . 0x2 reserved. 0x3 reserved. 31:2 - - reserved. -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 102 of 543 8.1 how to read this chapter remark: this chapter applies to parts in the following series (see ta b l e 1 ): ? lpc1100xl the implementation of the i/o configuration registers varies for different lpc1100xl parts and packages. table 105 shows which iocon registers are used on the different packages. 8.2 features the i/o configuration registers control the el ectrical characterist ics of the pads. the following features are programmable: ? pin function. ? internal pull-up/pull-down resistor or bus keeper function. ? hysteresis. ? analog input or digital mode for pads hosting the adc inputs. ? i 2 c mode for pads hosting the i 2 c-bus function. ? pseudo open-drain mode for non-i2c pins. 8.3 general description the iocon registers control the function (gpi o or peripheral function), the input mode, and the hysteresis of all pion_m pins. in addition, the i 2 c-bus pins can be configured for different i 2 c-bus modes. an analog input mode can be selected for the input pins to the adc. um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) rev. 12.1 ? 7 august 2013 user manual
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 103 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) 8.3.1 pin function the func bits in the iocon registers can be set to gpio (func = 000) or to a peripheral function. if the pins are gpio pins, the gpiondir registers determine whether the pin is configured as an input or output (see section 12.3.2 ). for any peripheral function, the pin direction is controlled automa tically depending on the pins functionality. the gpiondir registers have no effect for peripheral functions. 8.3.2 pin mode the mode bits in the iocon re gister allow the selection of on-chip pull-up or pull-down resistors for each pin or select the repeater mode. the possible on-chip resistor configurations are pull-up enabled, pull-down enabled, or no pull-up/pull-down. the default va lue is pull-up enabled. if the pull-up resistor is enabled (default), all non-i2c pins are pulled up to 3.3 v (v dd = 3.3 v). the repeater mode enables the pull-up resistor if the pin is at a logic high and enables the pull-down resistor if the pin is at a logic low. this causes the pin to retain its last known state if it is configured as an input and is not driven externally. the state retention is fig 15. standard i/o pin configuration pin v dd v dd esd v ss esd strong pull-up strong pull-down v dd weak pull-up weak pull-down open-drain enable output enable repeater mode enable pull-up enable pull-down enable data output data input analog input select analog input 002aah159 pin configured as digital output driver pin configured as digital input pin configured as analog input
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 104 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) not applicable to the deep power-down mode. repeater mode may typically be used to prevent a pin from floating (and potentially us ing significant power if it floats to an indeterminate state) if it is temporarily not driven. 8.3.3 hysteresis the input buffer for digital functions can be configured with hysteresis or as plain buffer through the iocon registers (see the lpc1100xl data sheet for details). if the external pad supply voltage v dd is between 2.5 v and 3.6 v, the hysteresis buffer can be enabled or disabled. if v dd is below 2.5 v, the hysteresis buffer must be disabled to use the pin in input mode. 8.3.4 a/d-mode in a/d-mode, the digital receiver is disconne cted to obtain an accu rate input voltage for analog-to-digital conversions. this mode can be selected in those iocon registers that control pins with an analog function. if a/d mode is selected, hysteresis and pin mode settings have no effect. for pins without analog functions, th e a/d-mode setting has no effect. 8.3.5 i 2 c mode if the i 2 c function is selected by the func bits of registers iocon_pio0_4 ( ta b l e 11 6 ) and iocon_pio0_5 ( table 117 ), then the i 2 c-bus pins can be configured for different i 2 c-modes: ? standard mode/fast-mode i 2 c with input glitch filter (this includes an open-drain output according to the i 2 c-bus specification). ? fast-mode plus with input glitch filter (this includes an open-drain output according to the i 2 c-bus specification). in this mode, th e pins function as high-current sinks. ? standard open-drain i/o functionality without input filter. remark: either standard mode/fast-mode i 2 c or standard i/o functionality should be selected if the pin is used as gpio pin. 8.3.6 open-drain mode when output is selected, either by selecting a special function in the func field, or by selecting gpio function for a pin having a 1 in its gpiodir register, a 1 in the od bit selects open-drain operation, that is, a 1 disables the high-drive transistor. this option has no effect on the primary i 2 c pins. 8.4 register description the i/o configuration registers control the pi o port pins, the inputs and outputs of all peripherals and functional blocks, the i 2 c-bus pins, and the adc input pins. each port pin pion_m has one iocon register assigned to control the pins function and electrical characteristics.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 105 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) some input functions (sck0, dsr , dcd , ri , ssel1, ct16b0_cap0, sck1, miso1, mosi1, ct32b0_cap0, and rxd) are multip lexed to several ph ysical pins. the iocon_loc registers select the pin location for each of these functions. remark: the iocon registers are listed in order of their memory locations in table 104 , which correspond to the order of their physical pin numbers in the lqfp48 package starting at the upper left corner with pin 1 (pio2_6). see table 105 for a listing of iocon registers ordered by port number. the iocon location registers are used to select a physical pin for multiplexed functions. remark: note that once the pin location has be en selected, the function still must be configured in the corresponding iocon registers for the function to be usable on that pin. table 104. register overview: i/o configuration (base address 0x4004 4000) name access address offset description reset value reference iocon_pio2_6 r/w 0x000 i/o configuration for pin pio2_6/ ct32b0_mat1 0xd0 ta b l e 1 0 6 - r/w 0x004 reserved - - iocon_pio2_0 r/w 0x008 i/o configuration for pin pio2_0/dtr /ssel1 0xd0 ta b l e 1 0 7 iocon_reset_pio0_0 r/w 0x00c i/o configuration for pin reset /pio0_0 0xd0 ta b l e 1 0 8 iocon_pio0_1 r/w 0x010 i/o configuration for pin pio0_1/clkout/ct32b0_mat2 0xd0 ta b l e 1 0 6 iocon_pio1_8 r/w 0x014 i/o configuration for pin pio1_8/ct16b1_cap0 0xd0 ta b l e 11 0 iocon_ssel1_loc r/w 0x018 ssel1 pin location select register 0x0 ta b l e 1 5 2 iocon_pio0_2 r/w 0x01c i/o configuration for pin pio0_2/ssel0/ct16b0_cap0 0xd0 table 111 iocon_pio2_7 r/w 0x020 i/o configuration for pin pio2_7/ ct32b0_mat2/rxd 0xd0 ta b l e 11 2 iocon_pio2_8 r/w 0x024 i/o configuration for pin pio2_8/ ct32b0_mat3/txd 0xd0 ta b l e 11 3 iocon_pio2_1 r/w 0x028 i/o configuration for pin pio2_1/dsr/ sck1 0xd0 ta b l e 11 4 iocon_pio0_3 r/w 0x02c i/o configuration for pin pio0_3 0xd0 ta b l e 11 5 iocon_pio0_4 r/w 0x030 i/o configuration for pin pio0_4/scl 0x00 ta b l e 11 6 iocon_pio0_5 r/w 0x034 i/o configuration for pin pio0_5/sda 0x00 ta b l e 11 7 iocon_pio1_9 r/w 0x038 i/o configuration for pin pio1_9/ct16b1_mat0/ mosi1 0xd0 ta b l e 11 8 iocon_pio3_4 r/w 0x03c i/o configuration for pin pio3_4/ ct16b0_cap1/rxd 0xd0 ta b l e 11 9 iocon_pio2_4 r/w 0x040 i/o configuration for pin pio2_4/ ct16b1_mat1/ ssel1 0xd0 ta b l e 1 2 0 iocon_pio2_5 r/w 0x044 i/o configuration for pin pio2_5/ ct32b0_mat0 0xd0 ta b l e 1 2 1 iocon_pio3_5 r/w 0x048 i/o configuration for pin pio3_5/ ct16b1_cap1/txd 0xd0 ta b l e 1 2 2 iocon_pio0_6 r/w 0x04c i/o configuration for pin pio0_6/sck0 0xd0 ta b l e 1 2 3
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 106 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) iocon_pio0_7 r/w 0x050 i/o configuration for pin pio0_7/cts 0xd0 ta b l e 1 2 4 iocon_pio2_9 r/w 0x054 i/o configuration for pin pio2_9/ ct32b0_cap0 0xd0 ta b l e 1 2 5 iocon_pio2_10 r/w 0x058 i/o configuration for pin pio2_10 0xd0 ta b l e 1 2 6 iocon_pio2_2 r/w 0x05c i/o configuration for pin pio2_2/dcd /miso1 0xd0 ta b l e 1 2 7 iocon_pio0_8 r/w 0x060 i/o configuration for pin pio0_8/miso0/ct16b0_mat0 0xd0 ta b l e 1 2 8 iocon_pio0_9 r/w 0x064 i/o configuration for pin pio0_9/mosi0/ct16b0_mat1 0xd0 ta b l e 1 2 9 iocon_swclk_pio0_10 r/w 0x068 i/o configuration for pin swclk/pio0_10/ sck0/ct16b0_mat2 0xd0 ta b l e 1 3 0 iocon_pio1_10 r/w 0x06c i/o configuration for pin pio1_10/ad6/ct16b1_mat1/ miso1 0xd0 ta b l e 1 3 1 iocon_pio2_11 r/w 0x070 i/o configur ation for pin pio2_11/sck0/ ct32b0_cap1 0xd0 ta b l e 1 3 2 iocon_r_pio0_11 r/w 0x074 i/o configuration for pin r/pio0_11/ad0/ct32b0_mat3 0xd0 ta b l e 1 3 3 iocon_r_pio1_0 r/w 0x078 i/o configuration for pin r/pio1_0/ad1/ct32b1_cap0 0xd0 ta b l e 1 3 4 iocon_r_pio1_1 r/w 0x07c i/o configuration for pin r/pio1_1/ad2/ct32b1_mat0 0xd0 ta b l e 1 3 5 iocon_r_pio1_2 r/w 0x080 i/o configuration for pin r/pio1_2/ad3/ct32b1_mat1 0xd0 ta b l e 1 3 6 iocon_pio3_0 r/w 0x084 i/o configuration for pin pio3_0/dtr /ct16b0_mat0/txd 0xd0 ta b l e 1 3 7 iocon_pio3_1 r/w 0x088 i/o configuration for pin pio3_1/dsr /ct16b0_mat1/rxd 0xd0 ta b l e 1 3 8 iocon_pio2_3 r/w 0x08c i/o configuration for pin pio2_3/ri /mosi1 0xd0 ta b l e 1 3 9 iocon_swdio_pio1_3 r/w 0x090 i/o configuration for pin swdio/pio1_3/ad4/ct32b1_mat2 0xd0 ta b l e 1 4 0 iocon_pio1_4 r/w 0x094 i/o configuration for pin pio1_4/ad5/ct32b1_mat3 0xd0 ta b l e 1 4 1 iocon_pio1_11 r/w 0x098 i/o configuration for pin pio1_11/ad7/ct32b1_cap1 0xd0 ta b l e 1 4 2 iocon_pio3_2 r/w 0x09c i/o configuration for pin pio3_2/dcd / ct16b0_mat2/sck1 0xd0 ta b l e 1 4 3 iocon_pio1_5 r/w 0x0a0 i/o configuration for pin pio1_5/rts /ct32b0_cap0 0xd0 ta b l e 1 4 4 iocon_pio1_6 r/w 0x0a4 i/o configuration for pin pio1_6/rxd/ct32b0_mat0 0xd0 ta b l e 1 4 5 iocon_pio1_7 r/w 0x0a8 i/o configuration for pin pio1_7/txd/ct32b0_mat1 0xd0 ta b l e 1 4 6 table 104. register overview: i/o configuration (base address 0x4004 4000) name access address offset description reset value reference
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 107 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) iocon_pio3_3 r/w 0x0ac i/o configuration for pin pio3_3/ri / ct16b0_cap0 0xd0 ta b l e 1 4 7 iocon_sck0_loc r/w 0x0b0 sck0 pin location select register 0x00 ta b l e 1 4 8 iocon_dsr_loc r/w 0x0b4 dsr pin location select register 0x00 ta b l e 1 4 9 iocon_dcd_loc r/w 0x0b8 dcd pin location select register 0x00 ta b l e 1 5 0 iocon_ri_loc r/w 0x0bc ri pin location select register 0x00 ta b l e 1 5 1 iocon_ct16b0_cap0_loc r/w 0x0c0 ct16b0_cap0 pin location select register 0x00 ta b l e 1 5 3 iocon_sck1_loc r/w 0x0c4 sck1 pin location select register 0x00 ta b l e 1 5 4 iocon_miso1_loc r/w 0x0c8 miso1 pi n location select register 0x00 ta b l e 1 5 5 iocon_mosi1_loc r/w 0x0cc mosi1 pi n location select register 0x00 ta b l e 1 5 6 iocon_ct32b0_cap0_loc r/w 0x0d0 ct32b0_cap0 pin location select register 0x00 ta b l e 1 5 7 iocon_rxd_loc r/w 0x0d4 rxd pin location select register 0x00 ta b l e 1 5 8 table 104. register overview: i/o configuration (base address 0x4004 4000) name access address offset description reset value reference table 105. i/o configuration regi sters ordered by port number port pin register name LPC1111/ 12/13/14 lpc1113/14/15 reference hvqfn33 lqfp48 pio0_0 iocon_rese t_pio0_0 yes yes table 108 pio0_1 iocon_pio0_1 yes yes table 106 pio0_2 iocon_pio0_2 yes yes ta b l e 111 pio0_3 iocon_pio0_3 yes yes ta b l e 11 5 pio0_4 iocon_pio0_4 yes yes ta b l e 11 6 pio0_5 iocon_pio0_5 yes yes ta b l e 11 7 pio0_6 iocon_pio0_6 yes yes table 123 pio0_7 iocon_pio0_7 yes yes table 124 pio0_8 iocon_pio0_8 yes yes table 128 pio0_9 iocon_pio0_9 yes yes table 129 pio0_10 iocon_swclk_pio0_10 yes yes table 130 pio0_11 iocon_r_pio0_11 yes yes table 133 pio1_0 iocon_r_pio1_0 yes yes table 134 pio1_1 iocon_r_pio1_1 yes yes table 135 pio1_2 iocon_r_pio1_2 yes yes table 136 pio1_3 iocon_swdio_pio1_3 yes yes table 140 pio1_4 iocon_pio1_4 yes yes table 141 pio1_5 iocon_pio1_5 yes yes table 144 pio1_6 iocon_pio1_6 yes yes table 145 pio1_7 iocon_pio1_7 yes yes table 146 pio1_8 iocon_pio1_8 yes yes ta b l e 11 0 pio1_9 iocon_pio1_9 yes yes ta b l e 11 8
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 108 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) 8.4.1 iocon_pio2_6 pio1_10 iocon_pio1_10 yes yes table 131 pio1_11 iocon_pio1_11 yes yes table 142 pio2_0 iocon_pio2_0 yes yes table 107 pio2_1 iocon_pio2_1 no yes ta b l e 11 4 pio2_2 iocon_pio2_2 no yes table 127 pio2_3 iocon_pio2_3 no yes table 139 pio2_4 iocon_pio2_4 no yes table 120 pio2_5 iocon_pio2_5 no yes table 121 pio2_6 iocon_pio2_6 no yes table 106 pio2_7 iocon_pio2_7 no yes ta b l e 11 2 pio2_8 iocon_pio2_8 no yes ta b l e 11 3 pio2_9 iocon_pio2_9 no yes table 125 pio2_10 iocon_pio2_10 no yes table 126 pio2_11 iocon_pio2_11 no yes table 132 pio3_0 iocon_pio3_0 no yes table 137 pio3_1 iocon_pio3_1 no yes table 138 pio3_2 iocon_pio3_2 yes yes table 143 pio3_3 iocon_pio3_3 no yes table 147 pio3_4 iocon_pio3_4 yes yes ta b l e 11 9 pio3_5 iocon_pio3_5 yes yes table 122 table 105. i/o configuration regi sters ordered by port number port pin register name LPC1111/ 12/13/14 lpc1113/14/15 reference hvqfn33 lqfp48 table 106. iocon_pio2_6 register (iocon_pio 2_6, address 0x4004 4000) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio2_6. 0x1 selects function ct32b0_mat1. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 109 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) 8.4.2 iocon_pio2_0 8.4.3 iocon_pio_reset_pio0_0 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 106. iocon_pio2_6 register (iocon_pio 2_6, address 0x4004 4000) bit description bit symbol value description reset value table 107. iocon_pio2_0 register (iocon_pio 2_0, address 0x4004 4008) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio2_0. 0x1 select function dtr . 0x2 select function ssel1. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 108. iocon_reset_pio0_0 register ( iocon_reset_pio0_0, address 0x4004 400c) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function reset . 0x1 selects function pio0_0.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 110 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) 8.4.4 iocon_pio0_1 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 108. iocon_reset_pio0_0 register ( iocon_reset_pio0_0, address 0x4004 400c) bit description bit symbol value description reset value table 109. iocon_pio0_1 register (iocon_pio 0_1, address 0x4004 4010) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio0_1. 0x1 selects function clkout. 0x2 selects function ct32b0_mat2. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 111 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) 8.4.5 iocon_pio1_8 8.4.6 iocon_pio0_2 table 110. iocon_pio1_8 register (iocon_pio 1_8, address 0x4004 4014) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio1_8. 0x1 selects function ct16b1_cap0. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 111. iocon_pio0_2 register (iocon_pio0_2, address 0x4004 401c) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio0_2. 0x1 selects function ssel0. 0x2 selects function ct16b0_cap0. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 112 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) 8.4.7 iocon_pio2_7 8.4.8 iocon_pio2_8 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 111. iocon_pio0_2 register (iocon_pio0_2, address 0x4004 401c) bit description bit symbol value description reset value table 112. iocon_pio2_7 register (iocon_pio 2_7, address 0x4004 4020) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio2_7. 0x1 selects function ct32b0_mat2. 0x2 selects function rxd. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 113. iocon_pio2_8 register (iocon_pio 2_8, address 0x4004 4024) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio2_8. 0x1 selects function ct32b0_mat3. 0x2 selects function txd.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 113 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) 8.4.9 iocon_pio2_1 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 113. iocon_pio2_8 register (iocon_pio 2_8, address 0x4004 4024) bit description bit symbol value description reset value table 114. iocon_pio2_1 register (iocon_pio 2_1, address 0x4004 4028) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio2_1. 0x1 select function dsr . 0x2 select function sck1. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 114 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) 8.4.10 iocon_pio0_3 8.4.11 iocon_pio0_4 table 115. iocon_pio0_3 register (iocon_pio 0_3, address 0x4004 402c) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio0_3. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 116. iocon_pio0_4 register (iocon_pio 0_4, address 0x4004 4030) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pi o0_4 (open-drain pin). 0x1 selects i2c function scl (open-drain pin). 7:3 - reserved. 00000 9:8 i2cmode selects i2c mode. select standard mode (i2cmode = 00, default) or standard i/o functi onality (i2cmode = 01) if the pin function is gpio (func = 000). 00 0x0 standard mode/ fast-mode i2c. 0x1 standard i/o functionality 0x2 fast-mode plus i2c 0x3 reserved. 31:10 - - reserved. -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 115 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) 8.4.12 iocon_pio0_5 8.4.13 iocon_pio1_9 remark: see section 8.1 for part specific details. 8.4.14 iocon_pio3_4 remark: see section 8.1 for part specific details. table 117. iocon_pio0_5 register (iocon_pio 0_5, address 0x4004 4034) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio0_5 (open-drain pin). 0x1 selects i2c function sda (open-drain pin). 7:3 - reserved. 00000 9:8 i2cmode selects i2c mode. select standard mode (i2cmode = 00, default) or standard i/o functi onality (i2cmode = 01) if the pin function is gpio (func = 000). 00 0x0 standard mode/ fast-mode i2c. 0x1 standard i/o functionality 0x2 fast-mode plus i2c 0x3 reserved. 31:10 - - reserved. - table 118. iocon_pio1_9 register (iocon_pio 1_9, address 0x4004 4038) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio1_9. 0x1 selects function ct16b1_mat0. 0x2 selects function mosi1. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 116 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) 8.4.15 iocon_pio2_4 remark: see section 8.1 for part specific details. table 119. iocon_pio3_4 register (iocon_pio 3_4, address 0x4004 403c) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio3_4. 0x1 selects function ct16b0_cap1. 0x2 selects function rxd. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 120. iocon_pio2_4 register (iocon_pio 2_4, address 0x4004 4040) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio2_4. 0x1 selects function ct16b1_mat1. 0x2 selects function ssel1. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 117 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) 8.4.16 iocon_pio2_5 remark: see section 8.1 for part specific details. 8.4.17 iocon_pio3_5 remark: see section 8.1 for part specific details. 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 120. iocon_pio2_4 register (iocon_pio 2_4, address 0x4004 4040) bit description bit symbol value description reset value table 121. iocon_pio2_5 register (iocon_pio 2_5, address 0x4004 4044) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio2_5. 0x1 selects function ct32b0_mat0. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 122. iocon_pio3_5 register (iocon_pio 3_5, address 0x4004 4048) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio3_5. 0x1 selects function ct16b1_cap1. 0x2 selects function txd.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 118 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) 8.4.18 iocon_pio0_6 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 122. iocon_pio3_5 register (iocon_pio 3_5, address 0x4004 4048) bit description bit symbol value description reset value table 123. iocon_pio0_6 register (iocon_pio0_6, address 0x4004 404c) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio0_6. 0x1 reserved. 0x2 selects function sck0 (only if pin pio0_6/sck0 selected in ta b l e 1 4 8 ). 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 119 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) 8.4.19 iocon_pio0_7 8.4.20 iocon_pio2_9 remark: see section 8.1 for part specific details. table 124. iocon_pio0_7 register (iocon_pio 0_7, address 0x4004 4050) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio0_7. 0x1 select function cts . 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 125. iocon_pio2_9 register (iocon_pio 2_9, address 0x4004 4054) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio2_9. 0x1 selects function ct32b0_cap0. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 120 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) 8.4.21 iocon_pio2_10 8.4.22 iocon_pio2_2 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 125. iocon_pio2_9 register (iocon_pio 2_9, address 0x4004 4054) bit description bit symbol value description reset value table 126. iocon_pio2_10 register (iocon_pio 2_10, address 0x4004 4058) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio2_10. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 127. iocon_pio2_2 register (iocon_pio2_2, address 0x4004 405c) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio2_2. 0x1 select function dcd . 0x2 select function miso1. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 121 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) 8.4.23 iocon_pio0_8 8.4.24 iocon_pio0_9 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 127. iocon_pio2_2 register (iocon_pio2_2, address 0x4004 405c) bit description bit symbol value description reset value table 128. iocon_pio0_8 register (iocon_pio 0_8, address 0x4004 4060) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio0_8. 0x1 selects function miso0. 0x2 selects function ct16b0_mat0. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 129. iocon_pio0_9 register (iocon_pio 0_9, address 0x4004 4064) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio0_9. 0x1 selects function mosi0. 0x2 selects function ct16b0_mat1.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 122 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) 8.4.25 iocon_swclk_pio0_10 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 129. iocon_pio0_9 register (iocon_pio 0_9, address 0x4004 4064) bit description bit symbol value description reset value table 130. iocon_swclk_pio0_10 register (iocon_swclk_pio0_10, address 0x4004 4068) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function swclk. 0x1 selects function pio0_10. 0x2 selects function sck0 (only if pin swclk/pio0_10/sck0/ct16b0_mat2 selected in table 148 ). 0x3 selects function ct16b0_mat2. 4:3 mode selects function mode (on-chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 123 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) 8.4.26 iocon_pio1_10 8.4.27 iocon_pio2_11 table 131. iocon_pio1_10 register (iocon_pio 1_10, address 0x4004 406c) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio1_10. 0x1 selects function ad6. 0x2 selects function ct16b1_mat1. 0x3 selects function miso1. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 6 - - reserved 1 7 admode selects analog/digital mode 1 0 analog input mode 1 digital functional mode 9:8 - - reserved 00 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 132. iocon_pio2_11 register (iocon_pio2_11, address 0x4004 4070) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio2_11. 0x1 select function sck0 (only if pin pio2_11/sck0 selected in ta b l e 1 4 8 ). 0x2 select function ct32b0_cap1. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 124 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) 8.4.28 iocon_r_pio0_11 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 132. iocon_pio2_11 register (iocon_pio2_11, address 0x4004 4070) bit description bit symbol value description reset value table 133. iocon_r_pio0_11 register (iocon_r_pio0_11, address 0x4004 4074) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function r. this func tion is reserved. select one of the alternate functions below. 0x1 selects function pio0_11. 0x2 selects function ad0. 0x3 selects function ct32b0_mat3. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 6 - - reserved 1 7 admode selects analog/digital mode 1 0 analog input mode 1 digital functional mode 9:8 - - reserved 00 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 125 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) 8.4.29 iocon_r_pio1_0 8.4.30 iocon_r_pio1_1 table 134. iocon_r_pio1_0 register (ioc on_r_pio1_0, address 0x4004 4078) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function r. this func tion is reserved. select one of the alternate functions below. 0x1 selects function pio1_0. 0x2 selects function ad1. 0x3 selects function ct32b1_cap0. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 6 - - reserved 1 7 admode selects analog/digital mode 1 0 analog input mode 1 digital functional mode 9:8 - - reserved 00 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 135. iocon_r_pio1_1 register (ioc on_r_pio1_1, address 0x4004 407c) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function r. this func tion is reserved. select one of the alternate functions below. 0x1 selects function pio1_1. 0x2 selects function ad2. 0x3 selects function ct32b1_mat0.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 126 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) 8.4.31 iocon_r_pio1_2 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 6 - - reserved 1 7 admode selects analog/digital mode 1 0 analog input mode 1 digital functional mode 9:8 - - reserved 00 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 135. iocon_r_pio1_1 register (ioc on_r_pio1_1, address 0x4004 407c) bit description ?continued bit symbol value description reset value table 136. iocon_r_pio1_2 register (ioc on_r_pio1_2, address 0x4004 4080) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function r. this func tion is reserved. select one of the alternate functions below. 0x1 selects function pio1_2. 0x2 selects function ad3. 0x3 selects function ct32b1_mat1. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 6 - - reserved 1
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 127 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) 8.4.32 iocon_pio3_0 7 admode selects analog/digital mode 1 0 analog input mode 1 digital functional mode 9:8 - - reserved 00 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 136. iocon_r_pio1_2 register (ioc on_r_pio1_2, address 0x4004 4080) bit description ?continued bit symbol value description reset value table 137. iocon_pio3_0 register (iocon_pio 3_0, address 0x4004 4084) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio3_0. 0x1 selects function dtr . 0x2 selects function ct16b0_mat0. 0x3 selects function txd. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 128 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) 8.4.33 iocon_pio3_1 8.4.34 iocon_pio2_3 table 138. iocon_pio3_1 register (iocon_pio 3_1, address 0x4004 4088) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio3_1. 0x1 selects function dsr . 0x2 selects function ct16b0_mat1. 0x3 selects function rxd . 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 139. iocon_pio2_3 register (iocon_pio2_3, address 0x4004 408c) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio2_3. 0x1 selects function ri . 0x2 selects function mosi1. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 129 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) 8.4.35 iocon_swdio_pio1_3 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 139. iocon_pio2_3 register (iocon_pio2_3, address 0x4004 408c) bit description bit symbol value description reset value table 140. iocon_swdio_pio1_3 register (i ocon_swdio_pio1_3, address 0x4004 4090) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function swdio. 0x1 selects function pio1_3. 0x2 selects function ad4. 0x3 selects function ct32b1_mat2. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 6 - - reserved 1 7 admode selects analog/digital mode 1 0 analog input mode 1 digital functional mode 9:8 - - reserved 00 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 130 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) 8.4.36 iocon_pio1_4 8.4.37 iocon_pio1_11 table 141. iocon_pio1_4 register (iocon_pio 1_4, address 0x4004 4094) bit description bit symbol value description reset value 2:0 func selects pin func tion. this pin functions as wakeup pin if the lpc111x/lpc11cxx is in deep power-down mode regardless of the value of func. all other values are reserved. 000 0x0 selects function pio1_4. 0x1 selects function ad5. 0x2 selects function ct32b1_mat3. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 6 - - reserved 1 7 admode selects analog/digital mode 1 0 analog input mode 1 digital functional mode 9:8 - - reserved 00 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 142. iocon_pio1_11 register (iocon_pio1_11, address 0x4004 4098) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio1_11. 0x1 selects function ad7. 0x2 selects function ct32b1_cap1. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 131 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) 8.4.38 iocon_pio3_2 5 hys hysteresis. 0 0 disable. 1 enable. 6 - - reserved 1 7 admode selects analog/digital mode 1 0 analog input mode 1 digital functional mode 9:8 - - reserved 00 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 142. iocon_pio1_11 register (iocon_pio1_11, address 0x4004 4098) bit description bit symbol value description reset value table 143. iocon_pio3_2 register (iocon_pio3_2, address 0x4004 409c) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio3_2. 0x1 selects function dcd . 0x2 selects function ct16b0_mat2. 0x3 selects function sck1. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 132 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) 8.4.39 iocon_pio1_5 8.4.40 iocon_pio1_6 table 144. iocon_pio1_5 register (iocon_pio1_5, address 0x4004 40a0) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio1_5. 0x1 selects function rts . 0x2 selects function ct32b0_cap0. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 145. iocon_pio1_6 register (iocon_pio1_6, address 0x4004 40a4) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio1_6. 0x1 selects function rxd. 0x2 selects function ct32b0_mat0. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 133 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) 8.4.41 iocon_pio1_7 8.4.42 iocon_pio3_3 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 145. iocon_pio1_6 register (iocon_pio1_6, address 0x4004 40a4) bit description bit symbol value description reset value table 146. iocon_pio1_7 register (iocon_pio1_7, address 0x4004 40a8) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio1_7. 0x1 selects function txd. 0x2 selects function ct32b0_mat1. 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 147. iocon_pio3_3 register (iocon_pio3_3, address 0x4004 40ac) bit description bit symbol value description reset value 2:0 func selects pin function. all other values are reserved. 000 0x0 selects function pio3_3. 0x1 selects function ri . 0x2 selects function ct16b0_cap0.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 134 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) 8.4.43 iocon_sck0_loc 4:3 mode selects function mode (on- chip pull-up/pull-down resistor control). 10 0x0 inactive (no pull-down/pull-up resistor enabled). 0x1 pull-down resistor enabled. 0x2 pull-up resistor enabled. 0x3 repeater mode. 5 hys hysteresis. 0 0 disable. 1 enable. 9:6 - - reserved 0011 10 od selects pseudo open-drain mode. 0 0 standard gpio output 1 open-drain output 31:11 - - reserved - table 147. iocon_pio3_3 register (iocon_pio3_3, address 0x4004 40ac) bit description bit symbol value description reset value table 148. iocon sck0 location register (iocon_sck0_loc, address 0x4004 40b0) bit description bit symbol value description reset value 1:0 sckloc selects pin location for sck0 function. 00 0x0 selects sck0 function in pin location swclk/pio0_10/sck0/ct16b0_mat2 (see table 130 ). 0x1 selects sck0 function in pin location pio2_11/sck0 (see ta b l e 1 3 2 ). 0x2 selects sck0 function in pin location pio0_6/sck0 (see ta b l e 1 2 3 ). 0x3 reserved. 31:2 - - reserved. -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 135 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) 8.4.44 iocon_dsr_loc 8.4.45 iocon_dcd_loc 8.4.46 iocon_ri_loc table 149. iocon dsr location register (iocon_dsr_loc, address 0x4004 40b4) bit description bit symbol value description reset value 1:0 dsrloc selects pin location for dsr function. 00 0x0 selects dsr function in pin location pio2_1/dsr/ sck1 (see ta b l e 11 4 ). 0x1 selects dsr function in pin location pio3_1/dsr (see ta b l e 1 3 8 ). 0x2 reserved. 0x3 reserved. 31:2 - - reserved. - table 150. iocon dcd location register (iocon_dcd_loc, address 0x4004 40b8) bit description bit symbol value description reset value 1:0 dcdloc selects pin location for dcd function. 00 0x0 selects dcd function in pin location pio2_2/dcd /miso1 (see ta b l e 1 2 7 ). 0x1 selects dcd function in pin location pio3_2/dcd (see ta b l e 1 4 3 ). 0x2 reserved. 0x3 reserved. 31:2 - - reserved. - table 151. iocon ri location register (iocon_ri_loc, address 0x4004 40bc) bit description bit symbol value description reset value 1:0 riloc selects pin locati on for ri function. 00 0x0 selects ri function in pin location pio2_3/ri /mosi1 (see ta b l e 1 3 9 ). 0x1 selects ri function in pin location pio3_3/ri (see table 147 ). 0x2 reserved. 0x3 reserved. 31:2 - - reserved. -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 136 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) 8.4.47 iocon_ssel1_loc 8.4.48 iocon_ct16b0_cap0_loc 8.4.49 iocon_sck1_loc table 152. iocon ssel1 location register (iocon_ssel1_loc, addr ess 0x4004 4018) bit description bit symbol value description reset value 1:0 ssel1loc selects pin location for ssel1 function. 00 0x0 selects ssel1 function in pin location pio2_0/dtr /ssel1 (see ta b l e 1 0 7 ).pio2_0/dtr /ssel1 0x1 selects ssel1 function in pin location pio2_4/ct16b1_mat1/ssel1 (see table 120 ). 0x2 reserved. 0x3 reserved. 31:2 - - reserved. - table 153. iocon ct16b0_cap0 location register (iocon_ct16b0_cap0_loc, address 0x4004 40c0) bit description bit symbol value description reset value 1:0 ct16b0_cap0loc selects pin loca tion for ct16b0_cap0 function. 00 0x0 selects ct16b0_cap0 function in pin location pio0_2/ssel0/ct16b0_cap0 (see table 111 ). 0x1 selects ct16b0_cap0 function in pin location pio3_3/ri /ct16b0 (see table 147 ). 0x2 reserved. 0x3 reserved. 31:2 - - reserved. - table 154. iocon sck1 location register (iocon_sck1_loc, address 0x4004 40c4) bit description bit symbol value description reset value 1:0 sck1loc selects pin location for sck1 function. 00 0x0 selects sck1 function in pin location pio2_1/dsr /sck1 (see ta b l e 11 4 ). 0x1 selects sck1 function in pin location pio3_2/dcd /ct16b0_mat2/sck1 (see table 143 ). 0x2 reserved. 0x3 reserved. 31:2 - - reserved. -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 137 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) 8.4.50 iocon_miso1_loc 8.4.51 iocon_mosi1_loc 8.4.52 iocon_ct32b0_cap0_loc table 155. iocon miso1 location register (iocon_miso1_loc, address 0x4004 40c8) bit description bit symbol value description reset value 1:0 miso1loc selects pin location for the miso1 function. 00 0x0 selects miso1 function in pin location pio2_2/dcd /miso1 (see table 127 ). 0x1 selects miso1 function in pin location pio1_10/ad6/ct16b1_mat1/miso1 (see table 131 ). 0x2 reserved. 0x3 reserved. 31:2 - - reserved. - table 156. iocon mosi1 location register (iocon_mosi1_loc, address 0x4004 40cc) bit description bit symbol value description reset value 1:0 mosi1loc selects pin location for the mosi1 function. 00 0x0 selects mosi1 function in pin location pio2_3/ri /mosi1 (see table 139 ). 0x1 selects mosi1 function in pin location pio1_9/ct16b1_mat0/mosi1 (see ta b l e 11 8 ). 0x2 reserved. 0x3 reserved. 31:2 - - reserved. - table 157. iocon ct32b0_cap0 location register (iocon_ct32b0_cap0_loc, address 0x4004 40d0) bit description bit symbol value description reset value 1:0 ct32b0_cap0loc selects pin location for the ct32b0_cap0 function. 00 0x0 selects ct32b0_cap0 function in pin location pio1_5/rts /ct32b0_cap0 (see table 144 ). 0x1 selects ct32b0_cap0 function in pin location pio2_9/ct32b0_cap0 ( ta b l e 1 2 5 ). 0x2 reserved. 0x3 reserved. 31:2 - - reserved. -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 138 of 543 nxp semiconductors um10398 chapter 8: lpc1100xl series: i/o configuration (ioconfig) 8.4.53 iocon_rxd_loc table 158. iocon rxd location register (iocon_rxd_loc, address 0x4004 40d4) bit description bit symbol value description reset value 1:0 rxdloc selects pin locati on for the rxd function. 00 0x0 selects rxd function in pin location pio1_6/rxd/ct32b0_mat0 (see table 145 ). 0x1 selects rxd function in pin location pio2_7/ct32b0_mat2/rxd (see table 112 ). 0x2 selects rxd function in pin location pio3_1/dsr /ct16b0_mat1/rxd (see table 138 ). 0x3 selects rxd function in pin location pio3_4/ct16b0_cap1/rxd (see table 119 ). 31:2 - - reserved. -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 139 of 543 9.1 how to read this chapter remark: this chapter applies to parts in the lpc1100, lpc1100c, and lpc1100l series for lqfp and hvqfn packages. the lpc111x are available in three packages: lqfp48 (lpc1113, lpc1114), and hvqfn33 (LPC1111, lpc1112, lpc1113, lpc1114). the lpc11cxx parts are available in a lqfp48 package. the lpc11d14 part is available as a dual-chip module in a lqfp100 package. um10398 chapter 9: lpc111x/lpc11cxx pi n configuration (lpc1100, lpc1100c, and lpc1100l ser ies, hvqfn/lqfp packages) rev. 12.1 ? 7 august 2013 user manual table 159. lpc11(d)1x/lpc11cxx pin configurations part lqfp48 hvqfn24 hvqfn33 lqfp100 LPC1111 pin configuration - - figure 17 - pin description - - table 161 - lpc1112 pin configuration - figure 18 figure 17 - pin description - table 162 table 161 - lpc1113 pin configuration figure 16 - figure 17 - pin description table 160 - table 161 - lpc1114 pin configuration figure 16 - figure 17 - pin description table 160 - table 161 - lpc11c12 pin configuration figure 19 --- pin description table 160 --- lpc11c14 pin configuration figure 19 --- pin description table 160 --- lpc11c22 pin configuration figure 20 --- pin description table 163 --- lpc11c24 pin configuration figure 20 --- pin description table 163 --- lpc11d14 pin configuration - - - figure 21 pin description - - - table 164
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 140 of 543 nxp semiconductors um10398 chapter 9: lpc111x/lpc11cxx pin configuration (lpc1100, lpc1100c, 9.2 lpc111x pin configuration fig 16. pin configuration lqfp48 package lpc1113fbd48/301 lpc1113fbd48/302 lpc1114fbd48/301 lpc1114fbd48/302 pio2_6 pio3_0/dtr pio2_0/dtr/ssel1 r/pio1_2/ad3/ct32b1_mat1 reset/pio0_0 r/pio1_1/ad2/ct32b1_mat0 pio0_1/clkout/ct32b0_mat2 r/pio1_0/ad1/ct32b1_cap0 v ss r/pio0_11/ad0/ct32b0_mat3 xtalin pio2_11/sck0 xtalout pio1_10/ad6/ct16b1_mat1 v dd swclk/pio0_10/sck0/ct16b0_mat2 pio1_8/ct16b1_cap0 pio0_9/mosi0/ct16b0_mat1 pio0_2/ssel0/ct16b0_cap0 pio0_8/miso0/ct16b0_mat0 pio2_7 pio2_2/dcd/miso1 pio2_8 pio2_10 pio2_1/dsr/sck1 pio3_3/ri pio0_3 pio1_7/txd/ct32b0_mat1 pio0_4/scl pio1_6/rxd/ct32b0_mat0 pio0_5/sda pio1_5/rts/ct32b0_cap0 pio1_9/ct16b1_mat0 v dd pio3_4 pio3_2/dcd pio2_4 pio1_11/ad7 pio2_5 v ss pio3_5 pio1_4/ad5/ct32b1_mat3/wakeup pio0_6/sck0 swdio/pio1_3/ad4/ct32b1_mat2 pio0_7/cts pio2_9 pio2_3/ri/mosi1 pio3_1/dsr 002aae697 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 37 24
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 141 of 543 nxp semiconductors um10398 chapter 9: lpc111x/lpc11cxx pin configuration (lpc1100, lpc1100c, fig 17. pin configuration hvqfn33 package 002aae698 transparent top view pio0_8/miso0/ct16b0_mat0 pio1_8/ct16b1_cap0 pio0_2/ssel0/ct16b0_cap0 pio0_9/mosi0/ct16b0_mat1 v dd swclk/pio0_10/sck0/ct16b0_mat2 xtalout pio1_10/ad6/ct16b1_mat1 xtalin r/pio0_11/ad0/ct32b0_mat3 pio0_1/clkout/ct32b0_mat2 r/pio1_0/ad1/ct32b1_cap0 reset/pio0_0 r/pio1_1/ad2/ct32b1_mat0 pio2_0/dtr r/pio1_2/ad3/ct32b1_mat1 pio0_3 pio0_4/scl pio0_5/sda pio1_9/ct16b1_mat0 pio3_4 pio3_5 pio0_6/sck0 pio0_7/cts pio1_7/txd/ct32b0_mat1 pio1_6/rxd/ct32b0_mat0 pio1_5/rts/ct32b0_cap0 v dd pio3_2 pio1_11/ad7 pio1_4/ad5/ct32b1_mat3/wakeup swdio/pio1_3/ad4/ct32b1_mat2 8 17 7 18 6 19 5 20 4 21 3 22 2 23 1 24 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 terminal 1 index area 33 v ss fig 18. pin configuration hvqfn24 package 002aah173 lpc1112fhn24 transparent top view pio0_9 v dd pio1_8 pio0_10 xtalin pio0_11 v ss pio1_0 pio0_1 pio1_1 reset/pio0_0 pio1_2 pio0_2 pio0_4 pio0_5 pio0_6 pio0_7 pio0_8 pio1_7 pio1_6 v dd v ss pio1_4 pio1_3 terminal 1 index area 6 13 5 14 4 15 3 16 2 17 1 18 7 8 9 10 11 12 24 23 22 21 20 19
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 142 of 543 nxp semiconductors um10398 chapter 9: lpc111x/lpc11cxx pin configuration (lpc1100, lpc1100c, 9.3 lpc11cxx pin configuration fig 19. pin configuration lqfp48 package lpc11c12fbd48/301 lpc11c14fbd48/301 pio2_6 pio3_0/dtr pio2_0/dtr/ssel1 r/pio1_2/ad3/ct32b1_mat1 reset/pio0_0 r/pio1_1/ad2/ct32b1_mat0 pio0_1/clkout/ct32b0_mat2 r/pio1_0/ad1/ct32b1_cap0 v ss r/pio0_11/ad0/ct32b0_mat3 xtalin pio2_11/sck0 xtalout pio1_10/ad6/ct16b1_mat1 v dd swclk/pio0_10/sck0/ct16b0_mat2 pio1_8/ct16b1_cap0 pio0_9/mosi0/ct16b0_mat1 pio0_2/ssel0/ct16b0_cap0 pio0_8/miso0/ct16b0_mat0 pio2_7 pio2_2/dcd/miso1 pio2_8 pio2_10 pio2_1/dsr/sck1 pio3_3/ri pio0_3 pio1_7/txd/ct32b0_mat1 pio0_4/scl pio1_6/rxd/ct32b0_mat0 pio0_5/sda pio1_5/rts/ct32b0_cap0 pio1_9/ct16b1_mat0 v dd pio2_4 pio3_2/dcd can_rxd pio1_11/ad7 can_txd v ss pio2_5 pio1_4/ad5/ct32b1_mat3/wakeup pio0_6/sck0 swdio/pio1_3/ad4/ct32b1_mat2 pio0_7/cts pio2_9 pio2_3/ri/mosi1 pio3_1/dsr 002aaf266 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 37 24
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 143 of 543 nxp semiconductors um10398 chapter 9: lpc111x/lpc11cxx pin configuration (lpc1100, lpc1100c, fig 20. pin configuration (lpc11c22/c24) lpc11c22fbd48/301 lpc11c24fbd48/301 pio2_6 pio3_0/dtr pio2_0/dtr/ssel1 r/pio1_2/ad3/ct32b1_mat1 reset/pio0_0 r/pio1_1/ad2/ct32b1_mat0 pio0_1/clkout/ct32b0_mat2 r/pio1_0/ad1/ct32b1_cap0 v ss r/pio0_11/ad0/ct32b0_mat3 xtalin pio2_11/sck0 xtalout pio1_10/ad6/ct16b1_mat1 v dd swclk/pio0_10/sck0/ct16b0_mat2 pio1_8/ct16b1_cap0 pio0_9/mosi0/ct16b0_mat1 pio0_2/ssel0/ct16b0_cap0 pio0_8/miso0/ct16b0_mat0 pio2_7 pio2_2/dcd/miso1 pio2_8 pio2_10 pio2_1/dsr/sck1 pio3_3/ri pio0_3 pio1_7/txd/ct32b0_mat1 pio0_4/scl pio1_6/rxd/ct32b0_mat0 pio0_5/sda pio1_5/rts/ct32b0_cap0 vdd_can v dd canl pio3_2/dcd canh pio1_11/ad7 v cc v ss gnd pio1_4/ad5/ct32b1_mat3/wakeup stb swdio/pio1_3/ad4/ct32b1_mat2 pio0_6/sck0 pio0_7/cts pio2_3/ri/mosi1 pio3_1/dsr 002aaf909 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 37 24
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 144 of 543 nxp semiconductors um10398 chapter 9: lpc111x/lpc11cxx pin configuration (lpc1100, lpc1100c, 9.4 lpc11d14 pin configuration fig 21. pin configuration lqfp100 package lpc11d14fbd100/302 pio1_7 s29 pio3_3 s28 n.c. s27 pio2_6 s26 pio2_0 s25 reset/pio0_0 s24 pio0_1 s23 v ss s22 xtalin s21 xtalout s20 v dd s19 pio1_8 s18 pio0_2 s17 pio2_7 s16 pio1_9 s10 pio3_4 s9 pio2_4 s8 pio2_5 s7 pio3_5 pio2_8 pio2_1 pio0_3 pio0_4 pio0_5 s6 s15 s14 s13 s12 s11 pio0_6 s5 pio0_7 pio1_6 pio2_9 pio1_5 pio2_10 v dd s34 pio3_2 s35 pio1_11 s36 v ss s37 pio1_4 s38 swdio/pio1_3 s39 pio2_3 lcd_ sda pio3_1 lcd_ scl pio3_0 sync r/pio1_2 clk r/pio1_1 v dd(lcd) r/pio1_0 bp3 pio0_8 s0 pio2_2 s1 s33 s2 s32 s3 v ss(lcd) v lcd bp0 bp2 bp1 s31 r/pio0_11 pio2_11 pio1_10 swclk/pio0_10 pio0_9 s4 s30 002aag450 1 2 3 4 5 6 7 8 9 10 11 12 13 14 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 56 55 54 53 52 51 15 16 17 18 19 61 60 59 58 57 26 27 28 29 30 31 32 33 34 35 36 37 38 39 45 46 47 48 49 50 10 0 99 98 97 96 95 94 93 92 91 90 89 88 87 81 80 79 78 77 76 40 41 42 43 44 86 85 84 83 82
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 145 of 543 nxp semiconductors um10398 chapter 9: lpc111x/lpc11cxx pin configuration (lpc1100, lpc1100c, 9.5 lpc111x/lpc11cxx pin description table 160. lpc1113/14 and lpc11c12/c14 pin description table (lqfp48 package) symbol pin type description pio0_0 to pio0_11 i/o port 0 ? port 0 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 0 pins depends on the function selected through the ioconfig register block. reset /pio0_0 3 [1] [2] i reset ? external reset input: a low on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. i/o pio0_0 ? general purpose digital input/output pin. pio0_1/clkout/ ct32b0_mat2 4 [3] [2] i/o pio0_1 ? general purpose digital input/outpu t pin. a low level on this pin during reset starts the flash isp command handler via uart (if pio0_3 is high) or via c_can (if pio0_3 is low). o clkout ? clockout pin. o ct32b0_mat2 ? match output 2 for 32-bit timer 0. pio0_2/ssel0/ ct16b0_cap0 10 [3] [2] i/o pio0_2 ? general purpose digital input/output pin. o ssel0 ? slave select for spi0. i ct16b0_cap0 ? capture input 0 for 16-bit timer 0. pio0_3 14 [3] [2] i/o pio0_3 ? general purpose digital input/output pin. this pin is monitored during reset: together with a low level on pin pio0_1, a low level starts the flash isp command handler via c_can and a high level starts the flash isp command handler via uart. pio0_4/scl 15 [4] [2] i/o pio0_4 ? general purpose digital inpu t/output pin (open-drain). i/o scl ? i 2 c-bus, open-drain clock input/outpu t. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_5/sda 16 [4] [2] i/o pio0_5 ? general purpose digital inpu t/output pin (open-drain). i/o sda ? i 2 c-bus, open-drain data input/out put. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_6/sck0 22 [3] [2] i/o pio0_6 ? general purpose digital input/output pin. i/o sck0 ? serial clock for spi0. pio0_7/cts 23 [3] [2] i/o pio0_7 ? general purpose digital input/ output pin (high-current output driver). i cts ? clear to send input for uart. pio0_8/miso0/ ct16b0_mat0 27 [3] [2] i/o pio0_8 ? general purpose digital input/output pin. i/o miso0 ? master in slave out for spi0. o ct16b0_mat0 ? match output 0 for 16-bit timer 0. pio0_9/mosi0/ ct16b0_mat1 28 [3] [2] i/o pio0_9 ? general purpose digital input/output pin. i/o mosi0 ? master out slave in for spi0. o ct16b0_mat1 ? match output 1 for 16-bit timer 0. swclk/pio0_10/ sck0/ct16b0_mat2 29 [3] [2] i swclk ? serial wire clock. i/o pio0_10 ? general purpose digital input/output pin. i/o sck0 ? serial clock for spi0. o ct16b0_mat2 ? match output 2 for 16-bit timer 0.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 146 of 543 nxp semiconductors um10398 chapter 9: lpc111x/lpc11cxx pin configuration (lpc1100, lpc1100c, r/pio0_11/ ad0/ct32b0_mat3 32 [5] [2] i r ? reserved. configure for an alternat e function in the ioconfig block. i/o pio0_11 ? general purpose digital input/output pin. i ad0 ? a/d converter, input 0. o ct32b0_mat3 ? match output 3 for 32-bit timer 0. pio1_0 to pio1_11 i/o port 1 ? port 1 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 1 pins depends on the function selected through the ioconfig register block. r/pio1_0/ ad1/ct32b1_cap0 33 [5] [2] i r ? reserved. configure for an alternat e function in the ioconfig block. i/o pio1_0 ? general purpose digital input/output pin. i ad1 ? a/d converter, input 1. i ct32b1_cap0 ? capture input 0 for 32-bit timer 1. r/pio1_1/ ad2/ct32b1_mat0 34 [5] o r ? reserved. configure for an alternat e function in the ioconfig block. i/o pio1_1 ? general purpose digital input/output pin. i ad2 ? a/d converter, input 2. o ct32b1_mat0 ? match output 0 for 32-bit timer 1. r/pio1_2/ ad3/ct32b1_mat1 35 [5] i r ? reserved. configure for an alternat e function in the ioconfig block. i/o pio1_2 ? general purpose digital input/output pin. i ad3 ? a/d converter, input 3. o ct32b1_mat1 ? match output 1 for 32-bit timer 1. swdio/pio 1_3/ad4/ ct32b1_mat2 39 [5] i/o swdio ? serial wire debug input/output. i/o pio1_3 ? general purpose digital input/output pin. i ad4 ? a/d converter, input 4. o ct32b1_mat2 ? match output 2 for 32-bit timer 1. pio1_4/ad5/ ct32b1_mat3/wakeup 40 [5] i/o pio1_4 ? general purpose digital input/output pin. i ad5 ? a/d converter, input 5. o ct32b1_mat3 ? match output 3 for 32-bit timer 1. i wakeup ? deep power-down mode wake-up pin. this pin must be pulled high externally to enter deep power-down mode and pulled low to exit deep power-down mode. pio1_5/rts / ct32b0_cap0 45 [3] i/o pio1_5 ? general purpose digital input/output pin. o rts ? request to send output for uart. i ct32b0_cap0 ? capture input 0 for 32-bit timer 0. pio1_6/rxd/ ct32b0_mat0 46 [3] i/o pio1_6 ? general purpose digital input/output pin. i rxd ? receiver input for uart. o ct32b0_mat0 ? match output 0 for 32-bit timer 0. pio1_7/txd/ ct32b0_mat1 47 [3] i/o pio1_7 ? general purpose digital input/output pin. o txd ? transmitter output for uart. o ct32b0_mat1 ? match output 1 for 32-bit timer 0. pio1_8/ct16b1_cap0 9 [3] i/o pio1_8 ? general purpose digital input/output pin. i ct16b1_cap0 ? capture input 0 for 16-bit timer 1. pio1_9/ct16b1_mat0 17 [3] i/o pio1_9 ? general purpose digital input/output pin. o ct16b1_mat0 ? match output 0 for 16-bit timer 1. table 160. lpc1113/14 and lpc11c12/c14 pin description table (lqfp48 package) ?continued symbol pin type description
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 147 of 543 nxp semiconductors um10398 chapter 9: lpc111x/lpc11cxx pin configuration (lpc1100, lpc1100c, pio1_10/ad6/ ct16b1_mat1 30 [5] i/o pio1_10 ? general purpose digital input/output pin. i ad6 ? a/d converter, input 6. o ct16b1_mat1 ? match output 1 for 16-bit timer 1. pio1_11/ad7 42 [5] i/o pio1_11 ? general purpose digital input/output pin. i ad7 ? a/d converter, input 7. pio2_0 to pio2_11 i/o port 2 ? port 2 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 2 pins depends on the function selected through the ioconfig register block. pio2_0/dtr /ssel1 2 [3] i/o pio2_0 ? general purpose digital input/output pin. o dtr ? data terminal ready output for uart. o ssel1 ? slave select for spi1. pio2_1/dsr /sck1 13 [3] i/o pio2_1 ? general purpose digital input/output pin. i dsr ? data set ready input for uart. i/o sck1 ? serial clock for spi1. pio2_2/dcd /miso1 26 [3] i/o pio2_2 ? general purpose digital input/output pin. i dcd ? data carrier detect input for uart. i/o miso1 ? master in slave out for spi1. pio2_3/ri /mosi1 38 [3] i/o pio2_3 ? general purpose digital input/output pin. i ri ? ring indicator input for uart. i/o mosi1 ? master out slave in for spi1. pio2_4 19 [3] i/o pio2_4 ? general purpose digital input/ output pin. (lpc1113/14 only). pio2_4 18 [3] i/o pio2_4 ? general purpose digital input/out put pin. (lpc11c12/c14 only). pio2_5 20 [3] i/o pio2_5 ? general purpose digital input/ output pin. lpc1113/14 only). pio2_5 21 [3] i/o pio2_5 ? general purpose digital input/out put pin. (lpc11c12/c14 only). pio2_6 1 [3] i/o pio2_6 ? general purpose digital input/output pin. pio2_7 11 [3] i/o pio2_7 ? general purpose digital input/output pin. pio2_8 12 [3] i/o pio2_8 ? general purpose digital input/output pin. pio2_9 24 [3] i/o pio2_9 ? general purpose digital input/output pin. pio2_10 25 [3] i/o pio2_10 ? general purpose digital input/output pin. pio2_11/sck0 31 [3] i/o pio2_11 ? general purpose digital input/output pin. i/o sck0 ? serial clock for spi0. pio3_0 to pio3_5 i/o port 3 ? port 3 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 3 pins depends on the function selected through the ioconfig register block. pins pio3_6 to pio3_11 are not available. pio3_0/dtr 36 [3] i/o pio3_0 ? general purpose digital input/output pin. o dtr ? data terminal ready output for uart. pio3_1/dsr 37 [3] i/o pio3_1 ? general purpose digital input/output pin. i dsr ? data set ready input for uart. pio3_2/dcd 43 [3] i/o pio3_2 ? general purpose digital input/output pin. i dcd ? data carrier detect input for uart. table 160. lpc1113/14 and lpc11c12/c14 pin description table (lqfp48 package) ?continued symbol pin type description
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 148 of 543 nxp semiconductors um10398 chapter 9: lpc111x/lpc11cxx pin configuration (lpc1100, lpc1100c, [1] 5 v tolerant pad. reset functionality is not available in deep power-down mode. use the wakeup pin to reset the chip and wake up from deep power-down mode. [2] serves as deep-sleep wake-up input pin to the start logic independently of selected pin function (see the lpc111x/11c1x user manual ). [3] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis. [4] i 2 c-bus pads compliant with the i 2 c-bus specification for i 2 c standard mode and i 2 c fast-mode plus. [5] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s, configurable hysteresis, and analog input. when configured as a adc input, digital section of t he pad is disabled and the pin is not 5 v tolerant. [6] 5 v tolerant digital i/o pad without pull-up/pull-down resistors. [7] when the system oscillator is not used, connect xtalin and xtalout as follows: xtalin can be left floating or can be grounde d (grounding is preferred to reduce susceptibilit y to noise). xtalout should be left floating. pio3_3/ri 48 [3] i/o pio3_3 ? general purpose digital input/output pin. i ri ? ring indicator input for uart. pio3_4 18 [3] i/o pio3_4 ? general purpose digital input/ output pin. (lpc1113/14 only). pio3_5 21 [3] i/o pio3_5 ? general purpose digital input/ output pin. (lpc1113/14 only). can_rxd 19 [6] i can_rxd ? c_can receive data input. (lpc11c12/14 only). can_txd 20 [6] o can_txd ? c_can transmit data output. (lpc11c12/14 only). v dd 8; 44 i 3.3 v supply voltage to the internal regulator, the external rail, and the adc. also used as the adc reference voltage. xtalin 6 [7] i input to the oscillator circuit and inte rnal clock generator circuits. input voltage must not exceed 1.8 v. xtalout 7 [7] o output from the oscillator amplifier. v ss 5; 41 i ground. table 160. lpc1113/14 and lpc11c12/c14 pin description table (lqfp48 package) ?continued symbol pin type description
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 149 of 543 nxp semiconductors um10398 chapter 9: lpc111x/lpc11cxx pin configuration (lpc1100, lpc1100c, table 161. LPC1111/12/13/14 pin description table (hvqfn33 package) symbol pin type description pio0_0 to pio0_11 i/o port 0 ? port 0 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 0 pins depends on the function selected through the ioconfig register block. reset /pio0_0 2 [1] [2] i reset ? external reset input: a low on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. i/o pio0_0 ? general purpose digital input/output pin. pio0_1/clkout/ ct32b0_mat2 3 [3] [2] i/o pio0_1 ? general purpose digital input/output pin. a low level on this pin during reset starts the isp command handler. o clkout ? clock out pin. o ct32b0_mat2 ? match output 2 for 32-bit timer 0. pio0_2/ssel0/ ct16b0_cap0 8 [3] [2] i/o pio0_2 ? general purpose digital input/output pin. o ssel0 ? slave select for spi0. i ct16b0_cap0 ? capture input 0 for 16-bit timer 0. pio0_3 9 [3] [2] i/o pio0_3 ? general purpose digita l input/output pin. pio0_4/scl 10 [4] [2] i/o pio0_4 ? general purpose digital input /output pin (open-drain). i/o scl ? i 2 c-bus, open-drain clock input/output. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_5/sda 11 [4] [2] i/o pio0_5 ? general purpose digital input /output pin (open-drain). i/o sda ? i 2 c-bus, open-drain data input/outp ut. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_6/sck0 15 [3] [2] i/o pio0_6 ? general purpose digital input/output pin. i/o sck0 ? serial clock for spi0. pio0_7/cts 16 [3] [2] i/o pio0_7 ? general purpose digital input/o utput pin (high-current output driver). i cts ? clear to send input for uart. pio0_8/miso0/ ct16b0_mat0 17 [3] [2] i/o pio0_8 ? general purpose digital input/output pin. i/o miso0 ? master in slave out for spi0. o ct16b0_mat0 ? match output 0 for 16-bit timer 0. pio0_9/mosi0/ ct16b0_mat1 18 [3] [2] i/o pio0_9 ? general purpose digital input/output pin. i/o mosi0 ? master out slave in for spi0. o ct16b0_mat1 ? match output 1 for 16-bit timer 0. swclk/pio0_10/sck0/ ct16b0_mat2 19 [3] [2] i swclk ? serial wire clock. i/o pio0_10 ? general purpose digital input/output pin. i/o sck0 ? serial clock for spi0. o ct16b0_mat2 ? match output 2 for 16-bit timer 0. r/pio0_11/ad0/ ct32b0_mat3 21 [5] [2] i r ? reserved. configure for an alternat e function in the ioconfig block. i/o pio0_11 ? general purpose digital input/output pin. i ad0 ? a/d converter, input 0. o ct32b0_mat3 ? match output 3 for 32-bit timer 0. pio1_0 to pio1_11 i/o port 1 ? port 1 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 1 pins depends on the function selected through the ioconfig register block.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 150 of 543 nxp semiconductors um10398 chapter 9: lpc111x/lpc11cxx pin configuration (lpc1100, lpc1100c, r/pio1_0/ad1/ ct32b1_cap0 22 [5] [2] i r ? reserved. configure for an alternat e function in the ioconfig block. i/o pio1_0 ? general purpose digital input/output pin. i ad1 ? a/d converter, input 1. i ct32b1_cap0 ? capture input 0 for 32-bit timer 1. r/pio1_1/ad2/ ct32b1_mat0 23 [5] o r ? reserved. configure for an alternat e function in the ioconfig block. i/o pio1_1 ? general purpose digital input/output pin. i ad2 ? a/d converter, input 2. o ct32b1_mat0 ? match output 0 for 32-bit timer 1. r/pio1_2/ad3/ ct32b1_mat1 24 [5] i r ? reserved. configure for an alternat e function in the ioconfig block. i/o pio1_2 ? general purpose digital input/output pin. i ad3 ? a/d converter, input 3. o ct32b1_mat1 ? match output 1 for 32-bit timer 1. swdio/pio 1_3/ad4/ ct32b1_mat2 25 [5] i/o swdio ? serial wire debug input/output. i/o pio1_3 ? general purpose digital input/output pin. i ad4 ? a/d converter, input 4. o ct32b1_mat2 ? match output 2 for 32-bit timer 1. pio1_4/ad5/ ct32b1_mat3/wakeup 26 [5] i/o pio1_4 ? general purpose digital input/output pin. i ad5 ? a/d converter, input 5. o ct32b1_mat3 ? match output 3 for 32-bit timer 1. i wakeup ? deep power-down mode wake-up pin. this pin must be pulled high externally to enter deep power-down mode and pulled low to exit deep power-down mode. pio1_5/rts / ct32b0_cap0 30 [3] i/o pio1_5 ? general purpose digital input/output pin. o rts ? request to send output for uart. i ct32b0_cap0 ? capture input 0 for 32-bit timer 0. pio1_6/rxd/ ct32b0_mat0 31 [3] i/o pio1_6 ? general purpose digital input/output pin. i rxd ? receiver input for uart. o ct32b0_mat0 ? match output 0 for 32-bit timer 0. pio1_7/txd/ ct32b0_mat1 32 [3] i/o pio1_7 ? general purpose digital input/output pin. o txd ? transmitter output for uart. o ct32b0_mat1 ? match output 1 for 32-bit timer 0. pio1_8/ct16b1_cap0 7 [3] i/o pio1_8 ? general purpose digital input/output pin. i ct16b1_cap0 ? capture input 0 for 16-bit timer 1. pio1_9/ct16b1_mat0 12 [3] i/o pio1_9 ? general purpose digital input/output pin. o ct16b1_mat0 ? match output 0 for 16-bit timer 1. pio1_10/ad6/ ct16b1_mat1 20 [5] i/o pio1_10 ? general purpose digital input/output pin. i ad6 ? a/d converter, input 6. o ct16b1_mat1 ? match output 1 for 16-bit timer 1. pio1_11/ad7 27 [5] i/o pio1_11 ? general purpose digital input/output pin. i ad7 ? a/d converter, input 7. table 161. LPC1111/12/13/14 pin description table (hvqfn33 package) ?continued symbol pin type description
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 151 of 543 nxp semiconductors um10398 chapter 9: lpc111x/lpc11cxx pin configuration (lpc1100, lpc1100c, [1] 5 v tolerant pad. reset functionality is not available in deep power-down mode. use the wakeup pin to reset the chip and wake up from deep power-down mode. [2] serves as deep-sleep wake-up input pin to the start logic independently of selected pin function (see the lpc111x/11c1x user manual ). [3] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis. [4] i 2 c-bus pads compliant with the i 2 c-bus specification for i 2 c standard mode and i 2 c fast-mode plus. [5] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s, configurable hysteresis, and analog input. when configured as a adc input, digital section of t he pad is disabled, and the pin is not 5 v tolerant. [6] when the system oscillator is not used, connect xtalin and xtalout as follows: xtalin can be left floating or can be grounde d (grounding is preferred to reduce susceptibilit y to noise). xtalout should be left floating. pio2_0 i/o port 2 ? port 2 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 2 pins depends on the function selected through the ioconfig regist er block. pins pio2_1 to pio2_11 are not available. pio2_0/dtr 1 [3] i/o pio2_0 ? general purpose digital input/output pin. o dtr ? data terminal ready output for uart. pio3_0 to pio3_5 i/o port 3 ? port 3 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 3 pins depends on the function selected through the ioconfig regist er block. pins pio3_0, pio3_1, pio3_3 and pio3_6 to pio3_11 are not available. pio3_2 28 [3] i/o pio3_2 ? general purpose digital input/output pin. pio3_4 13 [3] i/o pio3_4 ? general purpose digital input/output pin. pio3_5 14 [3] i/o pio3_5 ? general purpose digital input/output pin. v dd 6; 29 i 3.3 v supply voltage to the internal regulator, the external rail, and the adc. also used as the adc reference voltage. xtalin 4 [6] i input to the oscillator circuit and in ternal clock generator circuits. input voltage must not exceed 1.8 v. xtalout 5 [6] o output from the oscillator amplifier. v ss 33 - thermal pad. connect to ground. table 161. LPC1111/12/13/14 pin description table (hvqfn33 package) ?continued symbol pin type description table 162. lpc1112fhn24 pin description table (hvqfn24 package) symbol hvqfn pin start logic input type reset state [1] description reset /pio0_0 1 [1] yes i i; pu reset ? external reset input with 20 ns glitch filter. a low-going pulse as short as 50 ns on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. i/o - pio0_0 ? general purpose digital inpu t/output pin with 10 ns glitch filter. pio0_1/clkout/ ct32b0_mat2 2 [3] yes i/o i; pu pio0_1 ? general purpose digital input/output pin. a low level on this pin during reset starts the isp command handler. o- clkout ? clockout pin. o- ct32b0_mat2 ? match output 2 for 32-bit timer 0. pio0_2/ssel0/ ct16b0_cap0 7 [3] yes i/o i; pu pio0_2 ? general purpose digital input/output pin. i/o - ssel0 ? slave select for spi0. i- ct16b0_cap0 ? capture input 0 for 16-bit timer 0.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 152 of 543 nxp semiconductors um10398 chapter 9: lpc111x/lpc11cxx pin configuration (lpc1100, lpc1100c, pio0_4/scl 8 [4] yes i/o i; ia pio0_4 ? general purpose digital input/output pin (open-drain). i/o - scl ? i 2 c-bus, open-drain clock input/output. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_5/sda 9 [4] yes i/o i; ia pio0_5 ? general purpose digital input/output pin (open-drain). i/o - sda ? i 2 c-bus, open-drain data input/output. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_6/sck0 10 [3] yes i/o i; pu pio0_6 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for spi0. pio0_7/cts 11 [3] yes i/o i; pu pio0_7 ? general purpose digital input/output pin (high-current output driver). i- cts ? clear to send input for uart. pio0_8/miso0/ ct16b0_mat0 12 [3] yes i/o i; pu pio0_8 ? general purpose digital input/output pin. i/o - miso0 ? master in slave out for spi0. o- ct16b0_mat0 ? match output 0 for 16-bit timer 0. pio0_9/mosi0/ ct16b0_mat1 13 [3] yes i/o i; pu pio0_9 ? general purpose digital input/output pin. i/o - mosi0 ? master out slave in for spi0. o- ct16b0_mat1 ? match output 1 for 16-bit timer 0. swclk/pio0_10/ sck0/ ct16b0_mat2 14 [3] yes i i; pu swclk ? serial wire clock. i/o - pio0_10 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for spi0. o- ct16b0_mat2 ? match output 2 for 16-bit timer 0. r/pio0_11/ ad0/ct32b0_mat3 15 [5] yes i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio0_11 ? general purpose digital input/output pin. i- ad0 ? a/d converter, input 0. o- ct32b0_mat3 ? match output 3 for 32-bit timer 0. r/pio1_0/ ad1/ct32b1_cap0 16 [5] yes i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_0 ? general purpose digital input/output pin. i- ad1 ? a/d converter, input 1. i- ct32b1_cap0 ? capture input 0 for 32-bit timer 1. r/pio1_1/ ad2/ct32b1_mat0 17 [5] no o i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_1 ? general purpose digital input/output pin. i- ad2 ? a/d converter, input 2. o- ct32b1_mat0 ? match output 0 for 32-bit timer 1. table 162. lpc1112fhn24 pin description table (hvqfn24 package) symbol hvqfn pin start logic input type reset state [1] description
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 153 of 543 nxp semiconductors um10398 chapter 9: lpc111x/lpc11cxx pin configuration (lpc1100, lpc1100c, [1] pin state at reset for default function: i = input; o = ou tput; pu = internal pull-up enabled (pins pulled up to full v dd level); ia = inactive, no pull-up/down enabled. [2] reset functionality is not available in deep power-down mode. us e the wakeup pin to reset the chip and wake up from deep power-down mode. an external pull-up resistor is required on this pin for the deep power-down mode. [3] pad providing digital i/o functions with configurable pull-up/pull-down resistors and confi gurable hysteresis. [4] i 2 c-bus pads compliant with the i 2 c-bus specification for i 2 c standard mode and i 2 c fast-mode plus. [5] pad providing digital i/o functions with configurable pull-up/pull-down resistor s, configurable hysteresis, and analog input . when configured as a adc input, digital section of the pad is disabled. [6] when the system oscillator is not used, connect xtalin and xtalout as follows: xtalin can be left floating or can be grounde d (grounding is preferred to reduce susceptibilit y to noise). xtalout should be left floating. r/pio1_2/ ad3/ct32b1_mat1 18 [5] no i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_2 ? general purpose digital input/output pin. i- ad3 ? a/d converter, input 3. o- ct32b1_mat1 ? match output 1 for 32-bit timer 1. swdio/pio1_3/ ad4/ct32b1_mat2 19 [5] no i/o i; pu swdio ? serial wire debug input/output. i/o - pio1_3 ? general purpose digital input/output pin. i- ad4 ? a/d converter, input 4. o- ct32b1_mat2 ? match output 2 for 32-bit timer 1. pio1_4/ad5/ ct32b1_mat3/ wakeup 20 [5] no i/o i; pu pio1_4 ? general purpose digital inpu t/output pin with 10 ns glitch filter. i- ad5 ? a/d converter, input 5. o- ct32b1_mat3 ? match output 3 for 32-bit timer 1. i- wakeup ? deep power-down mode wake-up pin with 20 ns glitch filter. this pin must be pulled high externally to enter deep power-down mode and pulled low to exit deep power-down mode. a low-going pulse as short as 50 ns wakes up the part. pio1_6/rxd/ ct32b0_mat0 23 [3] no i/o i; pu pio1_6 ? general purpose digital input/output pin. i- rxd ? receiver input for uart. o- ct32b0_mat0 ? match output 0 for 32-bit timer 0. pio1_7/txd/ ct32b0_mat1 24 [3] no i/o i; pu pio1_7 ? general purpose digital input/output pin. o- txd ? transmitter output for uart. o- ct32b0_mat1 ? match output 1 for 32-bit timer 0. pio1_8/ ct16b1_cap0 6 [3] no i/o i; pu pio1_8 ? general purpose digital input/output pin. i- ct16b1_cap0 ? capture input 0 for 16-bit timer 1. xtalin 4 [7] - i - input to the oscillator circuit and internal clock generator circuits. input voltage must not exceed 1.8 v. v dd 5; 22 - i - 3.3 v supply voltage to the internal regulator, the external rail, and the adc. also used as the adc reference voltage. v ss 3; 21 - i - ground. table 162. lpc1112fhn24 pin description table (hvqfn24 package) symbol hvqfn pin start logic input type reset state [1] description
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 154 of 543 nxp semiconductors um10398 chapter 9: lpc111x/lpc11cxx pin configuration (lpc1100, lpc1100c, table 163. lpc11c24/c22 pin description table (lqfp48 package) symbol pin type description pio0_0 to pio0_11 port 0 ? port 0 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 0 pins dep ends on the function selected through the ioconfig register block. reset /pio0_0 3 [1] i reset ? external reset input with 20 ns glitch filter. a low-going pulse as short as 50 ns on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. i/o pio0_0 ? general purpose digital input/outp ut pin with 10 ns glitch filter. pio0_1/clkout/ ct32b0_mat2 4 [3] i/o pio0_1 ? general purpose digital input/output pin. a low level on this pin during reset starts the flash isp command handler via uart (if pio0_3 is high) or via c_can (if pio0_3 is low). o clkout ? clockout pin. o ct32b0_mat2 ? match output 2 for 32-bit timer 0. pio0_2/ssel0/ ct16b0_cap0 10 [3] i/o pio0_2 ? general purpose digital input/output pin. i/o ssel0 ? slave select for spi0. i ct16b0_cap0 ? capture input 0 for 16-bit timer 0. pio0_3 14 [3] i/o pio0_3 ? general purpose digital input/output pin. this pin is monitored during reset: together with a low level on pin pio0_1, a low level starts the flash isp command handler via c_can and a high level starts the flash isp command handler via uart. pio0_4/scl 15 [4] i/o pio0_4 ? general purpose digital input/output pin (open-drain). i/o scl ? i 2 c-bus, open-drain clock input/output. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_5/sda 16 [4] i/o pio0_5 ? general purpose digital input/output pin (open-drain). i/o sda ? i 2 c-bus, open-drain data input/outpu t. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_6/sck0 23 [3] i/o pio0_6 ? general purpose digital input/output pin. i/o sck0 ? serial clock for spi0. pio0_7/cts 24 [3] i/o pio0_7 ? general purpose digital input/output pin (high-current output driver). i cts ? clear to send input for uart. pio0_8/miso0/ ct16b0_mat0 27 [3] i/o pio0_8 ? general purpose digital input/output pin. i/o miso0 ? master in slave out for spi0. o ct16b0_mat0 ? match output 0 for 16-bit timer 0. pio0_9/mosi0/ ct16b0_mat1 28 [3] i/o pio0_9 ? general purpose digital input/output pin. i/o mosi0 ? master out slave in for spi0. o ct16b0_mat1 ? match output 1 for 16-bit timer 0. swclk/pio0_10/ sck0/ ct16b0_mat2 29 [3] i swclk ? serial wire clock. i/o pio0_10 ? general purpose digi tal input/output pin. i/o sck0 ? serial clock for spi0. o ct16b0_mat2 ? match output 2 for 16-bit timer 0. r/pio0_11/ ad0/ ct32b0_mat3 32 [5] - r ? reserved. configure for an alternate function in the ioconfig block. i/o pio0_11 ? general purpose digital input/output pin. i ad0 ? a/d converter, input 0. o ct32b0_mat3 ? match output 3 for 32-bit timer 0.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 155 of 543 nxp semiconductors um10398 chapter 9: lpc111x/lpc11cxx pin configuration (lpc1100, lpc1100c, pio1_0 to pio1_11 port 1 ? port 1 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 1 pins dep ends on the function selected through the ioconfig register block. r/pio1_0/ad1/ ct32b1_cap0 33 [5] - r ? reserved. configure for an alternate function in the ioconfig block. i/o pio1_0 ? general purpose digital input/output pin. i ad1 ? a/d converter, input 1. i ct32b1_cap0 ? capture input 0 for 32-bit timer 1. r/pio1_1/ad2/ ct32b1_mat0 34 [5] - r ? reserved. configure for an alternate function in the ioconfig block. i/o pio1_1 ? general purpose digital input/output pin. i ad2 ? a/d converter, input 2. o ct32b1_mat0 ? match output 0 for 32-bit timer 1. r/pio1_2/ad3/ ct32b1_mat1 35 [5] - r ? reserved. configure for an alternate function in the ioconfig block. i/o pio1_2 ? general purpose digital input/output pin. i ad3 ? a/d converter, input 3. o ct32b1_mat1 ? match output 1 for 32-bit timer 1. swdio/pio1_3/ ad4/ ct32b1_mat2 39 [5] i/o swdio ? serial wire debug input/output. i/o pio1_3 ? general purpose digital input/output pin. i ad4 ? a/d converter, input 4. o ct32b1_mat2 ? match output 2 for 32-bit timer 1. pio1_4/ad5/ ct32b1_mat3/ wakeup 40 [5] i/o pio1_4 ? general purpose digital input/outp ut pin with 10 ns glitch filter. i ad5 ? a/d converter, input 5. o ct32b1_mat3 ? match output 3 for 32-bit timer 1. i wakeup ? deep power-down mode wake-up pin wit h 20 ns glitch filter. this pin must be pulled high externally to enter deep power-down mode and pulled low to exit deep power-down mode. a low-going pulse as short as 50 ns wakes up the part. pio1_5/rts / ct32b0_cap0 45 [3] i/o pio1_5 ? general purpose digital input/output pin. o rts ? request to send output for uart. i ct32b0_cap0 ? capture input 0 for 32-bit timer 0. pio1_6/rxd/ ct32b0_mat0 46 [3] i/o pio1_6 ? general purpose digital input/output pin. i rxd ? receiver input for uart. o ct32b0_mat0 ? match output 0 for 32-bit timer 0. pio1_7/txd/ ct32b0_mat1 47 [3] i/o pio1_7 ? general purpose digital input/output pin. o txd ? transmitter output for uart. o ct32b0_mat1 ? match output 1 for 32-bit timer 0. pio1_8/ ct16b1_cap0 9 [3] i/o pio1_8 ? general purpose digital input/output pin. i ct16b1_cap0 ? capture input 0 for 16-bit timer 1. pio1_10/ad6/ ct16b1_mat1 30 [5] i/o pio1_10 ? general purpose digi tal input/output pin. i ad6 ? a/d converter, input 6. o ct16b1_mat1 ? match output 1 for 16-bit timer 1. pio1_11/ad7 42 [5] i/o pio1_11 ? general purpose digital input/output pin. i ad7 ? a/d converter, input 7. table 163. lpc11c24/c22 pin description table (lqfp48 package) symbol pin type description
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 156 of 543 nxp semiconductors um10398 chapter 9: lpc111x/lpc11cxx pin configuration (lpc1100, lpc1100c, pio2_0 to pio2_11 port 2 ? port 2 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 2 pins dep ends on the function selected through the ioconfig register block. pio2_0/dtr / ssel1 2 [3] i/o pio2_0 ? general purpose digital input/output pin. i/o dtr ? data terminal ready output for uart. i/o ssel1 ? slave select for spi1. pio2_1/dsr /sck1 13 [3] i/o pio2_1 ? general purpose digital input/output pin. i dsr ? data set ready input for uart. i/o sck1 ? serial clock for spi1. pio2_2/dcd / miso1 26 [3] i/o pio2_2 ? general purpose digital input/output pin. i dcd ? data carrier detect input for uart. i/o miso1 ? master in slave out for spi1. pio2_3/ri /mosi1 38 [3] i/o pio2_3 ? general purpose digital input/output pin. i ri ? ring indicator input for uart. i/o mosi1 ? master out slave in for spi1. pio2_6 1 [3] i/o pio2_6 ? general purpose digital input/output pin. pio2_7 11 [3] i/o pio2_7 ? general purpose digital input/output pin. pio2_8 12 [3] i/o pio2_8 ? general purpose digital input/output pin. pio2_10 25 [3] i/o pio2_10 ? general purpose digi tal input/output pin. pio2_11/sck0 31 [3] i/o pio2_11 ? general purpose digital input/output pin. i/o sck0 ? serial clock for spi0. pio3_0 to pio3_3 port 3 ? port 3 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 3 pins dep ends on the function selected through the ioconfig register block. pins pio3 _4 to pio3_11 are not available. pio3_0/dtr 36 [3] i/o pio3_0 ? general purpose digital input/output pin. o dtr ? data terminal ready output for uart. pio3_1/dsr 37 [3] i/o pio3_1 ? general purpose digital input/output pin. i dsr ? data set ready input for uart. pio3_2/dcd 43 [3] i/o pio3_2 ? general purpose digital input/output pin. i dcd ? data carrier detect input for uart. pio3_3/ri 48 [3] i/o pio3_3 ? general purpose digital input/output pin. i ri ? ring indicator input for uart. canl 18 i/o low-level can bus line. canh 19 i/o high-level can bus line. stb 22 i silent mode control input for can tran sceiver (low = normal mode, high = silent mode). vdd_can 17 - supply voltage for i/o level of can transceiver. v cc 20 - supply voltage for can transceiver. gnd 21 - ground for can transceiver. v dd 8;44 i supply voltage to the internal regulator, the external rail, and the adc. also used as the adc reference voltage. table 163. lpc11c24/c22 pin description table (lqfp48 package) symbol pin type description
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 157 of 543 nxp semiconductors um10398 chapter 9: lpc111x/lpc11cxx pin configuration (lpc1100, lpc1100c, [1] 5 v tolerant pad. reset functionality is not available in deep power-down mode. use the wakeup pin to reset the chip and wake up from deep power-down mode. an external pull-up resistor is required on this pin for the deep power-down mode. [2] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis. [3] i 2 c-bus pads compliant with the i 2 c-bus specification for i 2 c standard mode and i 2 c fast-mode plus. [4] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s, configurable hysteresis, and analog input. when configured as a adc input, digital section of t he pad is disabled and the pin is not 5 v tolerant. [5] 5 v tolerant digital i/o pad without pull-up/pull-down resistors. [6] when the system oscillator is not used, connect xtalin and xtalout as follows: xtalin can be left floating or can be grounde d (grounding is preferred to reduce susceptibilit y to noise). xtalout should be left floating. xtalin 6 [7] i input to the oscillator circuit and internal clock generator circuits. input voltage must not exceed 1.8 v. xtalout 7 [7] o output from the oscillator amplifier. v ss 5; 41 i ground. table 163. lpc11c24/c22 pin description table (lqfp48 package) symbol pin type description table 164. lpc11d14 pin description table (lqfp100 package) symbol pin start logic input type reset state [1] description microcontroller pins pio0_0 to pio0_11 i/o port 0 ? port 0 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 0 pins depends on the function selected through the ioconfig register block. reset /pio0_0 6 [1] yes i i; pu reset ? external reset input with 20 ns glitch filter. a low-going pulse as short as 50 ns on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. i/o - pio0_0 ? general purpose digital inpu t/output pin with 10 ns glitch filter. pio0_1/clkout/ ct32b0_mat2 7 [3] yes i/o i; pu pio0_1 ? general purpose digital input/output pin. a low level on this pin during reset starts the isp command handler. o- clkout ? clockout pin. o- ct32b0_mat2 ? match output 2 for 32-bit timer 0. pio0_2/ssel0/ ct16b0_cap0 13 [3] yes i/o i; pu pio0_2 ? general purpose digital input/output pin. i/o - ssel0 ? slave select for spi0. i- ct16b0_cap0 ? capture input 0 for 16-bit timer 0. pio0_3 17 [3] yes i/o i; pu pio0_3 ? general purpose digital input/output pin. pio0_4/scl 18 [4] yes i/o i; ia pio0_4 ? general purpose digital input/output pin (open-drain). i/o - scl ? i 2 c-bus, open-drain clock input/output. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 158 of 543 nxp semiconductors um10398 chapter 9: lpc111x/lpc11cxx pin configuration (lpc1100, lpc1100c, pio0_5/sda 19 [4] yes i/o i; ia pio0_5 ? general purpose digital input/output pin (open-drain). i/o - sda ? i 2 c-bus, open-drain data input/output. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_6/sck0 25 [3] yes i/o i; pu pio0_6 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for spi0. pio0_7/cts 26 [3] yes i/o i; pu pio0_7 ? general purpose digital input/output pin (high-current output driver). i- cts ? clear to send input for uart. pio0_8/miso0/ ct16b0_mat0 81 [3] yes i/o i; pu pio0_8 ? general purpose digital input/output pin. i/o - miso0 ? master in slave out for spi0. o- ct16b0_mat0 ? match output 0 for 16-bit timer 0. pio0_9/mosi0/ ct16b0_mat1 82 [3] yes i/o i; pu pio0_9 ? general purpose digital input/output pin. i/o - mosi0 ? master out slave in for spi0. o- ct16b0_mat1 ? match output 1 for 16-bit timer 0. swclk/pio0_10/ sck0/ ct16b0_mat2 83 [3] yes i i; pu swclk ? serial wire clock. i/o - pio0_10 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for spi0. o- ct16b0_mat2 ? match output 2 for 16-bit timer 0. r/pio0_11/ ad0/ct32b0_mat3 86 [5] yes i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio0_11 ? general purpose digital input/output pin. i- ad0 ? a/d converter, input 0. o- ct32b0_mat3 ? match output 3 for 32-bit timer 0. pio1_0 to pio1_11 i/o port 1 ? port 1 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 1 pins depends on the function selected through the ioconfig register block. r/pio1_0/ ad1/ct32b1_cap0 87 [5] yes i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_0 ? general purpose digital input/output pin. i- ad1 ? a/d converter, input 1. i- ct32b1_cap0 ? capture input 0 for 32-bit timer 1. r/pio1_1/ ad2/ct32b1_mat0 88 [5] no o i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_1 ? general purpose digital input/output pin. i- ad2 ? a/d converter, input 2. o- ct32b1_mat0 ? match output 0 for 32-bit timer 1. table 164. lpc11d14 pin description table (lqfp100 package) ?continued symbol pin start logic input type reset state [1] description
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 159 of 543 nxp semiconductors um10398 chapter 9: lpc111x/lpc11cxx pin configuration (lpc1100, lpc1100c, r/pio1_2/ ad3/ct32b1_mat1 89 [5] no i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_2 ? general purpose digital input/output pin. i- ad3 ? a/d converter, input 3. o- ct32b1_mat1 ? match output 1 for 32-bit timer 1. swdio/pio1_3/ ad4/ct32b1_mat2 93 [5] no i/o i; pu swdio ? serial wire debug input/output. i/o - pio1_3 ? general purpose digital input/output pin. i- ad4 ? a/d converter, input 4. o- ct32b1_mat2 ? match output 2 for 32-bit timer 1. pio1_4/ad5/ ct32b1_mat3/ wakeup 94 [5] no i/o i; pu pio1_4 ? general purpose digital inpu t/output pin with 10 ns glitch filter. i- ad5 ? a/d converter, input 5. o- ct32b1_mat3 ? match output 3 for 32-bit timer 1. i- wakeup ? deep power-down mode wake-up pin with 20 ns glitch filter. this pin must be pulled high externally to enter deep power-down mode and pulled low to exit deep power-down mode. a low-going pulse as short as 50 ns wakes up the part. pio1_5/rts / ct32b0_cap0 99 [3] no i/o i; pu pio1_5 ? general purpose digital input/output pin. o- rts ? request to send output for uart. i- ct32b0_cap0 ? capture input 0 for 32-bit timer 0. pio1_6/rxd/ ct32b0_mat0 100 [3] no i/o i; pu pio1_6 ? general purpose digital input/output pin. i- rxd ? receiver input for uart. o- ct32b0_mat0 ? match output 0 for 32-bit timer 0. pio1_7/txd/ ct32b0_mat1 1 [3] no i/o i; pu pio1_7 ? general purpose digital input/output pin. o- txd ? transmitter output for uart. o- ct32b0_mat1 ? match output 1 for 32-bit timer 0. pio1_8/ ct16b1_cap0 12 [3] no i/o i; pu pio1_8 ? general purpose digital input/output pin. i- ct16b1_cap0 ? capture input 0 for 16-bit timer 1. pio1_9/ ct16b1_mat0 20 [3] no i/o i; pu pio1_9 ? general purpose digital input/output pin. o- ct16b1_mat0 ? match output 0 for 16-bit timer 1. pio1_10/ad6/ ct16b1_mat1 84 [5] no i/o i; pu pio1_10 ? general purpose digital input/output pin. i- ad6 ? a/d converter, input 6. o- ct16b1_mat1 ? match output 1 for 16-bit timer 1. pio1_11/ad7 96 [5] no i/o i; pu pio1_11 ? general purpose digital input/output pin. i- ad7 ? a/d converter, input 7. pio2_0 to pio2_11 i/o port 2 ? port 2 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 2 pins depends on the function selected through the ioconfig register block. table 164. lpc11d14 pin description table (lqfp100 package) ?continued symbol pin start logic input type reset state [1] description
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 160 of 543 nxp semiconductors um10398 chapter 9: lpc111x/lpc11cxx pin configuration (lpc1100, lpc1100c, pio2_0/dtr /ssel1 5 [3] no i/o i; pu pio2_0 ? general purpose digital input/output pin. o- dtr ? data terminal ready output for uart. i/o - ssel1 ? slave select for spi1. pio2_1/dsr /sck1 16 [3] no i/o i; pu pio2_1 ? general purpose digital input/output pin. i- dsr ? data set ready input for uart. i/o - sck1 ? serial clock for spi1. pio2_2/dcd /miso1 80 [3] no i/o i; pu pio2_2 ? general purpose digital input/output pin. i- dcd ? data carrier detect input for uart. i/o - miso1 ? master in slave out for spi1. pio2_3/ri /mosi1 92 [3] no i/o i; pu pio2_3 ? general purpose digital input/output pin. i- ri ? ring indicator input for uart. i/o - mosi1 ? master out slave in for spi1. pio2_4 22 [3] no i/o i; pu pio2_4 ? general purpose digital input/output pin. pio2_5 23 [3] no i/o i; pu pio2_5 ? general purpose digital input/output pin. pio2_6 4 [3] no i/o i; pu pio2_6 ? general purpose digital input/output pin. pio2_7 14 [3] no i/o i; pu pio2_7 ? general purpose digital input/output pin. pio2_8 15 [3] no i/o i; pu pio2_8 ? general purpose digital input/output pin. pio2_9 27 [3] no i/o i; pu pio2_9 ? general purpose digital input/output pin. pio2_10 28 [3] no i/o i; pu pio2_10 ? general purpose digital input/output pin. pio2_11/sck0 85 [3] no i/o i; pu pio2_11 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for spi0. pio3_0 to pio3_5 i/o port 3 ? port 3 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 3 pins depends on the function selected through the ioconfig register block. pins pio3_6 to pio3_11 are not available. pio3_0/dtr 90 [3] no i/o i; pu pio3_0 ? general purpose digital input/output pin. o- dtr ? data terminal ready output for uart. pio3_1/dsr 91 [3] no i/o i; pu pio3_1 ? general purpose digital input/output pin. i- dsr ? data set ready input for uart. pio3_2/dcd 97 [3] no i/o i; pu pio3_2 ? general purpose digital input/output pin. i- dcd ? data carrier detect input for uart. pio3_3/ri 2 [3] no i/o i; pu pio3_3 ? general purpose digital input/output pin. i- ri ? ring indicator input for uart. pio3_4 21 [3] no i/o i; pu pio3_4 ? general purpose digital input/output pin. pio3_5 24 [3] no i/o i; pu pio3_5 ? general purpose digital input/output pin. v dd 11; 98 - i - 3.3 v supply voltage to the internal regulator, the external rail, and the adc. also used as the adc reference voltage. xtalin 9 [7] - i - input to the oscillator circuit and internal clock generator circuits. input voltage must not exceed 1.8 v. xtalout 10 [7] - o - output from the oscillator amplifier. v ss 8; 95 - i - ground. table 164. lpc11d14 pin description table (lqfp100 package) ?continued symbol pin start logic input type reset state [1] description
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 161 of 543 nxp semiconductors um10398 chapter 9: lpc111x/lpc11cxx pin configuration (lpc1100, lpc1100c, lcd display pins s0 46 - o v lcd [7] lcd segment output. s1 47 - o v lcd [7] lcd segment output. s2 48 - o v lcd [7] lcd segment output. s3 49 - o v lcd [7] lcd segment output. s4 50 - o v lcd [7] lcd segment output. s5 51 - o v lcd [7] lcd segment output. s6 52 - o v lcd [7] lcd segment output. s7 53 - o v lcd [7] lcd segment output. s8 54 - o v lcd [7] lcd segment output. s9 55 - o v lcd [7] lcd segment output. s10 56 - o v lcd [7] lcd segment output. s11 57 - o v lcd [7] lcd segment output. s12 58 - o v lcd [7] lcd segment output. s13 59 - o v lcd [7] lcd segment output. s14 60 - o v lcd [7] lcd segment output. s15 61 - o v lcd [7] lcd segment output. s16 62 - o v lcd [7] lcd segment output. s17 63 - o v lcd [7] lcd segment output. s18 64 - o v lcd [7] lcd segment output. s19 65 - o v lcd [7] lcd segment output. s20 66 - o v lcd [7] lcd segment output. s21 67 - o v lcd [7] lcd segment output. s22 68 - o v lcd [7] lcd segment output. s23 69 - o v lcd [7] lcd segment output. s24 70 - o v lcd [7] lcd segment output. s25 71 - o v lcd [7] lcd segment output. s26 72 - o v lcd [7] lcd segment output. s27 73 - o v lcd [7] lcd segment output. s28 74 - o v lcd [7] lcd segment output. s29 75 - o v lcd [7] lcd segment output. s30 76 - o v lcd [7] lcd segment output. s31 77 - o v lcd [7] lcd segment output. s32 78 - o v lcd [7] lcd segment output. s33 79 - o v lcd [7] lcd segment output. s34 29 - o v lcd [7] lcd segment output. s35 30 - o v lcd [7] lcd segment output. s36 31 - o v lcd [7] lcd segment output. s37 32 - o v lcd [7] lcd segment output. table 164. lpc11d14 pin description table (lqfp100 package) ?continued symbol pin start logic input type reset state [1] description
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 162 of 543 nxp semiconductors um10398 chapter 9: lpc111x/lpc11cxx pin configuration (lpc1100, lpc1100c, [1] pin state at reset for default function: i = input; o = ou tput; pu = internal pull-up enabled (pins pulled up to full v dd level (v dd = 3.3 v)); ia = inactive, no pull-up/down enabled. [2] reset functionality is not available in deep power-down mode. us e the wakeup pin to reset the chip and wake up from deep power-down mode. an external pull-up resistor is required on this pin for the deep power-down mode. [3] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis. [4] i 2 c-bus pads compliant with the i 2 c-bus specification for i 2 c standard mode and i 2 c fast-mode plus. [5] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s, configurable hysteresis, and analog input. when configured as a adc input, digital section of t he pad is disabled and the pin is not 5 v tolerant. [6] when the system oscillator is not used, connect xtalin and xtalout as follows: xtalin can be left floating or can be grounde d (grounding is preferred to reduce susceptibilit y to noise). xtalout should be left floating. [7] see the lpc11d4 data sheet . s38 33 - o v lcd [7] lcd segment output. s39 34 - o v lcd [7] lcd segment output. bp0 42 - o v lcd [7] lcd backplane output. bp1 44 - o v lcd [7] lcd backplane output. bp2 43 - o v lcd [7] lcd backplane output. bp3 45 - o v lcd [7] lcd backplane output. lcd_sda 35 - i/o [7] i 2 c-bus serial data input/output. lcd_scl 36 - i/o [7] i 2 c-bus serial clock input. sync 37 - i/o [7] cascade synchronization input/output. clk 38 - i/o [7] external clock input/output. v dd(lcd) 39 - - - 1.8 v to 5.5 v power supply: power supply voltage for the pcf8576d. v ss(lcd) 40 - - - lcd ground. v lcd 41 - - - lcd power supply; lcd voltage. n.c. 3 - - - not connected. table 164. lpc11d14 pin description table (lqfp100 package) ?continued symbol pin start logic input type reset state [1] description
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 163 of 543 10.1 how to read this chapter this chapter describes the small pin packages for the lpc111x parts in tssop, dip, and so packages. 10.2 pin configuration (lpc1110/11/12) um10398 chapter 10: lpc111x pin confi guration (lpc1100l series, tssop, dip, so packages) rev. 12.1 ? 7 august 2013 user manual table 165. lpc11xx pin configurations for 20-pin and 28-pin packages part so20 tssop20 tssop28 dip28 lpc1110fd20 pin configuration figure 22 --- pin description table 166 --- LPC1111fdh20/002 pin configuration - figure 23 -- pin description - ta b l e 1 6 6 -- lpc1112fd20/102 pin configuration figure 22 --- pin description table 166 --- lpc1112fdh20/102 pin configuration - figure 24 -- pin description - ta b l e 1 6 7 -- lpc1112fdh28/102 pin configuration - - figure 25 - pin description - - table 168 - lpc1114fdh28/102 pin configuration - - figure 25 - pin description - - table 168 - lpc1114fn28/102 pin configuration - - - figure 26 pin description - - - table 168 fig 22. pin configuration so20 package lpc1110fd20 lpc1112fd20/ 102 pio0_8/miso0/ct16b0_mat0 pio0_4/scl pio0_9/mosi0/ct16b0_mat1 pio0_2/ssel0/ct16b0_cap0 swclk/pio0_10/sck0/ct16b0_mat2 pio0_1/clkout/ct32b0_mat2 r/pio0_11/ad0/ct32b0_mat3 reset/pio0_0 pio0_5/sda v ss pio0_6/sck0 v dd r/pio1_0/ad1/ct32b1_cap0 xtalin r/pio1_1/ad2/ct32b1_mat0 xtalout r/pio1_2/ad3/ct32b1_mat1 pio1_7/txd/ct32b0_mat1 swdio/pio1_3/ad4/ct32b1_mat2 pio1_6/rxd/ct32b0_mat0 002aag595 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 164 of 543 nxp semiconductors um10398 chapter 10: lpc111x pin configuration (lpc1100l series, tssop, dip, fig 23. pin configuration tssop20 package with i 2 c-bus pins LPC1111fdh20/002 pio0_8/miso0/ct16b0_mat0 pio0_4/scl pio0_9/mosi0/ct16b0_mat1 pio0_2/ssel0/ct16b0_cap0 swclk/pio0_10/sck0/ct16b0_mat2 pio0_1/clkout/ct32b0_mat2 r/pio0_11/ad0/ct32b0_mat3 reset/pio0_0 pio0_5/sda v ss pio0_6/sck0 v dd r/pio1_0/ad1/ct32b1_cap0 xtalin r/pio1_1/ad2/ct32b1_mat0 xtalout r/pio1_2/ad3/ct32b1_mat1 pio1_7/txd/ct32b0_mat1 swdio/pio1_3/ad4/ct32b1_mat2 pio1_6/rxd/ct32b0_mat0 002aag596 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 table 166. lpc1110/11/12 pin description table (so20 and tssop20 package with i 2 c-bus pins) symbol pin so20/ tssop20 start logic input type reset state [1] description pio0_0 to pio0_11 i/o port 0 ? port 0 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 0 pins depends on the function selected throug h the ioconfig register block. reset /pio0_0 17 [2] yes i i; pu reset ? external reset input with 20 ns glitch filter. a low-going pulse as short as 50 ns on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. i/o - pio0_0 ? general purpose digital input/o utput pin with 10 ns glitch filter. pio0_1/clkout/ ct32b0_mat2 18 [3] yes i/o i; pu pio0_1 ? general purpose digital inpu t/output pin. a low level on this pin during reset starts the isp command handler. o- clkout ? clockout pin. o- ct32b0_mat2 ? match output 2 for 32-bit timer 0. pio0_2/ssel0/ ct16b0_cap0 19 [3] yes i/o i; pu pio0_2 ? general purpose digital input/output pin. i/o - ssel0 ? slave select for spi0. i- ct16b0_cap0 ? capture input 0 for 16-bit timer 0. pio0_4/scl 20 [4] yes i/o i; ia pio0_4 ? general purpose digital inpu t/output pin (open-drain). i/o - scl ? i 2 c-bus, open-drain clock input/output. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_5/sda 5 [4] yes i/o i; ia pio0_5 ? general purpose digital inpu t/output pin (open-drain). i/o - sda ? i 2 c-bus, open-drain data input/output. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_6/sck0 6 [3] yes i/o i; pu pio0_6 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for spi0. pio0_8/miso0/ ct16b0_mat0 1 [3] yes i/o i; pu pio0_8 ? general purpose digital input/output pin. i/o - miso0 ? master in slave out for spi0. o- ct16b0_mat0 ? match output 0 for 16-bit timer 0.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 165 of 543 nxp semiconductors um10398 chapter 10: lpc111x pin configuration (lpc1100l series, tssop, dip, pio0_9/mosi0/ ct16b0_mat1 2 [3] yes i/o i; pu pio0_9 ? general purpose digital input/output pin. i/o - mosi0 ? master out slave in for spi0. o- ct16b0_mat1 ? match output 1 for 16-bit timer 0. swclk/pio0_10/ sck0/ ct16b0_mat2 3 [3] yes i i; pu swclk ? serial wire clock. i/o - pio0_10 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for spi0. o- ct16b0_mat2 ? match output 2 for 16-bit timer 0. r/pio0_11/ ad0/ct32b0_mat3 4 [5] yes i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio0_11 ? general purpose digital input/output pin. i- ad0 ? a/d converter, input 0. o- ct32b0_mat3 ? match output 3 for 32-bit timer 0. pio1_0 to pio1_7 i/o port 1 ? port 1 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 1 pins depends on the function selected throug h the ioconfig register block. r/pio1_0/ ad1/ct32b1_cap0 7 [5] yes i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_0 ? general purpose digital input/output pin. i- ad1 ? a/d converter, input 1. i- ct32b1_cap0 ? capture input 0 for 32-bit timer 1. r/pio1_1/ ad2/ct32b1_mat0 8 [5] no o i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_1 ? general purpose digital input/output pin. i- ad2 ? a/d converter, input 2. o- ct32b1_mat0 ? match output 0 for 32-bit timer 1. r/pio1_2/ ad3/ct32b1_mat1 9 [5] no i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_2 ? general purpose digital input/output pin. i- ad3 ? a/d converter, input 3. o- ct32b1_mat1 ? match output 1 for 32-bit timer 1. swdio/pio1_3/ ad4/ct32b1_mat2 10 [5] no i/o i; pu swdio ? serial wire debug input/output. i/o - pio1_3 ? general purpose digital input/output pin. i- ad4 ? a/d converter, input 4. o- ct32b1_mat2 ? match output 2 for 32-bit timer 1. pio1_6/rxd/ ct32b0_mat0 11 [3] no i/o i; pu pio1_6 ? general purpose digital input/output pin. i- rxd ? receiver input for uart. o- ct32b0_mat0 ? match output 0 for 32-bit timer 0. pio1_7/txd/ ct32b0_mat1 12 [3] no i/o i; pu pio1_7 ? general purpose digital input/output pin. o- txd ? transmitter output for uart. o- ct32b0_mat1 ? match output 1 for 32-bit timer 0. table 166. lpc1110/11/12 pin description table (so20 and tssop20 package with i 2 c-bus pins) ?continued symbol pin so20/ tssop20 start logic input type reset state [1] description
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 166 of 543 nxp semiconductors um10398 chapter 10: lpc111x pin configuration (lpc1100l series, tssop, dip, [1] pin state at reset for default function: i = input; o = ou tput; pu = internal pull-up enabled (pins pulled up to full v dd level); ia = inactive, no pull-up/down enabled. [2] reset functionality is not available in deep power-down mode. us e the wakeup pin to reset the chip and wake up from deep power-down mode. an external pull-up resistor is required on this pin for the deep power-down mode. [3] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis. [4] i 2 c-bus pads compliant with the i 2 c-bus specification for i 2 c standard mode and i 2 c fast-mode plus. [5] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s, configurable hysteresis, and analog input. when configured as a adc input, digital section of t he pad is disabled and the pin is not 5 v tolerant. [6] when the system oscillator is not used, connect xtalin and xtalout as follows: xtalin can be left floating or can be grounde d (grounding is preferred to reduce susceptibilit y to noise). xtalout should be left floating. 10.3 pin configuration (lpc1112) v dd 15 - - 3.3 v supply voltage to the internal regulator, the external rail, and the adc. also used as the adc reference voltage. xtalin 14 [6] - i - input to the oscillator circuit and internal clock generator circuits. input voltage must not exceed 1.8 v. xtalout 13 [6] - o - output from the oscillator amplifier. v ss 16 - - ground. table 166. lpc1110/11/12 pin description table (so20 and tssop20 package with i 2 c-bus pins) ?continued symbol pin so20/ tssop20 start logic input type reset state [1] description fig 24. pin configuration tssop20 package with v dda and v ssa pins lpc1112fdh20/102 pio0_8/miso0/ct16b0_mat0 pio0_3 pio0_9/mosi0/ct16b0_mat1 pio0_2/ssel0/ct16b0_cap0 swclk/pio0_10/sck0/ct16b0_mat2 pio0_1/clkout/ct32b0_mat2 r/pio0_11/ad0/ct32b0_mat3 reset/pio0_0 v dda v ss v ssa v dd r/pio1_0/ad1/ct32b1_cap0 xtalin r/pio1_1/ad2/ct32b1_mat0 xtalout r/pio1_2/ad3/ct32b1_mat1 pio1_7/txd/ct32b0_mat1 swdio/pio1_3/ad4/ct32b1_mat2 pio1_6/rxd/ct32b0_mat0 002aag597 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 167 of 543 nxp semiconductors um10398 chapter 10: lpc111x pin configuration (lpc1100l series, tssop, dip, table 167. lpc1112 pin description table (tssop20 with v dda and v ssa pins) symbol pin tssop20 start logic input type reset state [1] description pio0_0 to pio0_11 i/o port 0 ? port 0 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 0 pins depends on the function selected through the ioconfig register block. reset /pio0_0 17 [2] yes i i; pu reset ? external reset input with 20 ns glitch filter. a low-going pulse as short as 50 ns on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor ex ecution to begin at address 0. i/o - pio0_0 ? general purpose digital in put/output pin with 10 ns glitch filter. pio0_1/clkout/ ct32b0_mat2 18 [3] yes i/o i; pu pio0_1 ? general purpose digital input/output pin. a low level on this pin during reset starts the isp command handler. o- clkout ? clockout pin. o- ct32b0_mat2 ? match output 2 for 32-bit timer 0. pio0_2/ssel0/ ct16b0_cap0 19 [3] yes i/o i; pu pio0_2 ? general purpose digi tal input/output pin. i/o - ssel0 ? slave select for spi0. i- ct16b0_cap0 ? capture input 0 for 16-bit timer 0. pio0_3 20 [3] yes i/o i; pu pio0_3 ? general purpose digita l input/output pin. pio0_8/miso0/ ct16b0_mat0 1 [3] yes i/o i; pu pio0_8 ? general purpose digi tal input/output pin. i/o - miso0 ? master in slave out for spi0. o- ct16b0_mat0 ? match output 0 for 16-bit timer 0. pio0_9/mosi0/ ct16b0_mat1 2 [3] yes i/o i; pu pio0_9 ? general purpose digi tal input/output pin. i/o - mosi0 ? master out slave in for spi0. o- ct16b0_mat1 ? match output 1 for 16-bit timer 0. swclk/pio0_10/ sck0/ ct16b0_mat2 3 [3] yes i i; pu swclk ? serial wire clock. i/o - pio0_10 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for spi0. o- ct16b0_mat2 ? match output 2 for 16-bit timer 0. r/pio0_11/ ad0/ct32b0_mat3 4 [4] yes i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio0_11 ? general purpose digital input/output pin. i- ad0 ? a/d converter, input 0. o- ct32b0_mat3 ? match output 3 for 32-bit timer 0. pio1_0 to pio1_7 i/o port 1 ? port 1 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 1 pins depends on the function selected through the ioconfig register block.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 168 of 543 nxp semiconductors um10398 chapter 10: lpc111x pin configuration (lpc1100l series, tssop, dip, [1] pin state at reset for default function: i = input; o = ou tput; pu = internal pull-up enabled (pins pulled up to full v dd level); ia = inactive, no pull-up/down enabled. [2] reset functionality is not available in deep power-down mode. us e the wakeup pin to reset the chip and wake up from deep power-down mode. an external pull-up resistor is required on this pin for the deep power-down mode. [3] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis. r/pio1_0/ ad1/ct32b1_cap0 7 [4] yes i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_0 ? general purpose digi tal input/output pin. i- ad1 ? a/d converter, input 1. i- ct32b1_cap0 ? capture input 0 for 32-bit timer 1. r/pio1_1/ ad2/ct32b1_mat0 8 [4] no o i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_1 ? general purpose digi tal input/output pin. i- ad2 ? a/d converter, input 2. o- ct32b1_mat0 ? match output 0 for 32-bit timer 1. r/pio1_2/ ad3/ct32b1_mat1 9 [4] no i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_2 ? general purpose digi tal input/output pin. i- ad3 ? a/d converter, input 3. o- ct32b1_mat1 ? match output 1 for 32-bit timer 1. swdio/pio1_3/ ad4/ct32b1_mat2 10 [4] no i/o i; pu swdio ? serial wire debug input/output. i/o - pio1_3 ? general purpose digi tal input/output pin. i- ad4 ? a/d converter, input 4. o- ct32b1_mat2 ? match output 2 for 32-bit timer 1. pio1_6/rxd/ ct32b0_mat0 11 [3] no i/o i; pu pio1_6 ? general purpose digi tal input/output pin. i- rxd ? receiver input for uart. o- ct32b0_mat0 ? match output 0 for 32-bit timer 0. pio1_7/txd/ ct32b0_mat1 12 [3] no i/o i; pu pio1_7 ? general purpose digi tal input/output pin. o- txd ? transmitter output for uart. o- ct32b0_mat1 ? match output 1 for 32-bit timer 0. v dd 15 - i - 3.3 v supply voltage to the internal regulator and the external rail. v dda 5 - i - 3.3 v supply voltage to the adc. also used as the adc reference voltage. xtalin 14 [5] - i - input to the oscillator circuit and internal clock generator circuits. input voltage must not exceed 1.8 v. xtalout 13 [5] - o - output from the oscillator amplifier. v ss 16 - i - ground. v ssa 6 - i - analog ground. table 167. lpc1112 pin description table (tssop20 with v dda and v ssa pins) ?continued symbol pin tssop20 start logic input type reset state [1] description
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 169 of 543 nxp semiconductors um10398 chapter 10: lpc111x pin configuration (lpc1100l series, tssop, dip, [4] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s, configurable hysteresis, and analog input. when configured as a adc input, digital section of t he pad is disabled and the pin is not 5 v tolerant. [5] when the system oscillator is not used, connect xtalin and xtalout as follows: xtalin can be left floating or can be grounde d (grounding is preferred to reduce susceptibilit y to noise). xtalout should be left floating. 10.4 pin configuration (lpc1112/14) fig 25. pin configuration tssop28 package lpc1112fdh28/102 lpc1114fdh28/102 pio0_8/miso0/ct16b0_mat0 pio0_7/cts pio0_9/mosi0/ct16b0_mat1 pio0_4/scl swclk/pio0_10/sck0/ct16b0_mat2 pio0_3 r/pio0_11/ad0/ct32b0_mat3 pio0_2/ssel0/ct16b0_cap0 pio0_5/sda pio0_1/clkout/ct32b0_mat2 pio0_6/sck0 reset/pio0_0 v dda v ss v ssa v dd r/pio1_0/ad1/ct32b1_cap0 xtalin r/pio1_1/ad2/ct32b1_mat0 xtalout r/pio1_2/ad3/ct32b1_mat1 pio1_9/ct16b1_mat0 swdio/pio1_3/ad4/ct32b1_mat2 pio1_8/ct16b1_cap0 pio1_4/ad5/ct32b1_mat3/wakeup pio1_7/txd/ct32b0_mat1 pio1_5/rts/ct32b0_cap0 pio1_6/rxd/ct32b0_mat0 002aag598 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 18 17 20 19 22 21 24 23 26 25 28 27 fig 26. pin configuration dip28 package lpc1114fn28/ 102 pio0_8/miso0/ct16b0_mat0 pio0_7/cts pio0_9/mosi0/ct16b0_mat1 pio0_4/scl swclk/pio0_10/sck0/ct16b0_mat2 pio0_3 r/pio0_11/ad0/ct32b0_mat3 pio0_2/ssel0/ct16b0_cap0 pio0_5/sda pio0_1/clkout/ct32b0_mat2 pio0_6/sck0 reset/pio0_0 v dda v ss v ssa v dd r/pio1_0/ad1/ct32b1_cap0 xtalin r/pio1_1/ad2/ct32b1_mat0 xtalout r/pio1_2/ad3/ct32b1_mat1 pio1_9/ct16b1_mat0 swdio/pio1_3/ad4/ct32b1_mat2 pio1_8/ct16b1_cap0 pio1_4/ad5/ct32b1_mat3/wakeup pio1_7/txd/ct32b0_mat1 pio1_5/rts/ct32b0_cap0 pio1_6/rxd/ct32b0_mat0 002aag599 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 18 17 20 19 22 21 24 23 26 25 28 27
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 170 of 543 nxp semiconductors um10398 chapter 10: lpc111x pin configuration (lpc1100l series, tssop, dip, table 168. lpc1112/14 pin descriptio n table (tssop28 and dip28 packages) symbol pin tssop28/ dip28 start logic input type reset state [1] description pio0_0 to pio0_11 i/o port 0 ? port 0 is a 12-bit i/o port with individual direction and function controls for each bit. th e operation of port 0 pins depends on the function selected through the ioconfig register block. reset /pio0_0 23 [2] yes i i; pu reset ? external reset input with 20 ns glitch filter. a low-going pulse as short as 50 ns on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. i/o - pio0_0 ? general purpose digital input/output pin with 10 ns glitch filter. pio0_1/clkout/ ct32b0_mat2 24 [3] yes i/o i; pu pio0_1 ? general purpose digital inpu t/output pin. a low level on this pin during reset starts the isp command handler. o- clkout ? clockout pin. o- ct32b0_mat2 ? match output 2 for 32-bit timer 0. pio0_2/ssel0/ ct16b0_cap0 25 [3] yes i/o i; pu pio0_2 ? general purpose digital input/output pin. i/o - ssel0 ? slave select for spi0. i- ct16b0_cap0 ? capture input 0 for 16-bit timer 0. pio0_3 26 [3] yes i/o i; pu pio0_3 ? general purpose digital input/output pin. pio0_4/scl 27 [4] yes i/o i; ia pio0_4 ? general purpose digital input/output pin (open-drain). i/o - scl ? i 2 c-bus, open-drain clock input/output. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_5/sda 5 [4] yes i/o i; ia pio0_5 ? general purpose digital inpu t/output pin (open-drain). i/o - sda ? i 2 c-bus, open-drain data input/output. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_6/sck0 6 [3] yes i/o i; pu pio0_6 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for spi0. pio0_7/cts 28 [3] yes i/o i; pu pio0_7 ? general purpose digital inpu t/output pin (high-current output driver). i- cts ? clear to send input for uart. pio0_8/miso0/ ct16b0_mat0 1 [3] yes i/o i; pu pio0_8 ? general purpose digital input/output pin. i/o - miso0 ? master in slave out for spi0. o- ct16b0_mat0 ? match output 0 for 16-bit timer 0. pio0_9/mosi0/ ct16b0_mat1 2 [3] yes i/o i; pu pio0_9 ? general purpose digital input/output pin. i/o - mosi0 ? master out slave in for spi0. o- ct16b0_mat1 ? match output 1 for 16-bit timer 0. swclk/pio0_10/ sck0/ ct16b0_mat2 3 [3] yes i i; pu swclk ? serial wire clock. i/o - pio0_10 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for spi0. o- ct16b0_mat2 ? match output 2 for 16-bit timer 0.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 171 of 543 nxp semiconductors um10398 chapter 10: lpc111x pin configuration (lpc1100l series, tssop, dip, r/pio0_11/ ad0/ct32b0_mat3 4 [5] yes i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio0_11 ? general purpose digital input/output pin. i- ad0 ? a/d converter, input 0. o- ct32b0_mat3 ? match output 3 for 32-bit timer 0. pio1_0 to pio1_9 i/o port 1 ? port 1 is a 12-bit i/o port with individual direction and function controls for each bit. th e operation of port 1 pins depends on the function selected through the ioconfig register block. r/pio1_0/ ad1/ct32b1_cap0 9 [5] yes i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_0 ? general purpose digital input/output pin. i- ad1 ? a/d converter, input 1. i- ct32b1_cap0 ? capture input 0 for 32-bit timer 1. r/pio1_1/ ad2/ct32b1_mat0 10 [5] no o i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_1 ? general purpose digital input/output pin. i- ad2 ? a/d converter, input 2. o- ct32b1_mat0 ? match output 0 for 32-bit timer 1. r/pio1_2/ ad3/ct32b1_mat1 11 [5] no i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_2 ? general purpose digital input/output pin. i- ad3 ? a/d converter, input 3. o- ct32b1_mat1 ? match output 1 for 32-bit timer 1. swdio/pio1_3/ ad4/ct32b1_mat2 12 [5] no i/o i; pu swdio ? serial wire debug input/output. i/o - pio1_3 ? general purpose digital input/output pin. i- ad4 ? a/d converter, input 4. o- ct32b1_mat2 ? match output 2 for 32-bit timer 1. pio1_4/ad5/ ct32b1_mat3/ wakeup 13 [5] no i/o i; pu pio1_4 ? general purpose digital input/output pin with 10 ns glitch filter. i- ad5 ? a/d converter, input 5. o- ct32b1_mat3 ? match output 3 for 32-bit timer 1. i- wakeup ? deep power-down mode wake-up pin with 20 ns glitch filter. this pin must be pul led high externally to enter deep power-down mode and pulled low to exit deep power-down mode. a low-going pulse as short as 50 ns wakes up the part. pio1_5/rts / ct32b0_cap0 14 [3] no i/o i; pu pio1_5 ? general purpose digital input/output pin. o- rts ? request to send output for uart. i- ct32b0_cap0 ? capture input 0 for 32-bit timer 0. table 168. lpc1112/14 pin descriptio n table (tssop28 and dip28 packages) ?continued symbol pin tssop28/ dip28 start logic input type reset state [1] description
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 172 of 543 nxp semiconductors um10398 chapter 10: lpc111x pin configuration (lpc1100l series, tssop, dip, [1] pin state at reset for default function: i = input; o = ou tput; pu = internal pull-up enabled (pins pulled up to full v dd level); ia = inactive, no pull-up/down enabled. [2] reset functionality is not available in deep power-down mode. us e the wakeup pin to reset the chip and wake up from deep power-down mode. an external pull-up resistor is required on this pin for the deep power-down mode. [3] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis. [4] i 2 c-bus pads compliant with the i 2 c-bus specification for i 2 c standard mode and i 2 c fast-mode plus. [5] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s, configurable hysteresis, and analog input. when configured as a adc input, digital section of t he pad is disabled and the pin is not 5 v tolerant. [6] when the system oscillator is not used, connect xtalin and xtalout as follows: xtalin can be left floating or can be grounde d (grounding is preferred to reduce susceptibilit y to noise). xtalout should be left floating. pio1_6/rxd/ ct32b0_mat0 15 [3] no i/o i; pu pio1_6 ? general purpose digital input/output pin. i- rxd ? receiver input for uart. o- ct32b0_mat0 ? match output 0 for 32-bit timer 0. pio1_7/txd/ ct32b0_mat1 16 [3] no i/o i; pu pio1_7 ? general purpose digital input/output pin. o- txd ? transmitter output for uart. o- ct32b0_mat1 ? match output 1 for 32-bit timer 0. pio1_8/ ct16b1_cap0 17 [3] no i/o i; pu pio1_8 ? general purpose digital input/output pin. i- ct16b1_cap0 ? capture input 0 for 16-bit timer 1. pio1_9/ ct16b1_mat0 18 [3] no i/o i; pu pio1_9 ? general purpose digital input/output pin. o- ct16b1_mat0 ? match output 0 for 16-bit timer 1. v dd 21 - - 3.3 v supply voltage to the internal regulator and the external rail. v dda 7 - - - 3.3 v supply voltage to the adc. also used as the adc reference voltage. xtalin 20 [6] - i - input to the oscillator circuit and internal clock generator circuits. input voltage must not exceed 1.8 v. xtalout 19 [6] - o - output from the oscillator amplifier. v ss 22 - - ground. v ssa 8 - - - analog ground. table 168. lpc1112/14 pin descriptio n table (tssop28 and dip28 packages) ?continued symbol pin tssop28/ dip28 start logic input type reset state [1] description
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 173 of 543 11.1 how to read this chapter remark: this chapter applies to parts in the lpc1100xl series for lqfp, hvqfn, and tfbga48 packages. the lpc111x are available in three packages: lqfp48 (lpc1113, lpc1114, lpc1115), hvqfn33 (LPC1111, lpc1112, lpc1113, lpc1114), and tfbga48 (lpc1115). um10398 chapter 11: lpc111x pin configur ation (lpc1100xl series, hvqfn/lqfp/tfbga48 packages) rev. 12.1 ? 7 august 2013 user manual table 169. lpc1100xl pin configurations part lqfp48 hvqfn33 tfbga48 LPC1111 pin configuration - figure 29 - pin description - table 171 - lpc1112 pin configuration - figure 29 - pin description - table 171 - lpc1113 pin configuration figure 27 figure 29 - pin description table 170 table 171 - lpc1114 pin configuration figure 27 figure 29 - pin description table 170 table 171 - lpc1115 pin configuration figure 27 - figure 28 pin description table 170 - table 170
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 174 of 543 nxp semiconductors um10398 chapter 11: lpc111x pin configuration (lpc1100xl series, 11.2 lpc111x pin configuration fig 27. pin configuration lqfp48 package lpc1113fbd48/303 lpc1114fbd48/303 lpc1114fbd48/323 lpc1114fbd48/333 lpc1115fbd48/303 pio2_6/ct32b0_mat1 pio3_0/dtr/ct16b0_mat0/txd pio2_0/dtr/ssel1 r/pio1_2/ad3/ct32b1_mat1 reset/pio0_0 r/pio1_1/ad2/ct32b1_mat0 pio0_1/clkout/ct32b0_mat2 r/pio1_0/ad1/ct32b1_cap0 v ss r/pio0_11/ad0/ct32b0_mat3 xtalin pio2_11/sck0/ct32b0_cap1 xtalout pio1_10/ad6/ct16b1_mat1/miso1 v dd swclk/pio0_10/sck0/ct16b0_mat2 pio1_8/ct16b1_cap0 pio0_9/mosi0/ct16b0_mat1 pio0_2/ssel0/ct16b0_cap0 pio0_8/miso0/ct16b0_mat0 pio2_7/ct32b0_mat2/rxd pio2_2/dcd/miso1 pio2_8/ct32b0_mat3/txd pio2_10 pio2_1/dsr/sck1 pio3_3/ri/ct16b0_cap0 pio0_3 pio1_7/txd/ct32b0_mat1 pio0_4/scl pio1_6/rxd/ct32b0_mat0 pio0_5/sda pio1_5/rts/ct32b0_cap0 pio1_9/ct16b1_mat0/mosi1 v dd pio3_4/ct16b0_cap1/rxd pio3_2/dcd/ct16b0_mat2/sck1 pio2_4/ct16b1_mat1/ssel1 pio1_11/ad7/ct32b1_cap1 pio2_5/ct32b0_mat0 v ss pio3_5/ct16b1_cap1/txd pio1_4/ad5/ct32b1_mat3/wakeup pio0_6/sck0 swdio/pio1_3/ad4/ct32b1_mat2 pio0_7/cts pio2_9/ct32b0_cap0 pio2_3/ri/mosi1 pio3_1/dsr/ct16b0_mat1/rxd 002aag781 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 37 24
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 175 of 543 nxp semiconductors um10398 chapter 11: lpc111x pin configuration (lpc1100xl series, fig 28. lpc1100xl series pin configuration tfbga48 package aaa-008364 lpc1115fet48/303 transparent top view h g f d b e c a 2468 1357 ball a1 index area
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 176 of 543 nxp semiconductors um10398 chapter 11: lpc111x pin configuration (lpc1100xl series, 11.3 lpc1100xl pin description fig 29. pin configuration hvqfn33 package 002aag782 transparent top view pio0_8/miso0/ct16b0_mat0 pio1_8/ct16b1_cap0 pio0_2/ssel0/ct16b0_cap0 pio0_9/mosi0/ct16b0_mat1 v dd swclk/pio0_10/sck0/ct16b0_mat2 xtalout pio1_10/ad6/ct16b1_mat1/miso1 xtalin r/pio0_11/ad0/ct32b0_mat3 pio0_1/clkout/ct32b0_mat2 r/pio1_0/ad1/ct32b1_cap0 reset/pio0_0 r/pio1_1/ad2/ct32b1_mat0 pio2_0/dtr/ssel1 r/pio1_2/ad3/ct32b1_mat1 pio0_3 pio0_4/scl pio0_5/sda pio1_9/ct16b1_mat0/mosi1 pio3_4/ct16b0_cap1/rxd pio3_5/ct16b1_cap1/txd pio0_6/sck0 pio0_7/cts pio1_7/txd/ct32b0_mat1 pio1_6/rxd/ct32b0_mat0 pio1_5/rts/ct32b0_cap0 v dd pio3_2/ct16b0_mat2/sck1 pio1_11/ad7/ct32b1_cap1 pio1_4/ad5/ct32b1_mat3/wakeup swdio/pio1_3/ad4/ct32b1_mat2 8 17 7 18 6 19 5 20 4 21 3 22 2 23 1 24 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 terminal 1 index area 33 v ss table 170. lpc1100xl series: lpc1113/14/15 pin description table (lqfp48 and tfbga48 package) symbol lqfp48 tfbga48 start logic input type reset state [1] description pio0_0 to pio0_11 i/o port 0 ? port 0 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 0 pins depends on the function selected through the ioconfig register block. reset /pio0_0 3 [2] c1 [2] yes i i; pu reset ? external reset input with 20 ns glitch filter. a low-going pulse as short as 50 ns on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. i/o - pio0_0 ? general purpose digital input/output pin with 10 ns glitch filter.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 177 of 543 nxp semiconductors um10398 chapter 11: lpc111x pin configuration (lpc1100xl series, pio0_1/clkout/ ct32b0_mat2 4 [3] c2 [3] yes i/o i; pu pio0_1 ? general purpose digita l input/output pin. a low level on this pin during reset starts the isp command handler. o- clkout ? clockout pin. o- ct32b0_mat2 ? match output 2 for 32-bit timer 0. pio0_2/ssel0/ ct16b0_cap0 10 [3] f1 [3] yes i/o i; pu pio0_2 ? general purpose digi tal input/output pin. i/o - ssel0 ? slave select for spi0. i- ct16b0_cap0 ? capture input 0 for 16-bit timer 0. pio0_3 14 [3] h2 [3] yes i/o i; pu pio0_3 ? general purpose digita l input/output pin. pio0_4/scl 15 [4] g3 [4] yes i/o i; ia pio0_4 ? general purpose digi tal input/output pin (open-drain). i/o - scl ? i 2 c-bus, open-drain clock input/output. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_5/sda 16 [4] h3 [4] yes i/o i; ia pio0_5 ? general purpose digi tal input/output pin (open-drain). i/o - sda ? i 2 c-bus, open-drain data input/output. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_6/sck0 22 [3] h6 [3] yes i/o i; pu pio0_6 ? general purpose digi tal input/output pin. i/o - sck0 ? serial clock for spi0. pio0_7/cts 23 [3] g7 [3] yes i/o i; pu pio0_7 ? general purpose digi tal input/output pin (high-current output driver). i- cts ? clear to send input for uart. pio0_8/miso0/ ct16b0_mat0 27 [3] f8 [3] yes i/o i; pu pio0_8 ? general purpose digi tal input/output pin. i/o - miso0 ? master in slave out for spi0. o- ct16b0_mat0 ? match output 0 for 16-bit timer 0. pio0_9/mosi0/ ct16b0_mat1 28 [3] f7 [3] yes i/o i; pu pio0_9 ? general purpose digi tal input/output pin. i/o - mosi0 ? master out slave in for spi0. o- ct16b0_mat1 ? match output 1 for 16-bit timer 0. swclk/pio0_10/ sck0/ ct16b0_mat2 29 [3] e7 [3] yes i i; pu swclk ? serial wire clock. i/o - pio0_10 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for spi0. o- ct16b0_mat2 ? match output 2 for 16-bit timer 0. r/pio0_11/ ad0/ct32b0_mat3 32 [5] d8 [5] yes i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio0_11 ? general purpose digital input/output pin. i- ad0 ? a/d converter, input 0. o- ct32b0_mat3 ? match output 3 for 32-bit timer 0. table 170. lpc1100xl series: lpc1113/14/15 pin description table (lqfp48 and tfbga48 package) ?continued symbol lqfp48 tfbga48 start logic input type reset state [1] description
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 178 of 543 nxp semiconductors um10398 chapter 11: lpc111x pin configuration (lpc1100xl series, pio1_0 to pio1_11 i/o port 1 ? port 1 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 1 pins depends on the function selected through the ioconfig register block. r/pio1_0/ ad1/ct32b1_cap0 33 [5] c7 [5] yes i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_0 ? general purpose digi tal input/output pin. i- ad1 ? a/d converter, input 1. i- ct32b1_cap0 ? capture input 0 for 32-bit timer 1. r/pio1_1/ ad2/ct32b1_mat0 34 [5] c8 [5] no o i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_1 ? general purpose digi tal input/output pin. i- ad2 ? a/d converter, input 2. o- ct32b1_mat0 ? match output 0 for 32-bit timer 1. r/pio1_2/ ad3/ct32b1_mat1 35 [5] b7 [5] no i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_2 ? general purpose digi tal input/output pin. i- ad3 ? a/d converter, input 3. o- ct32b1_mat1 ? match output 1 for 32-bit timer 1. swdio/pio1_3/ ad4/ct32b1_mat2 39 [5] b6 [5] no i/o i; pu swdio ? serial wire debug input/output. i/o - pio1_3 ? general purpose digi tal input/output pin. i- ad4 ? a/d converter, input 4. o- ct32b1_mat2 ? match output 2 for 32-bit timer 1. pio1_4/ad5/ ct32b1_mat3/ wakeup 40 [5] a6 [5] no i/o i; pu pio1_4 ? general purpose digital input/output pin with 10 ns glitch filter. i- ad5 ? a/d converter, input 5. o- ct32b1_mat3 ? match output 3 for 32-bit timer 1. i- wakeup ? deep power-down mode wake-up pin with 20 ns glitch filter. th is pin must be pulled high externally to enter deep power-down mode and pulled low to exit deep power-down mode. a low-going pulse as short as 50 ns wakes up the part. pio1_5/rts / ct32b0_cap0 45 [3] a3 [3] no i/o i; pu pio1_5 ? general purpose digi tal input/output pin. o- rts ? request to send output for uart. i- ct32b0_cap0 ? capture input 0 for 32-bit timer 0. pio1_6/rxd/ ct32b0_mat0 46 [3] b3 [3] no i/o i; pu pio1_6 ? general purpose digi tal input/output pin. i- rxd ? receiver input for uart. o- ct32b0_mat0 ? match output 0 for 32-bit timer 0. pio1_7/txd/ ct32b0_mat1 47 [3] b2 [3] no i/o i; pu pio1_7 ? general purpose digi tal input/output pin. o- txd ? transmitter output for uart. o- ct32b0_mat1 ? match output 1 for 32-bit timer 0. table 170. lpc1100xl series: lpc1113/14/15 pin description table (lqfp48 and tfbga48 package) ?continued symbol lqfp48 tfbga48 start logic input type reset state [1] description
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 179 of 543 nxp semiconductors um10398 chapter 11: lpc111x pin configuration (lpc1100xl series, pio1_8/ ct16b1_cap0 9 [3] f2 [3] no i/o i; pu pio1_8 ? general purpose digi tal input/output pin. i- ct16b1_cap0 ? capture input 0 for 16-bit timer 1. pio1_9/ ct16b1_mat0/ mosi1 17 [3] g4 [3] no i/o i; pu pio1_9 ? general purpose digi tal input/output pin. o- ct16b1_mat0 ? match output 0 for 16-bit timer 1. i/o - mosi1 ? master out slave in for spi1. pio1_10/ad6/ ct16b1_mat1/ miso1 30 [5] e8 [5] no i/o i; pu pio1_10 ? general purpose digital input/output pin. i- ad6 ? a/d converter, input 6. o- ct16b1_mat1 ? match output 1 for 16-bit timer 1. i/o - miso1 ? master in slave out for spi1. pio1_11/ad7/ ct32b1_cap1 42 [5] a5 [5] no i/o i; pu pio1_11 ? general purpose digital input/output pin. i- ad7 ? a/d converter, input 7. i- ct32b1_cap1 ? capture input 1 for 32-bit timer 1. pio2_0 to pio2_11 i/o port 2 ? port 2 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 2 pins depends on the function selected through the ioconfig register block. pio2_0/dtr /ssel1 2 [3] b1 [3] no i/o i; pu pio2_0 ? general purpose digi tal input/output pin. o- dtr ? data terminal ready output for uart. i/o - ssel1 ? slave select for spi1. pio2_1/dsr /sck1 13 [3] h1 [3] no i/o i; pu pio2_1 ? general purpose digi tal input/output pin. i- dsr ? data set ready input for uart. i/o - sck1 ? serial clock for spi1. pio2_2/dcd /miso1 26 [3] g8 [3] no i/o i; pu pio2_2 ? general purpose digi tal input/output pin. i- dcd ? data carrier detect input for uart. i/o - miso1 ? master in slave out for spi1. pio2_3/ri /mosi1 38 [3] a7 [3] no i/o i; pu pio2_3 ? general purpose digi tal input/output pin. i- ri ? ring indicator input for uart. i/o - mosi1 ? master out slave in for spi1. pio2_4/ ct16b1_mat1/ ssel1 19 [3] g5 [3] no i/o i; pu pio2_4 ? general purpose digi tal input/output pin. o- ct16b1_mat1 ? match output 1 for 16-bit timer 1. o- ssel1 ? slave select for spi1. pio2_5/ ct32b0_mat0 20 [3] h5 [3] no i/o i; pu pio2_5 ? general purpose digi tal input/output pin. o- ct32b0_mat0 ? match output 0 for 32-bit timer 0. pio2_6/ ct32b0_mat1 1 [3] a1 [3] no i/o i; pu pio2_6 ? general purpose digi tal input/output pin. o- ct32b0_mat1 ? match output 1 for 32-bit timer 0. pio2_7/ ct32b0_mat2/rxd 11 [3] g2 [3] no i/o i; pu pio2_7 ? general purpose digi tal input/output pin. o- ct32b0_mat2 ? match output 2 for 32-bit timer 0. i- rxd ? receiver input for uart. table 170. lpc1100xl series: lpc1113/14/15 pin description table (lqfp48 and tfbga48 package) ?continued symbol lqfp48 tfbga48 start logic input type reset state [1] description
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 180 of 543 nxp semiconductors um10398 chapter 11: lpc111x pin configuration (lpc1100xl series, pio2_8/ ct32b0_mat3/txd 12 [3] g1 [3] no i/o i; pu pio2_8 ? general purpose digi tal input/output pin. o- ct32b0_mat3 ? match output 3 for 32-bit timer 0. o- txd ? transmitter output for uart. pio2_9/ ct32b0_cap0 24 [3] h7 [3] no i/o i; pu pio2_9 ? general purpose digi tal input/output pin. i- ct32b0_cap0 ? capture input 0 for 32-bit timer 0. pio2_10 25 [3] h8 [3] no i/o i; pu pio2_10 ? general purpose digital input/output pin. pio2_11/sck0/ ct32b0_cap1 31 [3] d7 [3] no i/o i; pu pio2_11 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for spi0. i- ct32b0_cap1 ? capture input for 32-bit timer 0. pio3_0 to pio3_5 i/o port 3 ? port 3 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 3 pins depends on the function selected through the ioconfig register block. pins pio3_6 to pio3_11 are not available. pio3_0/dtr / ct16b0_mat0/txd 36 [3] b8 [3] no i/o i; pu pio3_0 ? general purpose digi tal input/output pin. o- dtr ? data terminal ready output for uart. o- ct16b0_mat0 ? match output 0 for 16-bit timer 0. o- txd ? transmitter output for uart. pio3_1/dsr / ct16b0_mat1/rxd 37 [3] a8 [3] no i/o i; pu pio3_1 ? general purpose digi tal input/output pin. i- dsr ? data set ready input for uart. o- ct16b0_mat1 ? match output 1 for 16-bit timer 0. i- rxd ? receiver input for uart. pio3_2/dcd / ct16b0_mat2/ sck1 43 [3] a4 [3] no i/o i; pu pio3_2 ? general purpose digi tal input/output pin. i- dcd ? data carrier detect input for uart. o- ct16b0_mat2 ? match output 2 for 16-bit timer 0. i/o - sck1 ? serial clock for spi1. pio3_3/ri / ct16b0_cap0 48 [3] a2 [3] no i/o i; pu pio3_3 ? general purpose digi tal input/output pin. i- ri ? ring indicator input for uart. i- ct16b0_cap0 ? capture input 0 for 16-bit timer 0. pio3_4/ ct16b0_cap1/rxd 18 [3] h4 [3] no i/o i; pu pio3_4 ? general purpose digi tal input/output pin. i- ct16b0_cap1 ? capture input 1 for 16-bit timer 0. i- rxd ? receiver input for uart pio3_5/ ct16b1_cap1/txd 21 [3] g6 [3] no i/o i; pu pio3_5 ? general purpose digi tal input/output pin. i- ct16b1_cap1 ? capture input 1 for 16-bit timer 1. o- txd ? transmitter output for uart v dd 8; 44 e2; b4 - i - 3.3 v supply voltage to the internal regulator, the external rail, and the adc. also used as the adc reference voltage. table 170. lpc1100xl series: lpc1113/14/15 pin description table (lqfp48 and tfbga48 package) ?continued symbol lqfp48 tfbga48 start logic input type reset state [1] description
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 181 of 543 nxp semiconductors um10398 chapter 11: lpc111x pin configuration (lpc1100xl series, [1] pin state at reset for default function: i = input; o = ou tput; pu = internal pull-up enabled (pins pulled up to full v dd level (v dd = 3.3 v)); ia = inactive, no pull-up/down enabled. [2] 5 v tolerant pad. reset functionality is not available in deep power-down mode. use the wakeup pin to reset the chip and wake up from deep power-down mode. an external pull-up resistor is required on this pin for the deep power-down mode. [3] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis. [4] i 2 c-bus pads compliant with the i 2 c-bus specification for i 2 c standard mode and i 2 c fast-mode plus. [5] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s, configurable hysteresis, and analog input. when configured as a adc input, digital section of t he pad is disabled and the pin is not 5 v tolerant. [6] when the system oscillator is not used, connect xtalin and xtalout as follows: xtalin can be left floating or can be grounde d (grounding is preferred to reduce susceptibilit y to noise). xtalout should be left floating. xtalin 6 [6] d1 [6] - i - input to the oscillator circuit and internal clock generator circuits. input voltage must not exceed 1.8 v. xtalout 7 [6] e1 [6] - o - output from the oscillator amplifier. v ss 5; 41 d2; b5 - i - ground. table 170. lpc1100xl series: lpc1113/14/15 pin description table (lqfp48 and tfbga48 package) ?continued symbol lqfp48 tfbga48 start logic input type reset state [1] description
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 182 of 543 nxp semiconductors um10398 chapter 11: lpc111x pin configuration (lpc1100xl series, table 171. LPC1111/12/13/14xl pin description table (hvqfn33 package) symbol pin start logic input type reset state [1] description pio0_0 to pio0_11 port 0 ? port 0 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 0 pins depends on the function selected through the ioconfig register block. reset /pio0_0 2 [2] yes i i;pu reset ? external reset input with 20 ns glitch filter. a low-going pulse as short as 50 ns on this pin resets the device, causing i/o ports and peripherals to take on their default states and processor execution to begin at address 0. i/o - pio0_0 ? general purpose digital input/output pin with 10 ns glitch filter. pio0_1/clkout/ ct32b0_mat2 3 [3] yes i/o i;pu pio0_1 ? general purpose digital input/ output pin. a low level on this pin during reset starts the isp command handler. o- clkout ? clock out pin. o- ct32b0_mat2 ? match output 2 for 32-bit timer 0. pio0_2/ssel0/ ct16b0_cap0 8 [3] yes i/o i;pu pio0_2 ? general purpose digital input/output pin. i/o - ssel0 ? slave select for spi0. i- ct16b0_cap0 ? capture input 0 for 16-bit timer 0. pio0_3 9 [3] yes i/o i;pu pio0_3 ? general purpose digital input/output pin. pio0_4/scl 10 [4] yes i/o i;pu pio0_4 ? general purpose digital input/output pin (open-drain). i/o - scl ? i 2 c-bus, open-drain clock input/output. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_5/sda 11 [4] yes i/o i;pu pio0_5 ? general purpose digital input/output pin (open-drain). i/o - sda ? i 2 c-bus, open-drain data input/out put. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_6/sck0 15 [3] yes i/o i;pu pio0_6 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for spi0. pio0_7/cts 16 [3] yes i/o i;pu pio0_7 ? general purpose digital inpu t/output pin (high-current output driver). i- cts ? clear to send input for uart. pio0_8/miso0/ ct16b0_mat0 17 [3] yes i/o i;pu pio0_8 ? general purpose digital input/output pin. i/o - miso0 ? master in slave out for spi0. o- ct16b0_mat0 ? match output 0 for 16-bit timer 0. pio0_9/mosi0/ ct16b0_mat1 18 [3] yes i/o i;pu pio0_9 ? general purpose digital input/output pin. i/o - mosi0 ? master out slave in for spi0. o- ct16b0_mat1 ? match output 1 for 16-bit timer 0. swclk/pio0_10/ sck0/ ct16b0_mat2 19 [3] yes i i;pu swclk ? serial wire clock. i/o - pio0_10 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for spi0. o- ct16b0_mat2 ? match output 2 for 16-bit timer 0.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 183 of 543 nxp semiconductors um10398 chapter 11: lpc111x pin configuration (lpc1100xl series, r/pio0_11/ad0/ ct32b0_mat3 21 [5] yes - i;pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio0_11 ? general purpose digital input/output pin. i- ad0 ? a/d converter, input 0. o- ct32b0_mat3 ? match output 3 for 32-bit timer 0. pio1_0 to pio1_11 port 1 ? port 1 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 1 pins depends on the function selected through the ioconfig register block. r/pio1_0/ad1/ ct32b1_cap0 22 [5] yes - i;pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_0 ? general purpose digital input/output pin. i- ad1 ? a/d converter, input 1. i- ct32b1_cap0 ? capture input 0 for 32-bit timer 1. r/pio1_1/ad2/ ct32b1_mat0 23 [5] no - i;pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_1 ? general purpose digital input/output pin. i- ad2 ? a/d converter, input 2. o- ct32b1_mat0 ? match output 0 for 32-bit timer 1. r/pio1_2/ad3/ ct32b1_mat1 24 [5] no - i;pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_2 ? general purpose digital input/output pin. i- ad3 ? a/d converter, input 3. o- ct32b1_mat1 ? match output 1 for 32-bit timer 1. swdio/pio1_3/ ad4/ct32b1_mat2 25 [5] no i/o i;pu swdio ? serial wire debug input/output. i/o - pio1_3 ? general purpose digital input/output pin. i- ad4 ? a/d converter, input 4. o- ct32b1_mat2 ? match output 2 for 32-bit timer 1. pio1_4/ad5/ ct32b1_mat3/ wakeup 26 [5] no i/o i;pu pio1_4 ? general purpose digital input/output pin with 10 ns glitch filter. i- ad5 ? a/d converter, input 5. o- ct32b1_mat3 ? match output 3 for 32-bit timer 1. i- wakeup ? deep power-down mode wake-up pin with 20 ns glitch filter. this pin must be pulled high externally to enter deep power-down mode and pulled low to exit deep power-down mode. a low-going pulse as short as 50 ns wakes up the part. pio1_5/rts / ct32b0_cap0 30 [3] no i/o i;pu pio1_5 ? general purpose digital input/output pin. o- rts ? request to send output for uart. i- ct32b0_cap0 ? capture input 0 for 32-bit timer 0. pio1_6/rxd/ ct32b0_mat0 31 [3] no i/o i;pu pio1_6 ? general purpose digital input/output pin. i- rxd ? receiver input for uart. o- ct32b0_mat0 ? match output 0 for 32-bit timer 0. table 171. LPC1111/12/13/14xl pin description table (hvqfn33 package) ?continued symbol pin start logic input type reset state [1] description
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 184 of 543 nxp semiconductors um10398 chapter 11: lpc111x pin configuration (lpc1100xl series, pio1_7/txd/ ct32b0_mat1 32 [3] no i/o i;pu pio1_7 ? general purpose digital input/output pin. o- txd ? transmitter output for uart. o- ct32b0_mat1 ? match output 1 for 32-bit timer 0. pio1_8/ ct16b1_cap0 7 [3] no i/o i;pu pio1_8 ? general purpose digital input/output pin. i- ct16b1_cap0 ? capture input 0 for 16-bit timer 1. pio1_9/ ct16b1_mat0/ mosi 12 [3] no i/o i;pu pio1_9 ? general purpose digital input/output pin. o- ct16b1_mat0 ? match output 0 for 16-bit timer 1. i/o - mosi ? master out slave in for spi1 pio1_10/ad6/ ct16b1_mat1/ miso 20 [5] no i/o i;pu pio1_10 ? general purpose digital input/output pin. i- ad6 ? a/d converter, input 6. o- ct16b1_mat1 ? match output 1 for 16-bit timer 1. i/o - miso1 ? master in slave out for spi1 pio1_11/ad7/ ct32b1_cap1 27 [5] no i/o i;pu pio1_11 ? general purpose digital input/output pin. i- ad7 ? a/d converter, input 7. i- ct32b1_cap1 ? capture input 1 for 32-bit timer 1. pio2_0 port 2 ? port 2 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 2 pins depends on the function selected through the ioconfig register block. pins pio2_1 to pio2_11 are not available. pio2_0/dtr /ssel1 1 [3] no i/o i;pu pio2_0 ? general purpose digital input/output pin. o- dtr ? data terminal ready output for uart. i/o - ssel1 ? slave select for spi1. pio3_0 to pio3_5 port 3 ? port 3 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 3 pins depends on the function selected through the ioconfig register block. pins pio3_0, pio3_1, pio3_3 and pio3_6 to pio3_11 are not available. pio3_2/ ct16b0_mat2/ sck1 28 [3] no i/o i;pu pio3_2 ? general purpose digital input/output pin. o- ct16b0_mat2 ? match output 2 for 16-bit timer 0. i/o - sck1 ? serial clock for spi1. pio3_4/ ct16b0_cap1/rxd 13 [3] no i/o i;pu pio3_4 ? general purpose digital input/output pin. i- ct16b0_cap1 ? capture input 1 for 16-bit timer 0. i- rxd ? receiver input for uart. pio3_5/ ct16b1_cap1/txd 14 [3] no i/o i;pu pio3_5 ? general purpose digital input/output pin. i- ct16b1_cap1 ? capture input 1 for 16-bit timer 1. o- txd ? transmitter output for uart. table 171. LPC1111/12/13/14xl pin description table (hvqfn33 package) ?continued symbol pin start logic input type reset state [1] description
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 185 of 543 nxp semiconductors um10398 chapter 11: lpc111x pin configuration (lpc1100xl series, [1] pin state at reset for default function: i = input; o = ou tput; pu = internal pull-up enabled (pins pulled up to full v dd level (v dd = 3.3 v)); ia = inactive, no pull-up/down enabled. [2] reset functionality is not available in deep power-down mode. us e the wakeup pin to reset the chip and wake up from deep power-down mode. an external pull-up resistor is required on this pin for the deep power-down mode. [3] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis. [4] i 2 c-bus pads compliant with the i 2 c-bus specification for i 2 c standard mode and i 2 c fast-mode plus. [5] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s, configurable hysteresis, and analog input. when configured as a adc input, digital section of t he pad is disabled, and the pin is not 5 v tolerant. [6] when the system oscillator is not used, connect xtalin and xtalout as follows: xtalin can be left floating or can be grounde d (grounding is preferred to reduce susceptibilit y to noise). xtalout should be left floating. v dd 6; 29 - i - 3.3 v supply voltage to the internal regulator, the external rail, and the adc. also used as the adc reference voltage. xtalin 4 [6] - i - input to the oscillator circuit and internal clock generator circuits. input voltage must not exceed 1.8 v. xtalout 5 [6] - o - output from the oscillator amplifier. v ss 33 - - - thermal pad. connect to ground. table 171. LPC1111/12/13/14xl pin description table (hvqfn33 package) ?continued symbol pin start logic input type reset state [1] description
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 186 of 543 12.1 how to read this chapter the number of gpio pins available on each port depends on the lpc111x/lpc11cxx part and the package. see ta b l e 1 7 2 for available gpio pins: register bits corresponding to pion_m pi ns which are not available are reserved. 12.2 introduction 12.2.1 features ? gpio pins can be configured as input or output by software. ? each individual port pin can serve as an edge or level-sensitive interrupt request. ? interrupts can be configured on single falling or rising edge s and on both edges. ? level-sensitive interrupt pins can be high or low-active. um10398 chapter 12: lpc111x/lpc11cxx general purpose i/o (gpio) rev. 12.1 ? 7 august 2013 user manual table 172. gpio configuration part package gpio port 0 gpio port 1 gpio port 2 gpio port 3 total gpio pins lpc1110 so20/ tssop20 pio0_0 to pio0_2; pio0_4 to pio0_6; pio0_8 to pio0_11 pio1_0 to pio1_3; pio1_6 to pio1_7 -- 16 LPC1111 hvqfn33 pio0_0 to pio0_11 pio1_0 to pio1_11 pio2_0 pio 3_2; pio3_4; pio3_5 28 lpc1112 tssop20 pio0_0 to pio0_3; pio0_8 to pio0_11 pio1_0 to pio1_3; pio1_6 to pio1_7 -- 14 tssop28 pio0_0 to pio0_1 1 pio1_0 to pio1_9 - - 22 hvqfn33 pio0_0 to pio0_11 pio1_0 to pio1_11 pio2_0 pio3_2; pio3_4; pio3_5 28 hvqfn33 pio0_0 to pio0_3; pio0_4 to pio0_11 pio1_0 to pio1_4; pio1_6 to pio1_8 -- lpc1113 hvqfn33 pio0_0 to pio0_11 pio1_0 to pio1_11 pio2_0 pio3_2; pio3_4; pio3_5 28 lqfp48 pio0_0 to pio0_11 pio1_0 to pio1 _11 pio2_0 to pio2_11 pio3_0 to pio3_5 42 lpc1114 tssop28 pio0_0 to pi o0_11 pio1_0 to pio1_9 - - 22 hvqfn33 pio0_0 to pio0_11 pio1_0 to pio1_11 pio2_0 pio3_2; pio3_4; pio3_5 28 lqfp48 pio0_0 to pio0_11 pio1_0 to pio1 _11 pio2_0 to pio2_11 pio3_0 to pio3_5 42 lpc11d14 lqfp100 pio0_0 to pio0_11 pio1_0 to pio1_11 pio2_0 to pio2_11 pio3_0 to pio3_5 42 lpc11c12 lqfp48 pio0_0 to pio0_11 pio1_0 to pio1_11 pio2_0 to pio2_11 pio3_0 to pio3_3 40 lpc11c14 lqfp48 pio0_0 to pio0_11 pio1_0 to pio1_11 pio2_0 to pio2_11 pio3_0 to pio3_3 40 lpc11c22 lqfp48 pio0_0 to pio0_11 pio1_0 to pio1_11 except pio1_9 pio2_0 to pio2_11 except pio2_4, pio2_5, pio2_9 pio3_0 to pio3_3 36 lpc11c24 lqfp48 pio0_0 to pio0_11 pio1_0 to pio1_11 except pio1_9 pio2_0 to pio2_11 except pio2_4, pio2_5, pio2_9 pio3_0 to pio3_3 36
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 187 of 543 nxp semiconductors um10398 chapter 12: lpc111x/lpc11cxx general purpose i/o (gpio) ? all gpio pins are inputs by default. ? reading and writing of data registers are masked by address bits 13:2. 12.3 register description each gpio register can be up to 12 bits wide and can be read or written using word or half-word operations at word addresses. 12.3.1 gpio data register the gpiondata register holds the current logic state of the pin (high or low), independently of whether the pin is configured as an gpio input or output or as another digital function. if the pin is configured as gpio output, the current value of the gpiondata register is driven to the pin. a read of the gpiondata register always return s the current logic level (state) of the pin independently of its configuration. because th ere is a single data register for both the value of the output driver and the state of t he pins input, write operations have different effects depending on the pins configuration: table 173. register overview: gpio (base address port 0: 0x5000 0000; port 1: 0x5001 0000, port 2: 0x5002 0000; port 3: 0x5003 0000) name access address offset description reset value gpiondata r/w 0x0000 to 0x3ff8 port n data address masking register locations for pins pion_0 to pion_11 (see section 12.4.1 ). n/a gpiondata r/w 0x3ffc port n data register for pins pion_0 to pion_11 n/a - - 0x4000 to 0x7ffc reserved - gpiondir r/w 0x8000 data direction register for port n 0x00 gpionis r/w 0x8004 interrupt s ense register for port n 0x00 gpionibe r/w 0x8008 interrupt both edges register for port n 0x00 gpioniev r/w 0x800c interrupt event register for port n 0x00 gpionie r/w 0x8010 interrupt mask register for port n 0x00 gpionris r 0x8014 raw interrupt status register for port n 0x00 gpionmis r 0x8018 masked interrupt status register for port n 0x00 gpionic w 0x801c interrupt clear register for port n 0x00 - - 0x8020 - 0xffff reserved 0x00 table 174. gpiondata register (gpio0data, address 0x5000 0000 to 0x5000 3ffc; gpio1data, address 0x5001 0000 to 0x5001 3ffc; gpio2data, address 0x5002 0000 to 0x5002 3ffc; gpio3data, address 0x5003 0000 to 0x5003 3ffc) bit description bit symbol description reset value access 11:0 data logic levels for pins pion _0 to pion_11. high = 1, low = 0. n/a r/w 31:12 - reserved - -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 188 of 543 nxp semiconductors um10398 chapter 12: lpc111x/lpc11cxx general purpose i/o (gpio) ? if a pin is configured as gpio input, a writ e to the gpiondata register has no effect on the pin level. a read returns the current state of the pin. ? if a pin is configured as gpio output, the current value of gpiondata register is driven to the pin. this value can be a result of writing to the gpiondata register, or it can reflect the previous state of the pin if the pin is switched to gpio output from gpio input or another digital function. a re ad returns the current state of the output latch. ? if a pin is configured as another digital function (input or output), a write to the gpiondata register has no effect on the pin level. a read returns the current state of the pin even if it is configured as an output. this means that by reading the gpiondata register, the digital output or inpu t value of a function other than gpio on that pin can be observed. the following rules apply when the pins are switched from input to output: ? pin is configured as input with a high level applied: ? change pin to output: pin drives high level. ? pin is configured as input with a low level applied: ? change pin to output: pin drives low level. the rules show that the pins mirror the current logic level. therefore floating pins may drive an unpredictable level when switched from input to output. 12.3.2 gpio data direction register 12.3.3 gpio interrupt sense register table 175. gpiondir register (gpio0dir, address 0x5000 8000 to gpio3dir, address 0x5003 8000) bit description bit symbol description reset value access 11:0 io selects pin x as input or output (x = 0 to 11). 0 = pin pion_x is configured as input. 1 = pin pion_x is configured as output. 0x00 r/w 31:12 - reserved - - table 176. gpionis register (gpio0is, addr ess 0x5000 8004 to gpio3is, address 0x5003 8004) bit description bit symbol description reset value access 11:0 isense selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = interrupt on pin pion_x is configured as edge sensitive. 1 = interrupt on pin pion_x is configured as level sensitive. 0x00 r/w 31:12 - reserved - -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 189 of 543 nxp semiconductors um10398 chapter 12: lpc111x/lpc11cxx general purpose i/o (gpio) 12.3.4 gpio interrupt both edges sense register 12.3.5 gpio interrupt event register 12.3.6 gpio interrupt mask register bits set to high in the gpionie register a llow the corresponding pins to trigger their individual interrupts and the combined gpionintr line. clearing a bit disables interrupt triggering on that pin. 12.3.7 gpio raw interrupt status register bits read high in the gpionris register reflec t the raw (prior to mask ing) interrupt status of the corresponding pins indicating that all the requirements have been met before they are allowed to trigger the gpioie. bits read as zero indicate that the corresponding input pins have not initiated an interrupt. the register is read-only. table 177. gpionibe register (gpio0ibe, ad dress 0x5000 8008 to gpio3ibe, address 0x5003 8008) bit description bit symbol description reset value access 11:0 ibe selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = interrupt on pin pion_x is controlled through register gpioniev. 1 = both edges on pin pion_x trigger an interrupt. 0x00 r/w 31:12 - reserved - - table 178. gpioniev register (gpio0iev, addr ess 0x5000 800c to gpio3iev, address 0x5003 800c) bit description bit symbol description reset value access 11:0 iev selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = depending on setting in register gpionis (see ta b l e 1 7 6 ), falling edges or low level on pin pion_x trigger an interrupt. 1 = depending on setting in register gpionis (see ta b l e 1 7 6 ), rising edges or high level on pin pion_x trigger an interrupt. 0x00 r/w 31:12 - reserved - - table 179. gpionie register (gpio0ie, addr ess 0x5000 8010 to gpio3ie, address 0x5003 8010) bit description bit symbol description reset value access 11:0 mask selects interrupt on pin x to be masked (x = 0 to 11). 0 = interrupt on pin pion_x is masked. 1 = interrupt on pin pion_x is not masked. 0x00 r/w 31:12 - reserved - -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 190 of 543 nxp semiconductors um10398 chapter 12: lpc111x/lpc11cxx general purpose i/o (gpio) 12.3.8 gpio masked inte rrupt status register bits read high in the gpionmis register reflect the status of the input lines triggering an interrupt. bits read as low indicate that ei ther no interrupt on the corresponding input pins has been generated or that the interrupt is masked. gpiomis is the state of the interrupt after masking. the register is read-only. 12.3.9 gpio interrupt clear register this register allows software to clear edge detection for port bits that are identified as edge-sensitive in the interrupt sense register . this register has no effect on port bits identified as level-sensitive. table 180. gpionris register (gpio0ris, ad dress 0x5000 8014 to gpio3ris, address 0x5003 8014) bit description bit symbol description reset value access 11:0 rawst raw interrupt status (x = 0 to 11). 0 = no interrupt on pin pion_x. 1 = interrupt requirements met on pion_x. 0x00 r 31:12 - reserved - - table 181. gpionmis register (gpio0mis, address 0x5000 8018 to gpio3mis, address 0x5003 8018) bit description bit symbol description reset value access 11:0 mask selects interrupt on pin x to be masked (x = 0 to 11). 0 = no interrupt or interrupt masked on pin pion_x. 1 = interrupt on pion_x. 0x00 r 31:12 - reserved - - table 182. gpionic register (gpio0ic, address 0x5000 801c to gpio3ic, address 0x5003 801c) bit description bit symbol description reset value access 11:0 clr selects interrupt on pin x to be cleared (x = 0 to 11). clears the interrupt edge detection logic. this register is write-only. remark: the synchronizer between the gpio and the nvic blocks causes a delay of 2 clocks. it is recommended to add two nops after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = no effect. 1 = clears edge detection logic for pin pion_x. 0x00 w 31:12 - reserved - -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 191 of 543 nxp semiconductors um10398 chapter 12: lpc111x/lpc11cxx general purpose i/o (gpio) 12.4 functional description 12.4.1 write/read data operation in order for software to be able to set gpio bits without affecting any other pins in a single write operation, bits [13:2] of a 14-bit wide address bus are used to create a 12-bit wide mask for write and read operations on the 12 gpio pins for each port. only gpiondata bits masked by 1 are affected by read and write operations. the masked gpiondata register can be located anywhere between address offsets 0x0000 to 0x3ffc in the gpion address space. reading and writing to the gpiondata register at address 0x3ffc sets all masking bits to 1. write operation if the address bit (i+2) associated with the gpio port bit i (i = 0 to 11) to be written is high, the value of the gpiodata register bit i is updated. if the address bit (i+2) is low, the corresponding gpiodata register bit i is left unchanged. fig 30. masked write operation to the gpiodata register 000000100110 111111100100 uuuuuu1uu10u 1312111098765432 00 address[13:2] address 0x098 data 0xfe4 gpiodata register at address + 0x098 u = unchanged
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 192 of 543 nxp semiconductors um10398 chapter 12: lpc111x/lpc11cxx general purpose i/o (gpio) read operation if the address bit associated with the gpio data bit is high, the value is read. if the address bit is low, the gpio data bit is read as 0. reading a port data register yields the state of port pins 11:0 anded with address bits 13:2. fig 31. masked read operation 000000110001 111111100100 000000100000 1312111098765432 00 address[13:2] address 0x0c4 port pin settings data read
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 193 of 543 13.1 how to read this chapter the uart block is identical for all lpc111x, lpc11d14, and lpc11cxx parts. the dsr , dcd , and ri modem signals are fully pinned out on the lqfp48 packages only. note that for parts of the lpc1100 series (l pc111x/101/201/301), t he uart pins must be configured before the uart clock can be enabled. no enabling sequence requirement exists for parts lpc11cxx , parts in the lpc1100l and lpc1100xl series, and lpc11d14. 13.2 basic configuration the uart is configured using the following registers: 1. pins: for the lpc111x/101/201/301 parts, the uart pins must be configured in the ioconfig register block ( section 7.4 ) before the uart clocks can be enabled in the sysahbclkctrl register. for all other pa rts, no special ena bling sequence is required. remark: if the modem input pins are used, the modem function location must be also selected in the uart location registers ( section 7.4 ) 2. power: in the sysahbclkct rl register, set bit 12 ( ta b l e 2 1 ). 3. peripheral clock: enable the uart peripheral clock by writing to the uartclkdiv register ( table 23 ). 13.3 features ? 16-byte receive and transmit fifos. ? register locations conform to 550 industry standard. ? receiver fifo trigger points at 1, 4, 8, and 14 bytes. ? built-in baud rate generator. ? uart allows for implementation of eith er software or hardware flow control. ? rs-485/eia-485 9-bit mode support with output enable. ? modem control. um10398 chapter 13: lpc111x/lpc11cxx uart rev. 12.1 ? 7 august 2013 user manual
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 194 of 543 nxp semiconductors um10398 chapter 13: lpc111x/lpc11cxx uart 13.4 pin description [1] lqfp48 packages only. the dsr , dcd , and ri modem inputs are multiplexed to two different pin locations. use the iocon_loc re gisters (see section 7.4 ) to select a physical location for each function on the lqfp48 pin package in addition to sele cting the function in the iocon registers. the dtr output is available in two pin location s as well. the output value of the dtr pin is driven in both locati ons identically, and the dtr function at any location can be selected simply by selecting the function in th e iocon register for that pin location. 13.5 register description the uart contains registers organized as shown in table 184 . the divisor latch access bit (dlab) is contained in u0lcr[7] and enables access to the divisor latches. the reset value reflects the data stored in used bits only. it does not include the content of reserved bits. table 183. uart pin description pin type description rxd input serial input. serial receive data. txd output serial output. serial transmit data. rts output request to send. rs-485 direction control pin. dtr output data terminal ready. dsr [1] input data set ready. cts input clear to send. dcd [1] input data carrier detect. ri [1] input ring indicator. table 184. register overview: uart (base address: 0x4000 8000) name access address offset description reset value u0rbr ro 0x000 receiver buffer register. contains the next received character to be read. (dlab=0) na u0thr wo 0x000 transmit holding register. the next character to be transmitted is written here. (dlab=0) na u0dll r/w 0x000 divisor latch lsb. least significan t byte of the baud rate divisor value. the full divisor is used to generate a baud rate from the fractional rate divider. (dlab=1) 0x01 u0dlm r/w 0x004 divisor latch msb. most significant byte of the baud rate divisor value. the full divisor is used to generate a baud rate from the fractional rate divider. (dlab=1) 0x00 u0ier r/w 0x004 interrupt enable register. contains individual interrupt enable bits for the 7 potential uart interrupts. (dlab=0) 0x00 u0iir ro 0x008 interrupt id register. identifies which interrupt(s) are pending. 0x01 u0fcr wo 0x008 fifo control register. cont rols uart fifo usage and modes. 0x00
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 195 of 543 nxp semiconductors um10398 chapter 13: lpc111x/lpc11cxx uart u0lcr r/w 0x00c line control register. contains controls for frame formatting and break generation. 0x00 u0mcr r/w 0x010 modem control register 0x00 u0lsr ro 0x014 line status register. contains flags for transmit and receive status, including line errors. 0x60 u0msr ro 0x018 modem status register 0x00 u0scr r/w 0x01c scratch pad register. eight-bit temporary storage for software. 0x00 u0acr r/w 0x020 auto-baud control register. cont ains controls for t he auto-baud feature. 0x00 - - 0x024 reserved - u0fdr r/w 0x028 fractional divider register. generates a clock input for the baud rate divider. 0x10 - - 0x02c reserved - u0ter r/w 0x030 transmit enable register. turns off uart transmitter for use with software flow control. 0x80 - - 0x034 - 0x048 reserved - u0rs485ctrl r/w 0x04c rs-485/eia-485 control. contai ns controls to configure various aspects of rs-485/eia-485 modes. 0x00 u0rs485adr match r/w 0x050 rs-485/eia-485 addr ess match. contains the address match value for rs-485/eia-485 mode. 0x00 u0rs485dly r/w 0x054 rs-485/eia- 485 direction control delay. 0x00 table 184. register overview: uart (base address: 0x4000 8000) name access address offset description reset value
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 196 of 543 nxp semiconductors um10398 chapter 13: lpc111x/lpc11cxx uart 13.5.1 uart receiver buffer regi ster (u0rbr - 0x4000 8000, when dlab = 0, read only) the u0rbr is the top byte of the uart rx fi fo. the top byte of the rx fifo contains the oldest character received and can be read via the bus interface. the lsb (bit 0) represents the oldest received data bit. if the character received is less than 8 bits, the unused msbs are padded with zeroes. the divisor latch access bit (dlab) in u0l cr must be zero in order to access the u0rbr. the u0rbr is always read only. since pe, fe and bi bits (see table 196 ) correspond to the byte sitting on the top of the rbr fifo (i.e. the one that will be read in th e next read fr om the rbr), th e right approach for fetching the valid pair of received byte and its status bits is first to read the content of the u0lsr register, and then to read a byte from the u0rbr. 13.5.2 uart transmitter holding re gister (u0thr - 0x4000 8000 when dlab = 0, write only) the u0thr is the top byte of the uart tx fifo. the top byte is the newest character in the tx fifo and can be written via the bus in terface. the lsb represents the first bit to transmit. the divisor latch access bit (dlab) in u0l cr must be zero in order to access the u0thr. the u0thr is always write only. 13.5.3 uart divisor latch lsb and ms b registers (u0dll - 0x4000 8000 and u0dlm - 0x4000 8004, when dlab = 1) the uart divisor latch is part of the uart baud rate generator and holds the value used, along with the fractional divider, to divide the uart_pclk clock in order to produce the baud rate clock, which must be 16x the desired baud rate. the u0dll and u0dlm registers together form a 16-bit divisor where u0dll contains the lower 8 bits of the divisor and u0dlm contains the higher 8 bits of the divisor. a 0x0000 value is treated like a 0x0001 value as division by zero is not allowed. the divisor latch access bit (dlab) in u0lcr must be one in order to access the uart divisor latches. details on how to select the right value for u0dll and u0dlm can be found in section 13.5.15 . table 185. uart receiver buffer register (u0rbr - address 0x4000 8000 when dlab = 0, read only) bit description bit symbol description reset value 7:0 rbr the uart receiver buffer regi ster contains the oldest received byte in the uart rx fifo. undefined 31:8 - reserved - table 186. uart transmitter holding register (u0thr - address 0x4000 8000 when dlab = 0, write only) bit description bit symbol description reset value 7:0 thr writing to the uart transmit holding register causes the data to be stored in the uart transmit fifo. the byte will be sent when it reaches the bottom of th e fifo and the tr ansmitter is available. na 31:8 - reserved -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 197 of 543 nxp semiconductors um10398 chapter 13: lpc111x/lpc11cxx uart 13.5.4 uart interrupt enable re gister (u0ier - 0x4000 8004, when dlab = 0) the u0ier is used to enable the four uart interrupt sources. table 187. uart divisor latch lsb register (u0dll - address 0x4000 8000 when dlab = 1) bit description bit symbol description reset value 7:0 dllsb the uart divisor latch lsb register, along with the u0dlm register, determines the baud rate of the uart. 0x01 31:8 - reserved - table 188. uart divisor latch msb register (u0dlm - address 0x4000 8004 when dlab = 1) bit description bit symbol description reset value 7:0 dlmsb the uart divisor latch m sb register, along with the u0dll register, determines the baud rate of the uart. 0x00 31:8 - reserved - table 189. uart interrupt enable register (u 0ier - address 0x4000 8004 when dlab = 0) bit description bit symbol value description reset value 0 rbrie rbr interrupt enable. enables the receive data available interrupt for uart. it also controls the character receive time-out interrupt. 0 0 disable the rda interrupt. 1 enable the rda interrupt. 1 threie thre interrupt enable. en ables the thre interrupt for uart. the status of this interrupt can be read from u0lsr[5]. 0 0 disable the thre interrupt. 1 enable the thre interrupt. 2 rxlie rx line interrupt enable. enables the uart rx line status interrupts. the status of this interrupt can be read from u0lsr[4:1]. 0 0 disable the rx line status interrupts. 1 enable the rx line status interrupts. 3 - - reserved - 6:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na 7 - - reserved 0 8 abeointen enables the end of auto-baud interrupt. 0 0 disable end of auto-baud interrupt. 1 enable end of auto-baud interrupt.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 198 of 543 nxp semiconductors um10398 chapter 13: lpc111x/lpc11cxx uart 13.5.5 uart interrupt identification register (u0iir - 0x4004 8008, read only) u0iir provides a status code that denotes the priority and source of a pending interrupt. the interrupts are frozen during a u0iir acce ss. if an interrupt occurs during a u0iir access, the interrupt is record ed for the next u0iir access. bits u0iir[9:8] are set by the auto-baud functi on and signal a time-out or end of auto-baud condition. the auto-baud interrupt conditions are cleared by setting the corresponding clear bits in the auto-baud control register. 9 abtointen enables the auto-baud time-out interrupt. 0 0 disable auto-baud time-out interrupt. 1 enable auto-baud time-out interrupt. 31:10 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na table 189. uart interrupt enable register (u 0ier - address 0x4000 8004 when dlab = 0) bit description ?continued bit symbol value description reset value table 190. uart interrupt identi fication register (u0iir - address 0x4004 8008, read only) bit description bit symbol valu e description reset value 0 intstatus interrupt status. note t hat u0iir[0] is active low. the pending interrupt can be determined by evaluating u0iir[3:1]. 1 0 at least one interrupt is pending. 1 no interrupt is pending. 3:1 intid interrupt identification. u0 ier[3:1] identifies an interrupt corresponding to the uart rx fifo. all other combinations of u0ier[3:1] not listed below are reserved (100,101,111). 0 0x3 1 - receive line status (rls). 0x2 2a - receive data available (rda). 0x6 2b - character time-out indicator (cti). 0x1 3 - thre interrupt. 0x0 4 - modem interrupt. 5:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na 7:6 fifoenable these bits are equivalent to u0fcr[0]. 0 8 abeoint end of auto-baud interrupt. true if auto-baud has finished successfully and interrupt is enabled. 0 9 abtoint auto-baud time-out inte rrupt. true if auto-baud has timed out and interrupt is enabled. 0 31:10 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 199 of 543 nxp semiconductors um10398 chapter 13: lpc111x/lpc11cxx uart if the intstatus bit is one and no interrupt is pendin g and the intid bits will be zero. if the intstatus is 0, a non auto-baud interrupt is pending in which case the intid bits identify the type of interrupt and handling as described in table 191 . given the status of u0iir[3:0], an interrupt handler routine can determine the cause of the interrupt and how to clear the active interrupt. the u0iir must be read in order to clear the interrupt prior to exiting the interrupt service routine. the uart rls interrupt (u0iir [3:1] = 011) is the highest pr iority interrupt and is set whenever any one of four error conditions occur on the uart rx input: overrun error (oe), parity error (pe), framing error (fe) and break interrupt (bi). the uart rx error condition that set the interrupt can be observed via u0lsr[4:1]. the interrupt is cleared upon a u0lsr read. the uart rda interrupt (u0iir[3:1] = 010) shar es the second level priority with the cti interrupt (u0iir[3:1] = 110). the rda is acti vated when the uart rx fifo reaches the trigger level defined in u0fcr7 :6 and is reset when the uart rx fifo depth falls below the trigger level. when the rda interrupt goes active, the cpu can read a block of data defined by the trigger level. the cti interrupt (u0iir[3:1] = 110) is a second level interrupt and is set when the uart rx fifo contains at least one character and no uart rx fifo activity has occurred in 3.5 to 4.5 character ti mes. any uart rx fifo activity (read or write of uart rsr) will clear the interrupt. this interrupt is intend ed to flush the uart rbr after a message has been received that is not a multiple of the tr igger level size. for example, if a peripheral wished to send a 105 character message and the trigger level was 10 characters, the cpu would receive 10 rda interrupts resulting in the transfer of 100 characters and 1 to 5 cti interrupts (depending on the service routine) resulting in the tran sfer of the remaining 5 characters. table 191. uart interrupt handling u0iir[3:0] value [1] priority interrupt type interrupt source interrupt reset 0001 - none none - 0110 highest rx line status / error oe [2] or pe [2] or fe [2] or bi [2] u0lsr read [2] 0100 second rx data available rx data available or trigger level reached in fifo (u0fcr0=1) u0rbr read [3] or uart fifo drops below trigger level
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 200 of 543 nxp semiconductors um10398 chapter 13: lpc111x/lpc11cxx uart [1] values 0000, 0011, 0101, 0111, 1000, 10 01, 1010, 1011,1101,1110,1111 are reserved. [2] for details see section 13.5.9 uart line status register (u0lsr - 0x4000 8014, read only) [3] for details see section 13.5.1 uart receiver buffer register (u0rbr - 0x4000 8000, when dlab = 0, read only) [4] for details see section 13.5.5 uart interrupt identification register (u0iir - 0x4004 8008, read only) and section 13.5.2 uart transmitter holding register (u0thr - 0x4000 8000 when dlab = 0, write only) the uart thre interrupt (u0iir[3:1] = 001) is a third level interr upt and is activated when the uart thr fifo is empty provided certain initialization conditions have been met. these initialization conditions are intended to give the uart thr fifo a chance to fill up with data to eliminate many thre interr upts from occurring at system start-up. the initialization conditions implement a one c haracter delay minus the stop bit whenever thre = 1 and there have not been at least two characters in the u0thr at one time since the last thre = 1 event. this delay is pr ovided to give the cpu time to write data to u0thr without a thre interr upt to decode and service. a thre interrupt is set immediately if the uart thr fifo has held two or more characters at one time and currently, the u0thr is empty. the thre inte rrupt is reset when a u0thr write occurs or a read of the u0iir occurs and the thre is the highest interr upt (u0iir[3:1] = 001). it is the lowest priority interrupt and is activated whenever there is any state change on modem inputs pins, dcd, dsr or cts. in addition, a low to high transition on modem input ri will generate a modem interrupt. th e source of the modem interrupt can be determined by examining msr[3:0]. a ms r read will clear th e modem interrupt. 13.5.6 uart fifo cont rol register (u0fcr - 0x4000 8008, write only) the u0fcr controls the operation of the uart rx and tx fifos. 1100 second character time-out indication minimum of one character in the rx fifo and no character input or removed during a time period depending on how many characters are in fifo and what the trigger level is set at (3.5 to 4.5 character times). the exact time will be: [(word length) ? 7 - 2] ? 8 + [(trigger level - number of characters) ? 8 + 1] rclks u0rbr read [3] 0010 third thre thre [2] u0iir read [4] (if source of interrupt) or thr write 0000 fourth modem status cts or dsr or ri or dcd msr read table 191. uart interrupt handling u0iir[3:0] value [1] priority interrupt type interrupt source interrupt reset
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 201 of 543 nxp semiconductors um10398 chapter 13: lpc111x/lpc11cxx uart 13.5.7 uart line control re gister (u0lcr - 0x4000 800c) the u0lcr determines the format of the data character that is to be transmitted or received. table 192. uart fifo control register (u0f cr - address 0x4000 8008, write only) bit description bit symbol value description reset value 0 fifoen fifo enable 0 0 uart fifos are disabled. must not be used in the application. 1 active high enable for both uart rx and tx fifos and u0fcr[7:1] access. this bit must be set for proper uart operation. any transition on this bit will automatically clear the uart fifos. 1 rxfifores rx fifo reset 0 0 no impact on either of uart fifos. 1 writing a logic 1 to u0fcr[1] will clear all bytes in uart rx fifo, reset the pointer logi c. this bit is self-clearing. 2 txfifores tx fifo reset 0 0 no impact on either of uart fifos. 1 writing a logic 1 to u0fcr[2] will clear all bytes in uart tx fifo, reset the pointer logic. this bit is self-clearing. 3 - - reserved 0 5:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na 7:6 rxtl rx trigger level. these two bits determine how many receiver uart fifo characters must be written before an interrupt is activated. 0 0x0 trigger level 0 (1 character or 0x01). 0x1 trigger level 1 (4 characters or 0x04). 0x2 trigger level 2 (8 characters or 0x08). 0x3 trigger level 3 (14 characters or 0x0e). 31:8 - - reserved - table 193. uart line control register (u0lcr - address 0x4000 800c) bit description bit symbol value description reset value 1:0 wls word length select 0 0x0 5-bit character length. 0x1 6-bit character length. 0x2 7-bit character length. 0x3 8-bit character length. 2 sbs stop bit select 0 0 1 stop bit. 1 2 stop bits (1.5 if u0lcr[1:0]=00).
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 202 of 543 nxp semiconductors um10398 chapter 13: lpc111x/lpc11cxx uart 13.5.8 uart modem control register the u0mcr enables the modem loopback mode and controls the modem output signals. 3 pe parity enable 0 0 disable parity generation and checking. 1 enable parity generation and checking. 5:4 ps parity select 0 0x0 odd parity. number of 1s in the transmitted character and the attached parity bit will be odd. 0x1 even parity. number of 1s in the transmitted character and the attached parity bit will be even. 0x2 forced 1 stick parity. 0x3 forced 0 stick parity. 6bc break control 0 0 disable break transmission. 1 enable break transmission. output pin uart txd is forced to logic 0 when u0lcr[6] is active high. 7 dlab divisor latch access bit 0 0 disable access to divisor latches. 1 enable access to divisor latches. 31: 8 - - reserved - table 193. uart line control register (u0lcr - address 0x4000 800c) bit description bit symbol value description reset value table 194. uart0 modem control register (u 0mcr - address 0x4000 8010) bit description bit symbol value description reset value 0 dtrc dtr control. source for modem output pin, dtr . this bit reads as 0 when modem loopback mode is active. 0 1 rtsc rts control. source for modem output pin rts . this bit reads as 0 when modem loopback mode is active. 0 3:2 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 203 of 543 nxp semiconductors um10398 chapter 13: lpc111x/lpc11cxx uart 13.5.8.1 auto-flow control if auto-rts mode is enabled the uarts re ceiver fifo hardware controls the rts output of the uart. if the auto-cts mode is enabled the uarts u0tsr hardware will only start transmitting if the cts input signal is asserted. 13.5.8.1.1 auto-rts the auto-rts function is enabled by setting th e rtsen bit. auto-rts data flow control originates in the u0rbr module and is linke d to the programmed receiver fifo trigger level. if auto-rts is enabled, th e data-flow is controlled as follows: when the receiver fifo level reaches the programmed trigger level, rts is deasserted (to a high value). it is possible that the sending uart sends an additional byte after the trigger level is reached (assuming the sending uart has another byte to send) because it might not recognize the deassertion of rts until after it has begun sending the additional byte. rts is automatically reasserted (to a low va lue) once the receiver fifo has reached the previous trigger level. the reassertion of rts signals the sending uart to continue transmitting data. if auto-rts mode is disabled, the rtsen bit controls the rts output of the uart. if auto-rts mode is enabled, hardware controls the rts output, and the actual value of rts will be copied in the rts control bit of the uart. as long as auto-rts is enabled, the value of the rts control bit is read-only for software. 4lms 0 loopback mode select. the modem loopback mode provides a mechanism to perform diagnostic loopback testing. serial data from the transmitter is connected internally to serial input of the receiver. input pin, rxd, has no effect on loopback and output pin, txd is held in marking state. the four modem inputs (cts , dsr , ri and dcd ) are disconnected externally. externally, the modem outputs (rts , dtr ) are set inactive. internally, the four modem outputs are connected to the four modem inputs. as a result of these connections, the upper four bits of the u0msr will be driven by the lower four bits of the u0mcr rat her than the four modem inputs in normal mode. this permits modem status interrupts to be generated in loopback mode by writing the lower four bits of u0mcr. 0 disable modem loopback mode. 1 enable modem loopback mode. 5 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. 0 6 rtsen rts flow control 0 0 disable auto-rts flow control. 1 enable auto-rts flow control. 7 ctsen cts flow control 0 0 disable auto-cts flow control. 1 enable auto-cts flow control. 31:8 - - reserved - table 194. uart0 modem control register (u 0mcr - address 0x4000 8010) bit description bit symbol value description reset value
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 204 of 543 nxp semiconductors um10398 chapter 13: lpc111x/lpc11cxx uart example: suppose the uart operating in type 550 mode has the trigger level in u0fcr set to 0x2, then, if auto-rts is enabled, the uart will deassert the rts output as soon as the receive fifo contains 8 bytes ( table 192 on page 201 ). the rts output will be reasserted as soon as the receive fifo hits the previous trigger level: 4 bytes. 13.5.8.1.2 auto-cts the auto-cts function is enabled by setting the ctsen bit. if auto-c ts is enabled, the transmitter circuitry in th e u0tsr module checks cts input before sending the next data byte. when cts is active (low), the transmitter sends the next byte. to stop the transmitter from sending the following byte, cts must be released before the middle of the last stop bit that is currently being sent. in auto-cts mode, a change of the cts signal does not trigger a modem status interrup t unless the cts interrupt enable bit is set, delta cts bit in the u0 msr will be set though. table 195 lists the conditions for generating a modem status interrupt. the auto-cts function reduces interrupts to the host system. when flow control is enabled, a cts state change does not trigger host interrupts because the device automatically controls its own transmitter. without auto-cts, the transmitter sends any data present in the transmit fifo and a receiver overrun error can result. figure 33 illustrates the auto-cts functional timing. fig 32. auto-rts functional timing start byte n stop start bits0..7 stop start bits0..7 stop n-1 n n-1 n-1 n-2 n-2 m+2 m+1 m m-1 uart1 rx rts1 pin uart1 rx fifo level uart1 rx fifo read ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ table 195. modem status interrupt generation enable modem status interrupt (u0er[3]) ctsen (u0mcr[7]) cts interrupt enable (u0ier[7]) delta cts (u0msr[0]) delta dcd or trailing edge ri or delta dsr (u0msr[3] or u0msr[2] or u0msr[1]) modem status interrupt 0x x x x no 10 x 0 0 no 10 x 1 x yes 10 x x 1 yes 11 0 x 0 no 11 0 x 1 yes 11 1 0 0 no 11 1 1 x yes 11 1 x 1 yes
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 205 of 543 nxp semiconductors um10398 chapter 13: lpc111x/lpc11cxx uart while starting transmission of the initial character, the cts signal is asserted. transmission will stall as soon as the pend ing transmission has co mpleted. the uart will continue transmitting a 1 bit as long as cts is de-asserted (high). as soon as cts gets de-asserted, transmission resumes and a start bit is sent followed by the data bits of the next character. 13.5.9 uart line status register (u0lsr - 0x4000 8014, read only) the u0lsr is a read only register that prov ides status information on the uart tx and rx blocks. fig 33. auto-cts functional timing start bits0..7 start bits0..7 stop start bits0..7 stop uart1 tx cts1 pin ~ ~ ~ ~ ~ ~ ~ ~ stop table 196. uart line status register (u0l sr - address 0x4000 8014, read only) bit description bit symbol value description reset value 0 rdr receiver data ready. u0lsr[0] is set when the u0rbr holds an unread character and is cl eared when the uart rbr fifo is empty. 0 0 u0rbr is empty. 1 u0rbr contains valid data. 1 oe overrun error. the overrun error condition is set as soon as it occurs. a u0lsr read clears u0lsr[1]. u0lsr[1] is set when uart rsr has a new character assembled and the uart rbr fifo is full. in this case , the uart rbr fifo will not be overwritten and the character in the uart rsr will be lost. 0 0 overrun error status is inactive. 1 overrun error status is active. 2 pe parity error. when the parity bit of a received character is in the wrong state, a parity erro r occurs. a u0lsr read clears u0lsr[2]. time of parity e rror detection is dependent on u0fcr[0]. note: a parity error is associated with the character at the top of the uart rbr fifo. 0 0 parity error status is inactive. 1 parity error status is active.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 206 of 543 nxp semiconductors um10398 chapter 13: lpc111x/lpc11cxx uart 3 fe framing error. when the stop bit of a received character is a logic 0, a framing error occurs. a u0lsr read clears u0lsr[3]. the time of the framing error detection is dependent on u0fcr0. upon detection of a framing error, the rx will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. however, it cannot be assumed that the next receiv ed byte will be correct even if there is no framing error. note: a framing error is associated with the character at the top of the uart rbr fifo. 0 0 framing error status is inactive. 1 framing error status is active. 4 bi break interrupt. when rxd1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. once the break condition has been detected, the receiver goes idle until rxd1 goes to marking state (all ones). a u0lsr read clears this status bit. the time of break detection is dependent on u0fcr[0]. note: the break interrupt is associated with the character at the top of the uart rbr fifo. 0 0 break interrupt status is inactive. 1 break interrupt status is active. 5 thre transmitter holding register empty. thre is set immediately upon detection of an empty uart thr and is cleared on a u0thr write. 1 0 u0thr contains valid data. 1 u0thr is empty. 6 temt transmitter empty. temt is set when both u0thr and u0tsr are empty; temt is cleared when either the u0tsr or the u0thr contain valid data. this bit is updated as soon as 50 % of the first stop bit has been transmitted or a byte has been written into the thr. 1 0 u0thr and/or the u0tsr contains valid data. 1 u0thr and the u0tsr are empty. 7 rxfe error in rx fifo. u0lsr[7] is set when a character with a rx error such as framing error, pari ty error or break interrupt, is loaded into the u0rbr. this bit is cleared when the u0lsr register is read and there are no subsequent errors in the uart fifo. 0 0 u0rbr contains no uart rx errors or u0fcr[0]=0. 1 uart rbr contains at least one uart rx error. 31: 8 - - reserved - table 196. uart line status register (u0l sr - address 0x4000 8014, read only) bit description ?continued bit symbol value description reset value
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 207 of 543 nxp semiconductors um10398 chapter 13: lpc111x/lpc11cxx uart 13.5.10 uart modem status register the u0msr is a read-only register that provides status information on the modem input signals. u0msr[3:0] is cleared on u0msr read. note that modem signals have no direct effect on the uart operation. they facilit ate the software implementation of modem signal operations. 13.5.11 uart scratch pad re gister (u0scr - 0x4000 801c) the u0scr has no effect on the uart operation. this register can be written and/or read at users discretion. there is no provision in the interrupt interface th at would indicate to the host that a read or write of the u0scr has occurred. table 197. uart modem status register (u0m sr - address 0x4000 8018) bit description bit symbol value description reset value 0 dcts delta cts. set upon state change of input cts . cleared on a u0msr read. 0 0 no change detected on modem input cts . 1 state change detected on modem input cts . 1 ddsr delta dsr. set upon state change of input dsr . cleared on a u0msr read. 0 0 no change detected on modem input dsr . 1 state change detected on modem input dsr . 2 teri trailing edge ri. set upon low to high transition of input ri . cleared on a u0msr read. 0 0 no change detected on modem input, ri . 1 low-to-high transition detected on ri . 3 ddcd delta dcd. set upon state change of input dcd . cleared on a u0msr read. 0 0 no change detected on modem input dcd . 1 state change detected on modem input dcd . 4 cts clear to send state. complement of input signal cts . this bit is connected to u0mcr[1] in modem loopback mode. 0 5 dsr data set ready state. complement of input signal dsr . this bit is connected to u0mcr[0] in modem loopback mode. 0 6 ri ring indicator state. complement of input ri . this bit is connected to u0mcr[2] in modem loopback mode. 0 7 dcd data carrier detect state. complement of input dcd . this bit is connected to u0mcr[3] in modem loopback mode. 0 31: 8 --reserved - table 198. uart scratch pad register (u0s cr - address 0x4000 801c) bit description bit symbol description reset value 7:0 pad a readable, writable byte. 0x00 31: 8 - reserved -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 208 of 543 nxp semiconductors um10398 chapter 13: lpc111x/lpc11cxx uart 13.5.12 uart auto-baud control register (u0acr - 0x4000 8020) the uart auto-baud control register (u0acr) controls the process of measuring the incoming clock/data rate for the baud rate generation and can be read and written at users discretion. 13.5.13 auto-baud the uart auto-baud function can be used to measure the incoming baud rate based on the at" protocol (hayes command). if enabl ed the auto-baud feat ure will measure the bit time of the receive data stream and set the divisor latch registers u0dlm and u0dll accordingly. auto-baud is started by setting the u0acr start bit. auto-baud can be stopped by clearing the u0acr start bit. the start bit will clear once auto-baud has finished and reading the bit will return the status of auto-baud (pending/finished). table 199. auto baud control register (u 0acr - address 0x4000 8020) bit description bit symbol value description reset value 0 start start bit. this bit is automatically cleared after auto-baud completion. 0 0 auto-baud stop (auto-baud is not running). 1 auto-baud start (auto-baud is running). auto-baud run bit. this bit is aut omatically cleared after auto-baud completion. 1 mode auto-baud mode select 0 0 mode 0. 1 mode 1. 2 autorestart restart enable 0 0 no restart 1 restart in case of time-out (counter restarts at next uart rx falling edge) 0 7:3 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. 0 8 abeointclr end of auto-baud in terrupt clear (write only accessible) 0 0 writing a 0 has no impact. 1 writing a 1 will clear the corresponding interrupt in the u0iir. 9 abtointclr auto-baud time-out interrupt clear (write only accessible) 0 0 writing a 0 has no impact. 1 writing a 1 will clear the corresponding interrupt in the u0iir. 31:10 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 209 of 543 nxp semiconductors um10398 chapter 13: lpc111x/lpc11cxx uart two auto-baud measuring modes are available which can be selected by the u0acr mode bit. in mode 0 the baud rate is meas ured on two subsequent falling edges of the uart rx pin (the falling edge of the start bi t and the falling edge of the least significant bit). in mode 1 the baud rate is measured betw een the falling edge and the subsequent rising edge of the uart rx pin (the length of the start bit). the u0acr autorestart bit can be used to automatically re start baud rate measurement if a time-out occurs (the rate measurement count er overflows). if this bit is set, the rate measurement will restart at the next falling edge of the uart rx pin. the auto-baud function can generate two interrupts. ? the u0iir abtoint interrupt will get set if the interrupt is enabled (u0ier abtointen is set and the auto-baud rate measurement counter overflows). ? the u0iir abeoint interrupt will get set if the interrupt is enabled (u0ier abeointen is set and the auto-baud has completed successfully). the auto-baud interrupts have to be cleared by setting the corresponding u0acr abtointclr and abeointen bits. the fractional baud rate generator must be disabled (divaddval = 0) during auto-baud. also, when auto-baud is used, any write to u0dlm and u0dll registers should be done before u0acr register write. the minimum and the maximum baud rates supported by uart are function of uart_pclk, number of data bits, stop bits and parity bits. (2) 13.5.14 auto-baud modes when the software is expecting an at" command, it configures the uart with the expected character format and sets the u0acr start bit. the initial values in the divisor latches u0dlm and u0dlm dont care. because of the a" or a" ascii coding (a" = 0x41, a" = 0x61), the uart rx pin sens ed start bit and the lsb of the expected character are delim ited by two falling edges. when th e u0acr start bit is set, the auto-baud protocol will ex ecute the following phases: 1. on u0acr start bit setting, the baud rate measurement counter is reset and the uart u0rsr is reset. the u0rsr baud ra te is switched to the highest rate. 2. a falling edge on uart rx pin triggers th e beginning of the start bit. the rate measuring counter will start counting uart_pclk cycles. 3. during the receipt of the start bit, 16 pu lses are generated on the rsr baud input with the frequency of the uart input clock, guaranteeing the start bit is stored in the u0rsr. ratemin 2p ? clk 16 2 15 ? ------------------------ - uart baudrate pclk 16 2 databits paritybits stopbits ++ + ?? ? ------------------------------------------------------------------------------------------------------------ ?? ratemax ==
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 210 of 543 nxp semiconductors um10398 chapter 13: lpc111x/lpc11cxx uart 4. during the receipt of the start bit (and the character lsb for mode = 0), the rate counter will continue incr ementing with the pre-sca led uart input clock (uart_pclk). 5. if mode = 0, the rate counter will stop on ne xt falling edge of the uart rx pin. if mode = 1, the rate counter will stop on the next rising edge of the uart rx pin. 6. the rate counter is loaded into u0dlm/ u0dll and the baud rate will be switched to normal operation. after setting the u0dlm/u0dll, the end of auto-baud interrupt u0iir abeoint will be set, if enabled. th e u0rsr will now cont inue receiving the remaining bits of the a/a" character. a. mode 0 (start bit and lsb are used for auto-baud) b. mode 1 (only start bit is used for auto-baud) fig 34. auto-baud a) mode 0 and b) mode 1 waveform uartn rx start bit lsb of 'a' or 'a' u0acr start rate counter start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop 'a' (0x41) or 'a' (0x61) 16 cycles 16 cycles 16xbaud_rate uartn rx start bit lsb of 'a' or 'a' rate counter 'a' (0x41) or 'a' (0x61) start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop u1acr start 16 cycles 16xbaud_rate
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 211 of 543 nxp semiconductors um10398 chapter 13: lpc111x/lpc11cxx uart 13.5.15 uart fractional divide r register (u0fdr - 0x4000 8028) the uart fractional divider register (u0fdr) controls the clock pre-scaler for the baud rate generation and can be read and written at the users discretion. this pre-scaler takes the apb clock and generates an output clock according to the specified fractional requirements. important: if the fractional divider is active (d ivaddval > 0) and dlm = 0, the value of the dll register must be 3 or greater. this register controls the clock pre-scaler for the baud rate generation. the reset value of the register keeps the fractional capabilities of uart disabled making sure that uart is fully software and hardware compatible with uarts not equipped with this feature. the uart baud rate can be calculated as: (3) where uart_pclk is the peripheral clock, u0dlm and u0dll are the standard uart baud rate divider registers, and divaddval and mulval are uart fractional baud rate generator specific parameters. the value of mulval and divaddval shou ld comply to the following conditions: 1. 1 ?? mulval ? 15 2. 0 ? divaddval ? 14 3. divaddval< mulval the value of the u0fdr should not be modified while transmitting/receiving data or data may be lost or corrupted. if the u0fdr register value does not comply to these two requests, then the fractional divider output is undefined. if divaddval is zero then the fractional divider is disabled, and the clock will not be divided. table 200. uart fractional divi der register (u0fdr - addre ss 0x4000 8028) bit description bit function description reset value 3:0 divaddval baud rate generation pre-scale r divisor value. if this field is 0, fractional baud rate generator will not impact the uart baud rate. 0 7:4 mulval baud rate pre-scaler multiplier value. this field must be greater or equal 1 for uart to operate properly, regardless of whether the fractional baud rate generator is used or not. 1 31:8 - reserved, user software shou ld not write ones to reserved bits. the value read from a reserved bit is not defined. 0 uart baudrate pclk 16 256 u0dlm ? u0dll + ?? ? 1 divaddval mulval ----------------------------- + ?? ?? ? ------------------------------------------------------------------------------------------------------------------------------- --- =
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 212 of 543 nxp semiconductors um10398 chapter 13: lpc111x/lpc11cxx uart 13.5.15.1 baud rate calculation uart can operate with or without using the fracti onal divider. in real-life applications it is likely that the desired baud rate can be achiev ed using several different fractional divider settings. the following algori thm illustrates one way of fi nding a set of dlm, dll, mulval, and divaddval values. such set of parameters yields a baud rate with a relative error of less than 1.1% from the desired one.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 213 of 543 nxp semiconductors um10398 chapter 13: lpc111x/lpc11cxx uart fig 35. algorithm for setting uart dividers pclk, br calculating uart baudrate (br) dl est = pclk/(16 x br) dl est is an integer? divaddval = 0 mulval = 1 tr u e fr est = 1.5 dl est = int(pclk/(16 x br x fr est )) 1.1 < fr est < 1.9? pick another fr est from the range [1.1, 1.9] fr est = pclk/(16 x br x dl est ) divaddval = table(fr est ) mulval = table(fr est ) dlm = dl est [15:8] dll = dl est [7:0] end false tr u e false
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 214 of 543 nxp semiconductors um10398 chapter 13: lpc111x/lpc11cxx uart 13.5.15.1.1 example 1: uart_pclk = 14.7456 mhz, br = 9600 according to the provided algorithm dl est = pclk/(16 x br) = 14.7456 mhz / (16 x 9600) = 96. since this dl est is an integer number, diva ddval = 0, mulval = 1, dlm = 0, and dll = 96. 13.5.15.1.2 example 2: uart_pclk = 12 mhz, br = 115200 according to the provided algorithm dl est = pclk/(16 x br) = 12 mhz / (16 x 115200) = 6.51. this dl est is not an integer number and the next step is to estimate the fr parameter. using an in itial estimate of fr est = 1.5 a new dl est = 4 is calculated and fr est is recalculated as fr est = 1.628. since fr est = 1.628 is within the specified range of 1.1 and 1.9, divaddval and mulval values can be obtained from the attached look-up table. the closest value for frest = 1.628 in the look-up table 201 is fr = 1.625. it is equivalent to divaddval = 5 and mulval = 8. based on these findings, the suggested uart setup would be: dlm = 0, dll = 4, divaddval = 5, and mulval = 8. according to equation 3 , the uarts baud rate is 115384. this rate has a relative error of 0.16% from the originally specified 115200. 13.5.16 uart transmit enable register (u0ter - 0x4000 8030) in addition to being equipped with full hardware flow control (auto-cts and auto-rts mechanisms described above), u0ter enables im plementation of software flow control. when txen = 1, uart transmitte r will keep sending data as long as they are available. as soon as txen becomes 0, uart transmission will stop. table 201. fractional divider setting look-up table fr divaddval/ mulval fr divaddval/ mulval fr divaddval/ mulval fr divaddval/ mulval 1.000 0/1 1.250 1/4 1.500 1/2 1.750 3/4 1.067 1/15 1.267 4/15 1.533 8/15 1.769 10/13 1.071 1/14 1.273 3/11 1.538 7/13 1.778 7/9 1.077 1/13 1.286 2/7 1.545 6/11 1.786 11/14 1.083 1/12 1.300 3/10 1.556 5/9 1.800 4/5 1.091 1/11 1.308 4/13 1.571 4/7 1.818 9/11 1.100 1/10 1.333 1/3 1.583 7/12 1.833 5/6 1.111 1/9 1.357 5/14 1.600 3/5 1.846 11/13 1.125 1/8 1.364 4/11 1.615 8/13 1.857 6/7 1.133 2/15 1.375 3/8 1.625 5/8 1.867 13/15 1.143 1/7 1.385 5/13 1.636 7/11 1.875 7/8 1.154 2/13 1.400 2/5 1.643 9/14 1.889 8/9 1.167 1/6 1.417 5/12 1.667 2/3 1.900 9/10 1.182 2/11 1.429 3/7 1.692 9/13 1.909 10/11 1.200 1/5 1.444 4/9 1.700 7/10 1.917 11/12 1.214 3/14 1.455 5/11 1.714 5/7 1.923 12/13 1.222 2/9 1.462 6/13 1.727 8/11 1.929 13/14 1.231 3/13 1.467 7/15 1.733 11/15 1.933 14/15
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 215 of 543 nxp semiconductors um10398 chapter 13: lpc111x/lpc11cxx uart although table 202 describes how to use txen bit in order to achieve hardware flow control, it is strongly suggested to let ua rt hardware implemented auto flow control features take care of this , and limit the scope of txen to software flow control. table 202 describes how to use txen bit in order to achieve software flow control. 13.5.17 uart rs485 control regist er (u0rs485ctrl - 0x4000 804c) the u0rs485ctrl register controls the configuration of the uart in rs-485/eia-485 mode. table 202. uart transmit enable register (u0ter - ad dress 0x4000 8030) bit description bit symbol description reset value 6:0 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na 7 txen when this bit is 1, as it is after a reset, data written to the thr is output on the txd pin as soon as any preceding data has been sent. if this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. in other words, a 0 in this bit blocks the transfer of characters from the thr or tx fifo into the transmit shift regi ster. software can clear this bit when it detects that the a hardware-handshaking tx-permit signal (cts ) has gone false, or with software handshaking, when it receives an xoff character (dc3). software can set this bit again when it detects th at the tx-permit signal has gone true, or when it receives an xon (dc1) character. 1 31:8 - reserved - table 203. uart rs485 control register (u0rs485ctrl - address 0x4000 804c) bit description bit symbol value description reset value 0 nmmen nmm enable. 0 0 rs-485/eia-485 normal multidrop mode (nmm) is disabled. 1 rs-485/eia-485 normal multidrop mode (nmm) is enabled. in this mode, an address is detected when a received byte causes the uart to set the parity error and generate an interrupt. 1 rxdis receiver enable. 0 0 the receiver is enabled. 1 the receiver is disabled. 2 aaden aad enable. 0 0 auto address detect (aad) is disabled. 1 auto address detect (aad) is enabled. 3 sel select direct ion control pin 0 0 if direction control is enabled (bit dctrl = 1), pin rts is used for direction control. 1 if direction control is enabled (bit dctrl = 1), pin dtr is used for direction control.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 216 of 543 nxp semiconductors um10398 chapter 13: lpc111x/lpc11cxx uart 13.5.18 uart rs485 address match re gister (u0rs485 adrmatch - 0x4000 8050) the u0rs485adrmatch register contains th e address match value for rs-485/eia-485 mode. 13.5.19 uart1 rs485 dela y value register (u0rs485dly - 0x4000 8054) the user may program the 8-bit rs485dly regist er with a delay between the last stop bit leaving the txfifo and the de-assertion of rts (or dtr ). this delay time is in periods of the baud clock. any delay time from 0 to 255 bit times may be programmed. 13.5.20 rs-485/eia-485 modes of operation the rs-485/eia-485 feature allows the uart to be configured as an addressable slave. the addressable slave is one of multiple slaves controlled by a single master. 4 dctrl auto direction control enable. 0 0 disable auto direction control. 1 enable auto direction control. 5 oinv polarity control. this bit reverses the polarity of the direction control signal on the rts (or dtr ) pin. 0 0 the direction control pin will be driven to logic 0 when the transmitter has data to be sent. it will be driven to logic 1 after the last bit of data has been transmitted. 1 the direction control pin will be driven to logic 1 when the transmitter has data to be sent. it will be driven to logic 0 after the last bit of data has been transmitted. 31:6 - - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na table 203. uart rs485 control register (u0rs485ctrl - address 0x4000 804c) bit description ?continued bit symbol value description reset value table 204. uart rs485 address match re gister (u0rs485adrmatch - address 0x4000 8050) bit description bit symbol description reset value 7:0 adrmatch contains the address match value. 0x00 31:8 - reserved - table 205. uart rs485 delay value register (u0rs485dly - address 0x4000 8054) bit description bit symbol description reset value 7:0 dly contains the direction control (rts or dtr) delay value. this register works in conjunction with an 8-bit counter. 0x00 31:8 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 217 of 543 nxp semiconductors um10398 chapter 13: lpc111x/lpc11cxx uart the uart master transmitter will identify an address character by se tting the parity (9th) bit to 1. for data characters , the parity bit is set to 0. each uart slave receiver can be assigned a unique address. the slave can be programmed to either manually or automatically reject data following an address which is not theirs. rs-485/eia-485 normal multidrop mode (nmm) setting the rs485ctrl bit 0 enables this mo de. in this mode, an address is detected when a received byte causes the uart to set the parity error and generate an interrupt. if the receiver is disabled (rs485ctrl bit 1 = 1), any received data bytes will be ignored and will not be stored in the rxfifo. when an ad dress byte is detected (parity bit = 1) it will be placed into the rxfifo and an rx da ta ready interrupt will be generated. the processor can then read the address byte and decide whether or not to enable the receiver to accept the following data. while the receiver is enabled (rs485ctrl bi t 1 =0), all received bytes will be accepted and stored in the rxfifo regardless of wh ether they are data or address. when an address character is received a parity error interrupt will be generated and the processor can decide whether or not to disable the receiver. rs-485/eia-485 auto address detection (aad) mode when both rs485ctrl register bits 0 (9-bit mode enable) and 2 (aad mode enable) are set, the uart is in auto address detect mode. in this mode, the receiver will compare any address byte receiv ed (parity = 1) to the 8-bit value programmed into the rs485adrmatch register. if the receiver is disabled (rs485ctrl bit 1 = 1), any received byte will be discarded if it is either a data byte or an address byte which fails to match the rs485adrmatch value. when a matching address character is detected it will be pushed on to the rxfifo along with the parity bit, an d the receiver will be automatically enabled (rs485ctrl bit 1 will be cleared by hardware). the receiver will al so generate an rx da ta ready interrupt. while the receiver is enabled (rs485ctrl bi t 1 = 0), all bytes received will be accepted and stored in the rxfifo until an address byte which does not match the rs485adrmatch value is received. when this occurs, the receiver will be automatically disabled in hardware (rs485ctrl bit 1 will be set), the received non-matching address character will not be stored in the rxfifo. rs-485/eia-485 auto direction control rs485/eia-485 mode includes the option of allowing the transmitte r to automatically control the state of the dir pin as a direction control output signal. setting rs485ctrl bit 4 = 1 enables this feature. direction control, if enabled, will use the rts pin when rs485ctrl bit 3 = 0. it will use the dtr pin when rs485ctrl bit 3 = 1.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 218 of 543 nxp semiconductors um10398 chapter 13: lpc111x/lpc11cxx uart when auto direction co ntrol is enabled, th e selected pin will be a sserted (driven low) when the cpu writes data into the txfifo . the pin will be de-asserted (driven high) once the last bit of data has been transm itted. see bits 4 and 5 in the rs485ctrl register. the rs485ctrl bit 4 takes precedence ov er all other mechanisms controlling the direction control pin with the exception of loopback mode. rs485/eia-485 driver delay time the driver delay time is the delay between th e last stop bit leaving the txfifo and the de-assertion of rts . this delay time can be programmed in the 8-bit rs485dly register. the delay time is in periods of the baud clock. any delay time from 0 to 255 bit times may be used. rs485/eia-485 output inversion the polarity of the direction control signal on the rts (or dtr ) pins can be reversed by programming bit 5 in the u0rs485ctrl register. when this bit is set, the direction control pin will be driven to logic 1 when the transmitte r has data waiting to be sent. the direction control pin will be driven to logic 0 after the last bit of data has been transmitted. 13.6 architecture the architecture of the uart is shown below in the block diagram. the apb interface provides a communications link between the cpu or host and the uart. the uart receiver block, u0rx , monitors the serial input li ne, rxd, for valid input. the uart rx shift register (u0rsr) accepts valid characters via rxd. after a valid character is assembled in the u0rsr, it is passed to the ua rt rx buffer register fifo to await access by the cpu or host via the generic host interface. the uart transmitter block, u0tx, accepts da ta written by the cpu or host and buffers the data in the uart tx hold ing register fifo (u0thr). the uart tx shift register (u0tsr) reads the data stored in the u0thr and assembles the data to transmit via the serial output pin, txd1. the uart baud rate generator block, u0brg, generates the timing enables used by the uart tx block. the u0brg clock input s ource is uart_pclk. the main clock is divided down per the divisor specified in the u0dll and u0dlm registers. this divided down clock is a 16x oversample clock, nbaudout. the interrupt interface contains registers u0ier and u0iir. the interrupt interface receives several one clock wide enables from the u0tx and u0rx blocks. status information from the u0 tx and u0rx is stored in the u0lsr. control information for the u0tx and u0rx is stored in the u0lcr.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 219 of 543 nxp semiconductors um10398 chapter 13: lpc111x/lpc11cxx uart fig 36. uart block diagram apb interface u0lcr u0rx ddis u0lsr u0fcr u0brg u0tx interrupt pa[2:0] psel pstb pwrite pd[7:0] ar mr pclk u0intr u0scr ntxrdy txd nbaudout rclk nrxrdy rxd u0rbr u0rsr u0dlm u0dll u0thr u0tsr u0iir u0ier
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 220 of 543 14.1 how to read this chapter the spi blocks are identical for all lpc111x, lpc11d14, and lpc11cxx parts. the second spi block, spi1, is available on lqfp48 packages. for parts in the lpc1100 and lpc1100l series, spi1 is not available on hvqfn33 packages. for parts in the lpc1100xl series, spi1 is supported on all packages. remark: both spi blocks include the full ssp feature set, and all regi ster names use the ssp prefix. 14.2 basic configuration the spi0/1 are configured using the following registers: 1. pins: the spi pins must be configured in the ioconfig register block. in addition, use the iocon_loc register (see section 7.4 ) to select a location for the sck0 function. 2. power: in the sysahbclkctrl regi ster, set bit 11 and bit 18 ( table 21 ). 3. peripheral clock: enable the spi0/1 periph eral clock by writing to the ssp0/1clkdiv registers ( section 3.5.15 and section 3.5.17 ). 4. reset: before accessing the spi blocks, ensure that th e ssp_rst_n bits (bit 0 and bit 2) in the preset ctrl register ( table 9 ) is set to 1. this de-asserts the reset signal to the spi blocks. 14.3 features ? compatible with motorola spi , 4-wire ti ssi, and national semiconductor microwire buses. ? synchronous serial communication. ? supports master or slave operation. ? eight-frame fifos for both transmit and receive. ? 4-bit to 16-bit frame. 14.4 general description the spi/ssp is a synchronous se rial port (ssp) controller ca pable of operation on a spi, 4-wire ssi, or microwire bus. it can interact with multiple masters and slaves on the bus. only a single master and a single slave can communicate on the bus during a given data transfer. data transfers are in principle full duplex, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from th e slave to the master. in practice it is often the case that only one of these data flows carries meaningful data. um10398 chapter 14: lpc111x/lpc11cxx spi0/1 with ssp rev. 12.1 ? 7 august 2013 user manual
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 221 of 543 nxp semiconductors um10398 chapter 14: lpc111x/lpc11cxx spi0/1 with ssp the lpc111x/lpc11cxx has two spi/synchronous serial port controllers. 14.5 pin description remark: the sck0 function is multip lexed to three different pin locations (two locations on the hvqfn package). use the iocon_loc register (see section 7.4 ) to select a physical location for the sck0 function in a ddition to selecting the function in the iocon registers. the sck1 pin is not multiplexed. table 206. spi pin descriptions pin name type interface pin name/function pin description spi ssi microwire sck0/1 i/o sck clk sk serial clock. sck/clk/sk is a clock signal used to synchronize the transfer of data. it is driven by the master and received by the slave. when spi/ssp interface is used, the clock is programmable to be active-high or active-low, otherwise it is always active-high. sck only switches during a data transfer. any other time, the spi/ssp interface either hold s it in its inactive state or does not drive it (leaves it in high-impedance state). ssel0/1 i/o ssel fs cs frame sync/slave select. when the spi/ssp interface is a bus master, it drives this signal to an active state before the start of serial data and then releases it to an inactive state after the data has been sent.the active state of this signal can be high or low depending upon the selected bus and mode. when the spi/ssp inte rface is a bus slave, this signal qualifies the presence of data from the master according to the protocol in use. when there is just one bus master and one bus slave, the frame sync or slave select signal from the master can be connected directly to the slaves corresponding input. when there is more than one slave on the bus, further qual ification of their frame select/slave select inputs will typically be necessary to prevent more than one slave from responding to a transfer. miso0/1 i/o miso dr(m) dx(s) si(m) so(s) master in slave out. the miso signal transfers serial data from the slave to the master. when the spi/ssp is a slave, serial data is output on this signal. when the spi/ssp is a master, it clocks in serial data from this signal. when the spi/ssp is a slave and is not selected by fs/ ssel, it does not drive this signal (leaves it in high-impedance state). mosi0/1 i/o mosi dx(m) dr(s) so(m) si(s) master out slave in. the mosi signal transfers serial data from the master to the slave. when the spi/ssp is a master, it outputs serial data on this signal. when the spi/ssp is a slave, it clocks in serial data from this signal.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 222 of 543 nxp semiconductors um10398 chapter 14: lpc111x/lpc11cxx spi0/1 with ssp 14.6 register description the register addresses of the spi controllers are shown in table 207 and table 208 . the reset value reflects the data stored in used bits only. it does not include the content of reserved bits. remark: register names use the ssp prefix to indicate that the spi controllers have full ssp capabilities. 14.6.1 spi/ssp control register 0 this register controls the basic operation of the spi/ssp controller. table 207. register overview: spi0 (base address 0x4004 0000) name access address offset description reset value ssp0cr0 r/w 0x000 control register 0. selects the serial clock ra te, bus type, a nd data size. 0 ssp0cr1 r/w 0x004 control register 1. selects master/slave and other modes. 0 ssp0dr r/w 0x008 data register. wr ites fill the transmit fifo, and reads empty the receive fifo. 0 ssp0sr ro 0x00c status register 0x0000 0003 ssp0cpsr r/w 0x010 clock prescale register 0 ssp0imsc r/w 0x014 interrupt ma sk set and clear register 0 ssp0ris ro 0x018 raw interrupt status register 0x0000 0008 ssp0mis ro 0x01c masked interru pt status register 0 ssp0icr wo 0x020 sspicr interru pt clear register na table 208. register overview: spi1 (base address 0x4005 8000) name access address offset description reset value ssp1cr0 r/w 0x000 control register 0. selects the serial clock ra te, bus type, a nd data size. 0 ssp1cr1 r/w 0x004 control register 1. selects master/slave and other modes. 0 ssp1dr r/w 0x008 data register. wr ites fill the transmit fifo, and reads empty the receive fifo. 0 ssp1sr ro 0x00c status register 0x0000 0003 ssp1cpsr r/w 0x010 clock prescale register 0 ssp1imsc r/w 0x014 interrupt ma sk set and clear register 0 ssp1ris ro 0x018 raw interrupt status register 0x0000 0008 ssp1mis ro 0x01c masked interru pt status register 0 ssp1icr wo 0x020 sspicr interru pt clear register na
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 223 of 543 nxp semiconductors um10398 chapter 14: lpc111x/lpc11cxx spi0/1 with ssp 14.6.2 spi/ssp0 control register 1 this register contro ls certain aspects of the operation of the spi/ssp controller. table 209: spi/ssp control register 0 (ssp0 cr0 - address 0x4004 00 00, ssp1cr0 - address 0x4005 8000) bit description bit symbol value description reset value 3:0 dss data size select. this field controls the number of bits transferred in each frame. values 0000-0010 are not supported and should not be used. 0000 0x3 4-bit transfer 0x4 5-bit transfer 0x5 6-bit transfer 0x6 7-bit transfer 0x7 8-bit transfer 0x8 9-bit transfer 0x9 10-bit transfer 0xa 11-bit transfer 0xb 12-bit transfer 0xc 13-bit transfer 0xd 14-bit transfer 0xe 15-bit transfer 0xf 16-bit transfer 5:4 frf frame format. 00 0x0 spi 0x1 ti 0x2 microwire 0x3 this combination is not supported and should not be used. 6 cpol clock out polarity. this bit is only used in spi mode. 0 0 spi controller maintains the bus clock low between frames. 1 spi controller maintains the bus clock high between frames. 7 cpha clock out phase. this bit is only used in spi mode. 0 0 spi controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line. 1 spi controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line. 15:8 scr serial clock rate. the numbe r of prescaler ou tput clocks per bit on the bus, minus one. given that cpsdvsr is the prescale divider, and the apb clock pclk clocks the prescaler, the bit frequency is pclk / (cpsdvsr ? [scr+1]). 0x00 31:16 - - reserved -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 224 of 543 nxp semiconductors um10398 chapter 14: lpc111x/lpc11cxx spi0/1 with ssp 14.6.3 spi/ssp data register software can write data to be transmitted to this register and read data that has been received. table 210: spi/ssp control register 1 (ssp0 cr1 - address 0x4004 00 04, ssp1cr1 - address 0x4005 8004) bit description bit symbol value description reset value 0 lbm loop back mode. 0 0 during normal operation. 1 serial input is taken from the serial output (mosi or miso) rather than the serial input pin (miso or mosi respectively). 1 sse spi enable. 0 0 the spi controller is disabled. 1 the spi controller will interact with other devices on the serial bus. software should write the appropriate control information to the other spi/ssp registers and interrupt controller registers, before setting this bit. 2 ms master/slave mode.this bit can only be written when the sse bit is 0. 0 0 the spi controller acts as a ma ster on the bus, driving the sclk, mosi, and ssel lines and receiving the miso line. 1 the spi controller acts as a slave on the bus, driving miso line and receiving sclk , mosi, and ssel lines. 3 sod slave output disable. this bit is relevant only in slave mode (ms = 1). if it is 1, this blocks this spi controller from driving the transmit data line (miso). 0 31:4 - reserved, user software s hould not write ones to reserved bits. the value read from a reserved bit is not defined. na table 211: spi/ssp data register (ssp0dr - address 0x4004 0008, ssp1dr - address 0x4005 8008) bit description bit symbol description reset value 15:0 data write: software can write data to be sent in a future frame to this register whenever the tnf bit in the status register is 1, indicating that the tx fifo is not full. if the tx fifo was previously empty and the spi controller is not busy on the bus, transmission of the data will begi n immediately. otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). if the data length is less than 16 bit, software must right-justify the data written to this register. read: software can read data from this register whenever the rne bit in the status register is 1, indicating that the rx fifo is not empty. when software reads this register, the spi controller returns data from the least recent frame in the rx fifo. if the data length is less than 16 bit, th e data is right-justified in this field with higher order bits filled with 0s. 0x0000 31:16 - reserved. -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 225 of 543 nxp semiconductors um10398 chapter 14: lpc111x/lpc11cxx spi0/1 with ssp 14.6.4 spi/ssp status register this read-only register reflects the current status of the spi controller. 14.6.5 spi/ssp clock prescale register this register controls the factor by which the prescaler divides the spi peripheral clock spi_pclk to yield the prescaler clock that is, in turn, divided by the scr factor in the sspcr0 registers, to de termine the bit clock. important: the sspncpsr value must be properly initialized, or the spi controller will not be able to transmit data correctly. in slave mode, the spi clock rate provided by the master must not exceed 1/12 of the spi peripheral clock selected in section 3.5.15 . the content of the sspn cpsr register is not relevant. in master mode, cpsdvsr min = 2 or larger (even numbers only). 14.6.6 spi/ssp interrupt m ask set/clear register this register controls whether each of the four possible interrup t conditions in the spi controller are enabled. note that arm uses the word masked in the opposite sense from classic computer terminology, in which masked meant disabled. arm uses the word masked to mean enabled . to avoid confusion we will not use the word masked. table 212: spi/ssp status register (ssp0sr - address 0x4004 000c, ssp1sr - address 0x4005 800c) bit description bit symbol description reset value 0 tfe transmit fifo empty. this bi t is 1 is the transmit fifo is empty, 0 if not. 1 1 tnf transmit fifo not full. this bit is 0 if the tx fifo is full, 1 if not. 1 2 rne receive fifo not empty. this bit is 0 if the receive fifo is empty, 1 if not. 0 3 rff receive fifo full. this bit is 1 if the receive fifo is full, 0 if not. 0 4 bsy busy. this bit is 0 if the spi controller is idle, 1 if it is currently sending/receiving a frame and/or the tx fifo is not empty. 0 31:5 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na table 213: spi/ssp clock prescale register (ssp0cpsr - address 0x4004 0010, ssp1cpsr - address 0x4005 8010) bit description bit symbol description reset value 7:0 cpsdvsr this even value between 2 and 254, by which spi_pclk is divided to yield the prescaler output clock. bit 0 always reads as 0. 0 31:8 - reserved. -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 226 of 543 nxp semiconductors um10398 chapter 14: lpc111x/lpc11cxx spi0/1 with ssp 14.6.7 spi/ssp raw interrupt status register this read-only register contains a 1 for ea ch interrupt condition that is asserted, regardless of whether or no t the interrupt is enabled in the sspimsc registers. 14.6.8 spi/ssp masked inte rrupt status register this read-only register contains a 1 for each interrupt condition that is asserted and enabled in the sspimsc register s. when an spi interrupt o ccurs, the interrupt service routine should read this register to determine the cause(s) of the interrupt. table 214: spi/ssp interrupt m ask set/clear register (ssp0 imsc - address 0x4004 0014, ssp1imsc - address 0x4005 8014) bit description bit symbol description reset value 0 rorim software should set this bi t to enable interrupt when a receive overrun occurs, that is, when the rx fifo is full a nd another frame is completely received. the arm spec implies that the preceding frame data is overwritten by the new frame data when this occurs. 0 1 rtim software should set this bit to enable interrupt when a receive time-out condition occurs. a receive time-out occurs when the rx fifo is not empty, and no has no t been read for a time-out period. the time-out period is the same for master and slave modes and is determined by the ssp bit rate: 32 bits at pclk / (cpsdvsr ? [scr+1]). 0 2 rxim software should set this bit to enabl e interrupt when the rx fifo is at least half full. 0 3 txim software should set this bit to enable interrupt when the tx fifo is at least half empty. 0 31:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na table 215: spi/ssp raw interrupt status regi ster (ssp0ris - address 0x4004 0018, ssp1ris - address 0x4005 8018) bit description bit symbol description reset value 0 rorris this bit is 1 if another fram e was completely received while the rxfifo was full. the arm spec implies that the preceding frame data is overwritten by the new frame data when this occurs. 0 1 rtris this bit is 1 if the rx fifo is not empty, and has not been read for a time-out period. the time-out period is the same for master and slave modes and is determined by the ssp bit rate: 32 bits at pclk / (cpsdvsr ? [scr+1]). 0 2 rxris this bit is 1 if the rx fifo is at least half full. 0 3 txris this bit is 1 if the tx fifo is at least half empty. 1 31:4 - reserved, user software sh ould not write ones to reserved bits. the value read from a reserved bit is not defined. na
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 227 of 543 nxp semiconductors um10398 chapter 14: lpc111x/lpc11cxx spi0/1 with ssp 14.6.9 spi/ssp interrupt clear register software can write one or more one(s) to this write-only register, to clear the corresponding interrupt condition(s) in the spi controller. note that the other two interrupt conditions can be cleared by writing or re ading the appropriate fifo or disabled by clearing the corr esponding bit in sspimsc registers. 14.7 functional description 14.7.1 texas instruments sy nchronous serial frame format figure 37 shows the 4-wire texas instruments synchronous serial frame format supported by the spi module. table 216: spi/ssp masked interrupt status register (ssp0mis - address 0x4004 001c, ssp1mis - address 0x4005 801c) bit description bit symbol description reset value 0 rormis this bit is 1 if another frame was completely received while the rxfifo was full, and this interrupt is enabled. 0 1 rtmis this bit is 1 if the rx fifo is not empty, has not been read for a time-out period, and this interrupt is enabled. the time-out period is the same for master and slave modes and is determined by the ssp bit rate: 32 bits at pclk / (cpsdvsr ? [scr+1]). 0 2 rxmis this bit is 1 if the rx fifo is at least half full, and this interrupt is enabled. 0 3 txmis this bit is 1 if the tx fifo is at least half empty, and this interrupt is enabled. 0 31:4 - reserved, user software sh ould not write ones to reserved bits. the value read from a reserved bit is not defined. na table 217: spi/ssp interrupt clear register (ssp0icr - address 0x4004 0020, ssp1icr - address 0x4005 8020) bit description bit symbol description reset value 0 roric writing a 1 to this bit clear s the frame was received when rxfifo was full interrupt. na 1 rtic writing a 1 to this bit clears the rx fifo was not empty and has not been read for a timeout period interrupt. the timeout period is the same for master and slave modes and is determined by the ssp bit rate: 32 bits at pclk / (cpsdvsr ? [scr+1]). na 31:2 - reserved, user software sh ould not write ones to reserved bits. the value read from a reserved bit is not defined. na
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 228 of 543 nxp semiconductors um10398 chapter 14: lpc111x/lpc11cxx spi0/1 with ssp for device configured as a master in this mode, clk and fs are forced low, and the transmit data line dx is in 3-state mode when ever the ssp is idle. on ce the bottom entry of the transmit fifo contains data, fs is pulsed high for one clk period. the value to be transmitted is also transferred from the tran smit fifo to the serial shift register of the transmit logic. on the next rising edge of clk, the msb of the 4-bit to 16-bit data frame is shifted out on the dx pin. likewise, the msb of the received data is shifted onto the dr pin by the off-chip serial slave device. both the ssp and the off-chip serial slave device then clock each data bit into their serial shifter on the falling edge of each clk. the rece ived data is transfer red from the serial shifter to the receive fifo on the first rising edge of clk after the lsb has been latched. 14.7.2 spi frame format the spi interface is a four -wire interface where the ssel signal behaves as a slave select. the main feature of the spi format is that the inactive state and phase of the sck signal are programmabl e through the cpol and cpha bits within the sspcr0 control register. 14.7.2.1 clock polarity (cpol) and phase (cpha) control when the cpol clock polarity control bit is lo w, it produces a steady state low value on the sck pin. if the cpol clock polarity contro l bit is high, a steady state high value is placed on the clk pin when data is not being transferred. a. single frame transfer b. continuous/back-to-back frames transfer fig 37. texas instruments synchronous serial frame format: a) single and b) continuous/back-to-back two frames transfer clk fs dx/dr 4 to 16 bits msb lsb clk fs dx/dr lsb msb lsb msb 4 to 16 bits 4 to 16 bits
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 229 of 543 nxp semiconductors um10398 chapter 14: lpc111x/lpc11cxx spi0/1 with ssp the cpha control bit selects the clock edge that captures data and allows it to change state. it has the most impact on the first bit tr ansmitted by either allowing or not allowing a clock transition before the first data captur e edge. when the cpha phase control bit is low, data is captured on the first clock edge transition. if the cpha clock phase control bit is high, data is captured on the second clock edge transition. 14.7.2.2 spi format with cpol=0,cpha=0 single and continuous transmission signal sequences for spi format with cpol = 0, cpha = 0 are shown in figure 38 . in this configuration, during idle periods: ? the clk signal is forced low. ? ssel is forced high. ? the transmit mosi/miso pad is in high impedance. if the spi/ssp is enabled and there is valid da ta within the transmit fifo, the start of transmission is signified by the ssel master si gnal being driven low. this caus es slave data to be enabled onto the miso input line of the master. masters mosi is enabled. one half sck period later, valid master data is transferred to the mosi pin. now that both the master and slave data have been set, the sck master clock pin goes high after one further half sck period. the data is captured on the rising and prop agated on the fa lling edges of the sck signal. a. single transfer with cpol=0 and cpha=0 b. continuous transfer with cpol=0 and cpha=0 fig 38. spi frame format with cpol=0 and cpha=0 (a) single and b) continuous transfer) sck ssel mosi msb lsb q msb lsb 4 to 16 bits miso sck ssel mosi miso 4 to 16 bits 4 to 16 bits msb lsb msb lsb q msb lsb q msb lsb
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 230 of 543 nxp semiconductors um10398 chapter 14: lpc111x/lpc11cxx spi0/1 with ssp in the case of a single word transmission, after all bits of the data word have been transferred, the ssel line is returned to its idle high state one sck period after the last bit has been captured. however, in the case of continuous back-to- back transmissions, the ssel signal must be pulsed high between each data word transfe r. this is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the cpha bit is logic zero. theref ore the master device must raise the ssel pin of the slave device between each data transfer to enable the serial peripheral data write. on completion of the continuous transfer, the ssel pin is retur ned to its idle state one sck period after the last bit has been captured. 14.7.2.3 spi format with cpol=0,cpha=1 the transfer signal sequence for spi format with cpol = 0, cpha = 1 is shown in figure 39 , which covers both single and continuous transfers. in this configuration, during idle periods: ? the clk signal is forced low. ? ssel is forced high. ? the transmit mosi/miso pad is in high impedance. if the spi/ssp is enabled and there is valid da ta within the transmit fifo, the start of transmission is signified by the ssel master signal being driven low. masters mosi pin is enabled. after a further one half sck period, both master and slave valid data is enabled onto their respective transmission lines. at the same time, the sck is enabled with a rising edge transition. data is then captured on the falling edges and propagated on the rising edges of the sck signal. in the case of a single word transfer, after all bits have be en transferred, the ssel line is returned to its idle high state one sck period after the last bit has been captured. for continuous back-to-back transfers, the ssel pin is held low between successive data words and termination is the same as that of the single word transfer. 14.7.2.4 spi format with cpol = 1,cpha = 0 single and continuous transmission sign al sequences for spi format with cpol=1, cpha=0 are shown in figure 40 . fig 39. spi frame format with cpol=0 and cpha=1 sck ssel mosi q 4 to 16 bits miso q msb msb lsb lsb
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 231 of 543 nxp semiconductors um10398 chapter 14: lpc111x/lpc11cxx spi0/1 with ssp in this configuration, during idle periods: ? the clk signal is forced high. ? ssel is forced high. ? the transmit mosi/miso pad is in high impedance. if the spi/ssp is enabled and there is valid da ta within the transmit fifo, the start of transmission is signified by the ssel master signal being driven low, which causes slave data to be immediately transferred onto the miso line of the ma ster. masters mosi pin is enabled. one half period later, valid ma ster data is transferred to the mosi line. now that both the master and slave data have been set, the sck master clock pin becomes low after one further half sck period. this means that data is captur ed on the falling edges and be propagated on the rising edges of the sck signal. in the case of a single word transmission, after all bits of the data word are transferred, the ssel line is returned to its idle high state one sck period after the last bit has been captured. however, in the case of continuous back-to- back transmissions, the ssel signal must be pulsed high between each data word transfe r. this is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the cpha bit is logic zero. theref ore the master device must raise the ssel pin of the slave device between each data transfer to enable the serial peripheral data write. on completion of the continuous transfer, the ssel pin is retur ned to its idle state one sck period after the last bit has been captured. a. single transfer with cpol=1 and cpha=0 b. continuous transfer with cpol=1 and cpha=0 fig 40. spi frame format with cpol = 1 and cpha = 0 (a) single and b) continuous transfer) sck ssel q msb lsb 4 to 16 bits miso mosi msb lsb sck ssel mosi miso 4 to 16 bits 4 to 16 bits msb lsb msb lsb q msb lsb q msb lsb
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 232 of 543 nxp semiconductors um10398 chapter 14: lpc111x/lpc11cxx spi0/1 with ssp 14.7.2.5 spi format with cpol = 1,cpha = 1 the transfer signal sequence for spi format with cpol = 1, cpha = 1 is shown in figure 41 , which covers both single and continuous transfers. in this configuration, during idle periods: ? the clk signal is forced high. ? ssel is forced high. ? the transmit mosi/miso pad is in high impedance. if the spi/ssp is enabled and there is valid da ta within the transmit fifo, the start of transmission is signified by the ssel master si gnal being driven low. masters mosi is enabled. after a further one half sck period, both master and slave data are enabled onto their respective transmission lines. at the same time, the sck is enabled with a falling edge transition. data is then captured on t he rising edges and propagated on the falling edges of the sck signal. after all bits have been transf erred, in the case of a singl e word transmission, the ssel line is returned to its idle high state one sck period after the last bit has been captured. for continuous back-to-back transmissions, th e ssel pins remains in its active low state, until the final bit of the last word has b een captured, and then returns to its idle state as described above. in general, for continuous back-to-ba ck transfers the ssel pin is held low between successive data words and termination is the same as that of the single word transfer. 14.7.3 semiconductor mi crowire fr ame format figure 42 shows the microwire frame format for a single frame. figure 43 shows the same format when back-to-back frames are transmitted. fig 41. spi frame format with cpol = 1 and cpha = 1 sck ssel mosi q 4 to 16 bits miso q msb msb lsb lsb
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 233 of 543 nxp semiconductors um10398 chapter 14: lpc111x/lpc11cxx spi0/1 with ssp microwire format is very sim ilar to spi format, ex cept that transmission is half-duplex instead of full-duplex, using a master-slave message passing technique. each serial transmission begins with an 8-bit control word that is transmitted from the spi/ssp to the off-chip slave device. during this transmission, no incoming data is received by the spi/ssp. after the message has been sent, the of f-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the required data. the returned data is 4 to 16 bit in length, making the total frame length anywhere from 13 to 25 bits. in this configuration, during idle periods: ? the sk signal is forced low. ? cs is forced high. ? the transmit data line so is arbitrarily forced low. a transmission is triggered by writing a control byte to t he transmit fifo.the falling edge of cs causes the value contained in the bottom entry of the transmit fifo to be transferred to the serial shift register of the transmit logic, and the msb of the 8-bit control frame to be shifted out onto the so pin. cs remains low for the duration of the frame transmission. the si pin remains tristated during this transmission. the off-chip serial slave device latches each control bit into its serial shifter on the rising edge of each sk. after the last bit is latched by the slave device, the control byte is decoded during a one clock wait-state, and the slave responds by transmitting data back to the spi/ssp. each bit is driven onto si line on the falling edge of sk. the spi/ssp in fig 42. microwire frame fo rmat (single transfer) fig 43. microwire frame format (continuous transfers) sk cs so 4 to 16 bits of output data si 8-bit control msb lsb 0 msb lsb sk cs so si msb lsb 4 to 16 bits of output data 8-bit control 4 to 16 bits of output data msb lsb 0 msb lsb lsb
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 234 of 543 nxp semiconductors um10398 chapter 14: lpc111x/lpc11cxx spi0/1 with ssp turn latches each bit on the rising edge of sk. at the end of the frame, for single transfers, the cs signal is pulled high one clock period after the last bit has been latched in the receive serial shifter, that causes the da ta to be transferred to the receive fifo. note: the off-chip slave device can tristate th e receive line either on the falling edge of sk after the lsb has been latched by the receiv e shiftier, or when the cs pin goes high. for continuous transfers, data transmission b egins and ends in the same manner as a single transfer. however, the cs line is continuously asserted (held low) and transmission of data occurs back to back. the control byte of the next frame follows directly after the lsb of the received data fr om the current frame. each of the received values is transferred from the receive shifter on the falling edge sk, after the lsb of the frame has been latched into the spi/ssp. 14.7.3.1 setup and hold time requirements on cs with respect to sk in microwire mode in the microwire mode, the spi/ssp slave samples the first bi t of receive data on the rising edge of sk after cs has gone low. masters that drive a free-running sk must ensure that the cs signal has sufficient setup and hold margins with respect to the rising edge of sk. figure 44 illustrates these set up and hold time requi rements. with respect to the sk rising edge on which the first bit of receive data is to be sampled by the spi/ssp slave, cs must have a setup of at least tw o times the period of sk on whic h the spi/ssp operates. with respect to the sk rising edge previous to this edge, cs must have a hold of at least one sk period. fig 44. microwire frame format setup and hold details sk cs si t hold = t sk t setup =2*t sk
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 235 of 543 15.1 how to read this chapter the i 2 c-bus block is identical for all lpc111x, lpc11d14, and lpc11cxx parts. the i2c-bus is interface is not available on part lpc1112fdh20/102. 15.2 basic configuration the i 2 c-bus interface is configured using the following registers: 1. pins: the i2c pin functions and the i2c mode are configured in the ioconfig register block ( section 7.4 , table 68 and ta b l e 6 9 ). 2. power and peripheral clock: in th e sysahbclkctrl register, set bit 5 ( ta b l e 2 1 ). 3. reset: before accessing the i2c block, ensure that the i2c_rst_n bit (bit 1) in the presetctrl register ( ta b l e 9 ) is set to 1. this de-asse rts the reset signal to the i2c block. 15.3 features ? standard i 2 c-compliant bus interfaces may be configured as master, slave, or master/slave. ? arbitration is handled between simultaneous ly transmitting masters without corruption of serial data on the bus. ? programmable clock allows adjustment of i 2 c transfer rates. ? data transfer is bidirectiona l between masters and slaves. ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ? serial clock synchronization is used as a handshake mechanism to suspend and resume serial transfer. ? supports fast-mode plus. ? optional recognition of up to four distinct slave addresses. ? monitor mode allows observing all i 2 c-bus traffic, regardless of slave address. ? i 2 c-bus can be used for test and diagnostic purposes. ? the i 2 c-bus contains a standard i 2 c-compliant bus interface with two pins. 15.4 applications interfaces to external i 2 c standard parts, such as serial rams, lcds, tone generators, other microcontrollers, etc. um10398 chapter 15: lpc111x/lpc11c xx i2c-bus controller rev. 12.1 ? 7 august 2013 user manual
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 236 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller 15.5 general description a typical i 2 c-bus configuration is shown in figure 45 . depending on the state of the direction bit (r/w), two types of data transfers are possible on the i 2 c-bus: ? data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the slave address. next follows a number of data bytes. the slave returns an acknowledge bit after each received byte. ? data transfer from a slave transmitter to a master receiver. the first byte (the slave address) is transmitted by the master. the slave then returns an acknowledge bit. next follows the data bytes transmitted by th e slave to the master. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a not acknowledge is returned. the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the i 2 c bus will not be released. the i 2 c interface is byte oriented and has four operating modes: master transmitter mode, master receiver mode, slave transmitter mode and slave receiver mode. the i 2 c interface complie s with the entire i 2 c specification, suppor ting the ability to turn power off to the arm cortex-m0 without in terfering with other devices on the same i 2 c-bus. 15.5.1 i 2 c fast-mode plus fast-mode plus supports a 1 mbit/sec transfer rate to communicate with the i 2 c-bus products which nxp semiconductors is now providing. fig 45. i 2 c-bus configuration other device with i 2 c interface pull-up resistor other device with i 2 c interface lpc11xx sda scl i 2 c bus scl sda pull-up resistor
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 237 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller 15.6 pin description the i 2 c-bus pins must be configured through the iocon_pio0_4 ( ta b l e 6 8 ) and iocon_pio0_5 ( table 69 ) registers for standard/ fast-mode or fast-mode plus. in fast-mode plus, rates above 400 khz and up to 1 mhz may be selected. the i 2 c-bus pins are open-drain outputs and fully compatible with the i 2 c-bus specification. 15.7 register description table 218. i 2 c-bus pin description pin type description sda input/output i 2 c serial data scl input/output i 2 c serial clock table 219. register overview: i 2 c (base address 0x4000 0000) name access address offset description reset value [1] i2c0conset r/w 0x000 i2c control set register. when a one is written to a bit of this register, the corresponding bit in the i 2 c control register is set. writing a zero has no effect on the corresponding bit in the i 2 c control register. 0x00 i2c0stat ro 0x004 i2c status register. during i 2 c operation, this register provides detailed status codes that allow software to determine the next action needed. 0xf8 i2c0dat r/w 0x008 i2c data register. during master or slave tr ansmit mode, data to be transmitted is written to this regist er. during master or slave receive mode, data that has been received ma y be read from this register. 0x00 i2c0adr0 r/w 0x00c i2c slave address register 0. contains the 7-bit slave address for operation of the i 2 c interface in slave mode, and is not used in master mode. the least significant bit dete rmines whether a slave responds to the general call address. 0x00 i2c0sclh r/w 0x010 sch duty cycle register high half word. determines the high time of the i 2 c clock. 0x04 i2c0scll r/w 0x014 scl duty cycle register low half word. determines the low time of the i 2 c clock. i2nscll and i2nsclh together determine the clock frequency generated by an i 2 c master and certain times used in slave mode. 0x04 i2c0conclr wo 0x018 i2c control clear register. when a one is written to a bit of this register, the corresponding bit in the i 2 c control register is cleared. writing a zero has no effect on the corresponding bit in the i 2 c control register. na i2c0mmctrl r/w 0x01c monitor mode control register. 0x00 i2c0adr1 r/w 0x020 i2c slave address register 1. contains the 7-bit slave address for operation of the i 2 c interface in slave mode, and is not used in master mode. the least significant bit dete rmines whether a slave responds to the general call address. 0x00 i2c0adr2 r/w 0x024 i2c slave address register 2. contains the 7-bit slave address for operation of the i 2 c interface in slave mode, and is not used in master mode. the least significant bit dete rmines whether a slave responds to the general call address. 0x00
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 238 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. 15.7.1 i 2 c control set register (i2c0conset - 0x4000 0000) the conset registers control setting of bits in the con register that controls operation of the i 2 c interface. writing a one to a bit of this register causes the corresponding bit in the i 2 c control register to be set. writing a zero has no effect. i2en i 2 c interface enable. when i2en is 1, the i 2 c interface is enabled. i2en can be cleared by writing 1 to the i2enc bit in the conclr register. when i2en is 0, the i 2 c interface is disabled. when i2en is 0, the sda and scl input signals are ignored, the i 2 c block is in the not addressed slave state, and the sto bit is forced to 0. i2c0adr3 r/w 0x028 i2c slave address register 3. contains the 7-bit slave address for operation of the i 2 c interface in slave mode, and is not used in master mode. the least significant bit dete rmines whether a slave responds to the general call address. 0x00 i2c0data_ buffer ro 0x02c data buffer register. the contents of the 8 msbs of the i2dat shift register will be transferred to the data_buffer automatically after every nine bits (8 bits of data plus ack or nack) has been received on the bus. 0x00 i2c0mask0 r/w 0x030 i2c slave address mask register 0 . this mask register is associated with i2adr0 to determine an address match. the mask register has no effect when comparing to the general call address (0000000). 0x00 i2c0mask1 r/w 0x034 i2c slave address mask register 1 . this mask register is associated with i2adr1 to determine an address match. the mask register has no effect when comparing to the general call address (0000000). 0x00 i2c0mask2 r/w 0x038 i2c slave address mask register 2 . this mask register is associated with i2adr2 to determine an address match. the mask register has no effect when comparing to the general call address (0000000). 0x00 i2c0mask3 r/w 0x03c i2c slave address mask register 3 . this mask register is associated with i2adr3 to determine an address match. the mask register has no effect when comparing to the general call address (0000000). 0x00 table 219. register overview: i 2 c (base address 0x4000 0000) ?continued name access address offset description reset value [1] table 220. i 2 c control set register (i2c0conset - address 0x4000 0000) bit description bit symbol description reset value 1:0 - reserved. user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na 2 aa assert acknowledge flag. 3si i 2 c interrupt flag. 0 4 sto stop flag. 0 5 sta start flag. 0 6i2en i 2 c interface enable. 0 31:7 - reserved. the value read fr om a reserved bit is not defined. -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 239 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller i2en should not be used to temporarily release the i 2 c-bus since, when i2en is reset, the i 2 c-bus status is lost. the aa flag should be used instead. sta is the start flag. setting this bit causes the i 2 c interface to enter master mode and transmit a start condition or transmit a repeated start cond ition if it is already in master mode. when sta is 1 and the i 2 c interface is not already in mast er mode, it enters master mode, checks the bus and generates a start condition if the bus is free. if the bus is not free, it waits for a stop condition (which will free the bus) and generates a start condition after a delay of a half clock period of the internal clock generator. if the i 2 c interface is already in master mode and data has been transmitted or received, it transmits a repeated start condition. sta may be set at any time, including when the i 2 c interface is in an addressed slave mode. sta can be cleared by writing 1 to the stac bit in the conclr register. when sta is 0, no start condition or repeated start condition will be generated. if sta and sto are both set, then a stop condition is transmitted on the i 2 c-bus if it the interface is in master mode, and transmit s a start condition thereafter. if the i 2 c interface is in slave mode, an internal stop condition is ge nerated, but is not transmitted on the bus. sto is the stop flag. setting this bit causes the i 2 c interface to transmit a stop condition in master mode, or recover from an error condition in slave mode. when sto is 1 in master mode, a stop condition is transmitted on the i 2 c-bus. when the bus detects the stop condition, sto is cleared automatically. in slave mode, setting this bit can recover from an error condit ion. in this case, no stop condition is transmitted to the bus. the hardware behaves as if a stop condition has been received and it switches to not addr essed slave receiver mode. the sto flag is cleared by hardware automatically. si is the i 2 c interrupt flag. this bit is set when the i 2 c state changes. however, entering state f8 does not set si since there is nothing for an interrupt service routine to do in that case. while si is set, the low period of the serial clock on the scl line is stretched, and the serial transfer is suspended. when scl is high, it is unaffected by the state of the si flag. si must be reset by software, by writing a 1 to the sic bit in the conclr register. aa is the assert acknowledge flag. when set to 1, an acknowledge (low level to sda) will be returned during the acknowledge cloc k pulse on the scl line on the following situations: 1. the address in the slave address register has been received. 2. the general call address has been received while the general call bit (gc) in the adr register is set. 3. a data byte has been received while the i 2 c is in the master receiver mode. 4. a data byte has been received while the i 2 c is in the addressed slave receiver mode
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 240 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller the aa bit can be cleared by writing 1 to the aac bit in the conclr register. when aa is 0, a not acknowledge (high level to sda) will be returned during the acknowledge clock pulse on the scl line on the following situations: 1. a data byte has been received while the i 2 c is in the master receiver mode. 2. a data byte has been received while the i 2 c is in the addressed slave receiver mode. 15.7.2 i 2 c status register (i2c0stat - 0x4000 0004) each i 2 c status register reflects the condition of the corresponding i 2 c interface. the i 2 c status register is read-only. the three least significant bits are always 0. ta ken as a byte, the status register contents represent a status code. there are 26 possible status codes. when the status code is 0xf8, there is no relevant info rmation available and the si bit is not set. all other 25 status codes correspond to defined i 2 c states. when any of these st ates entered, the si bit will be set. for a complete list of status codes, refer to tables from table 236 to table 241 . 15.7.3 i 2 c data register (i2c0dat - 0x4000 0008) this register contains the data to be trans mitted or the data just received. the cpu can read and write to this register only while it is not in the process of shifting a byte, when the si bit is set. data in dat register remains stable as long as the si bit is set. data in dat register is always shifted from right to left: the first bit to be transmitted is the msb (bit 7), and after a byte has been received, the first bi t of received data is located at the msb of the dat register. 15.7.4 i 2 c slave address register 0 (i2c0adr0- 0x4000 000c) this register is readable and writable and are only used when an i 2 c interface is set to slave mode. in master mode, this register has no effect. the lsb of the adr register is the general call bit. when this bit is set, the general call address (0x00) is recognized. if this register contains 0x00, the i 2 c will not acknowledge any address on the bus. all four registers (adr0 to adr3) will be cleared to this disabled state on reset. see also table 229 . table 221. i 2 c status register (i2c0stat - 0x4000 0004) bit description bit symbol description reset value 2:0 - these bits are unused and are always 0. 0 7:3 status these bits give the actual status information about the i 2 c interface. 0x1f 31:8 - reserved. the value read fr om a reserved bit is not defined. - table 222. i 2 c data register (i2c0dat - 0x4000 0008) bit description bit symbol description reset value 7:0 data this register holds data values that have been received or are to be transmitted. 0 31:8 - reserved. the value read from a reserved bit is not defined. -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 241 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller 15.7.5 i 2 c scl high and low duty cycle registers (i2c0sclh - 0x4000 0010 and i2c0scll- 0x4000 0014) 15.7.5.1 selecting the appropriate i 2 c data rate and duty cycle software must set values for the registers sclh and scll to select the appropriate data rate and duty cycle. sclh defines the num ber of i2c_pclk cycles for the scl high time, scll defines the number of i2c_pclk cycles for the scl low time. the frequency is determined by the following formula (i2c_pcl k is the frequency of the peripheral i2c clock): (4) the values for scll and sclh must ensure t hat the data rate is in the appropriate i 2 c data rate range. each register value must be greater than or equal to 4. table 226 gives some examples of i 2 c-bus rates based on i2c_pclk frequency and scll and sclh values. table 223. i 2 c slave address register 0 (i2c0adr0- 0x4000 000c) bit description bit symbol description reset value 0 gc general call enable bit. 0 7:1 address the i 2 c device address for slave mode. 0x00 31:8 - reserved. the value read from a reserved bit is not defined. - table 224. i 2 c scl high duty cycle register (i 2c0sclh - address 0x4000 0010) bit description bit symbol description reset value 15:0 sclh count for scl high time period selection. 0x0004 31:16 - reserved. the value read from a reserved bit is not defined. - table 225. i 2 c scl low duty cycle register (i2c0scll - 0x4000 0014) bit description bit symbol description reset value 15:0 scll count for scl low time period selection. 0x0004 31:16 - reserved. the value read from a reserved bit is not defined. - table 226. scll + sclh values for selected i 2 c clock values i 2 c mode i 2 c bit frequency i2c_pclk (mhz) 6 8 10 12 16 20 30 40 50 sclh + scll standard mode 100 khz 60 80 100 120 160 200 300 400 500 fast-mode 400 khz 15 20 25 30 40 50 75 100 125 fast-mode plus 1 mhz - 8 10 12 16 20 30 40 50 i 2 c bitfrequency i2cpclk sclh scll + ------------------------------------ =
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 242 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller scll and sclh values should not necessarily be the same. software can set different duty cycles on scl by setting these two registers. for example, the i 2 c-bus specification defines the scl low time and high time at di fferent values for a fast-mode and fast-mode plus i 2 c. 15.7.6 i 2 c control clear register (i2c0conclr - 0x4000 0018) the conclr register control clearing of bits in the con register that controls operation of the i 2 c interface. writing a one to a bit of this register causes the corresponding bit in the i 2 c control register to be cleared. writing a zero has no effect. aac is the assert acknowledge clear bit. writing a 1 to this bit clears the aa bit in the conset register. writing 0 has no effect. sic is the i 2 c interrupt clear bit. writing a 1 to this bit clears the si bit in the conset register. writing 0 has no effect. stac is the start flag clear bit. writing a 1 to this bit clears the sta bit in the conset register. writing 0 has no effect. i 2enc is the i 2 c interface disable bit. writing a 1 to this bit clears the i2en bit in the conset register. writing 0 has no effect. 15.7.7 i 2 c monitor mode control regist er (i2c0mmctrl - 0x4000 001c) this register controls the monitor mode which allows the i 2 c module to monitor traffic on the i 2 c bus without actually participating in traffic or interfering with the i 2 c bus. table 227. i 2 c control clear register (i2c0con clr - 0x4000 0018) bit description bit symbol description reset value 1:0 - reserved. user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na 2 aac assert acknowledge clear bit. 3sic i 2 c interrupt clear bit. 0 4 - reserved. user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na 5 stac start flag clear bit. 0 6i2enci 2 c interface disable bit. 0 7 - reserved. user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na 31:8 - reserved. the value read fr om a reserved bit is not defined. -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 243 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller [1] when the ena_scl bit is cleared and the i 2 c no longer has the ability to st all the bus, interrupt response time becomes important. to give the part more time to respond to an i 2 c interrupt under these conditions, a data _buffer register is used ( section 15.7.9 ) to hold received data for a full 9-bit word transmission time. remark: the ena_scl and match_all bits have no effect if the mm_ena is 0 (i.e. if the module is not in monitor mode). 15.7.7.1 interrupt in monitor mode all interrupts will occur as normal when the module is in monitor mode. this means that the first interrupt will o ccur when an address-match is detec ted (any address received if the match_all bit is set, otherwise an address matching one of the four address registers). subsequent to an address-match detection, in terrupts will be generate d after each data byte is received for a slave-write transfer, or after each byte that the module thinks it has transmitted for a slave-read tr ansfer. in this second case, th e data register will actually contain data transmitted by some other slave on the bus which was actually addressed by the master. table 228. i 2 c monitor mode control register (i2c0mmctrl - 0x4000 001c) bit description bit symbol value description reset value 0 mm_ena monitor mode enable. 0 0 monitor mode disabled. 1the i 2 c module will enter monitor mode. in this mode the sda output will be forced high. this will prevent the i 2 c module from outputting data of any kind (including ack) onto the i 2 c data bus. depending on the state of the ena_scl bit, the output may be also forced high, preventing the module from having control over the i 2 c clock line. 1 ena_scl scl output enable. 0 0 when this bit is cleared to 0, the scl output will be forced high when the module is in monitor mode. as described above, this will prevent the module from having any control over the i 2 c clock line. 1 when this bit is set, the i 2 c module may exercise the same control over the clock line that it would in normal operation. this means that, acting as a slave peripheral, the i 2 c module can stretch the clock line (hold it low) until it has had time to respond to an i 2 c interrupt. [1] 2 match_all select interrupt register match. 0 0 when this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. that is, the module will respond as a normal slave as far as address-recognition is concerned. 1 when this bit is set to 1 and the i 2 c is in monitor mode, an interrupt will be generated on any address received. this will enable the part to monitor all traffic on the bus. 31:3 - - reserved. the value read from reserved bits is not defined.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 244 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller following all of these interrupts, the processor may read the data register to see what was actually transmitted on the bus. 15.7.7.2 loss of arbitration in monitor mode in monitor mode, the i 2 c module will not be able to resp ond to a request for information by the bus master or issue an ack) . some other slave on the bus will respond instead. this will most probably result in a lost-arbitration state as far as our module is concerned. software should be aware of the fact that the module is in monitor mode and should not respond to any loss of arbitration state that is detected. in addition, hardware may be designed into the module to blo ck some/all loss of arbitration states from occurring if those state would either prevent a desired interr upt from occurring or cause an unwanted interrupt to occur. whether any such hardware will be added is still to be determined. 15.7.8 i 2 c slave address registers (i2c0adr[1 , 2, 3] - 0x4000 00[20, 24, 28]) these registers are readable and writable and are only used when an i 2 c interface is set to slave mode. in master mode, this register has no effect. the lsb of the adr register is the general call bit. when this bit is set, the general call address (0x00) is recognized. if these registers contain 0x00, the i 2 c will not acknowledge any address on the bus. all four registers will be clea red to this disabled state on reset (also see table 223 ). 15.7.9 i 2 c data buffer register (i 2c0data_buffer - 0x4000 002c) in monitor mode, the i 2 c module may lose the ability to st retch the clock (stall the bus) if the ena_scl bit is not set. this means that the processor will have a limited amount of time to read the contents of the data received on the bus. if the processor reads the dat shift register, as it ordinarily would, it co uld have only one bit-time to respond to the interrupt before the received data is overwritten by new data. to give the processor more time to respond, a new 8-bit, read-only data_buffer register will be added. the co ntents of the 8 msbs of the dat shift register will be transferred to the data_buffer automatically after every nine bits (8 bits of data plus ack or nack) has been received on the bus. this means that the processor will have nine bit transmission times to respond to the interrupt and read the data before it is overwritten. the processor will still have the ability to read th e dat register directly , as usual, and the behavior of dat will not be altered in any way. although the data_buffer register is primarily intended for use in monitor mode with the ena_scl bit = 0, it will be available fo r reading at any time under any mode of operation. table 229. i 2 c slave address registers (i2c0adr[1, 2, 3]- 0x4000 00[20, 24, 28]) bit description bit symbol description reset value 0 gc general call enable bit. 0 7:1 address the i 2 c device address for slave mode. 0x00 31:8 - reserved. the value read from a reserved bit is not defined. 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 245 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller 15.7.10 i 2 c mask registers (i2c0m ask[0, 1, 2, 3] - 0x 4000 00[30, 34, 38, 3c]) the four mask registers each contain seven acti ve bits (7:1). any bit in these registers which is set to 1 will cause an automatic compare on the corresponding bit of the received address when it is compared to t he addrn register associated with that mask register. in other words, bits in an addrn register which are mask ed are not taken into account in determining an address match. on reset, all mask register bits are cleared to 0. the mask register has no effect on comparison to the general call address (0000000). bits(31:8) and bit(0) of the mask registers are unused and should not be written to. these bits will always read back as zeros. when an address-match interrup t occurs, the processor will have to read the data register (dat) to determine what the received addr ess was that actually caused the match. 15.8 i 2 c operating modes in a given application, the i 2 c block may operate as a master, a slave, or both. in the slave mode, the i 2 c hardware looks for any one of its f our slave addresses and the general call address. if one of these addresses is detected, an interrupt is requested. if the processor wishes to become the bus master, the hardwar e waits until the bus is free before the master mode is entered so that a possible slave operation is not interrupted. if bus arbitration is lost in the master mode, the i 2 c block switches to the slave mode immediately and can detect its own slave address in the same serial transfer. 15.8.1 master transmitter mode in this mode data is transmitted from master to slave. before the master transmitter mode can be entered, the conset register must be initialized as shown in table 232 . i2en must be set to 1 to enable the i 2 c function. if the aa bit is 0, the i 2 c interface will not acknowledge any address when another device is master of the bus, so it can not enter slave mode. the sta, sto and si bits must be 0. the si bit is cleared by writing 1 to the sic bit in the conclr register. the sta bit should be cleared after writing the slave address. table 230. i 2 c data buffer register (i2c0data_buffer - 0x4000 002c) bit description bit symbol description reset value 7:0 data this register holds contents of the 8 msbs of the dat shift register. 0 31:8 - reserved. the value read from a reserved bit is not defined. 0 table 231. i 2 c mask registers (i2c0mask[ 0, 1, 2, 3] - 0x4000 00 [30, 34, 38, 3c]) bit description bit symbol description reset value 0 - reserved. user software should not write ones to reserved bits. this bit reads always back as 0. 0 7:1 mask mask bits. 0x00 31:8 - reserved. the value read from reserved bits is undefined. 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 246 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller the first byte transmitted contains the slave address of the receiving device (7 bits) and the data direction bit. in this mode the data direction bit (r/w) should be 0 which means write. the first byte transmitted contains the slave address and write bit. data is transmitted 8 bits at a time. after each byte is transmitted, an acknowledge bit is received. start and stop conditions are output to indi cate the beginning and the end of a serial transfer. the i 2 c interface will enter master transmitter mode when software sets the sta bit. the i 2 c logic will send the start condition as soon as the bus is free. after the start condition is transmitted, the si bit is set, and the status code in the stat register is 0x08. this status code is used to vector to a state service routine which will load the slave address and write bit to the dat register, and th en clear the si bit. si is cleared by writing a 1 to the sic bit in the conclr register. when the slave address and r/w bit have been transmitted and an acknowledgment bit has been received, the si bit is set again, and the possible status codes now are 0x18, 0x20, or 0x38 for the master mode, or 0x68, 0x78, or 0xb0 if the slave mode was enabled (by setting aa to 1). the appropriate actions to be taken for each of these status codes are shown in ta b l e 2 3 6 to table 241 . 15.8.2 master receiver mode in the master receiver mode, data is received from a slave transmitter. the transfer is initiated in the same way as in the master transmitter mode. when the start condition has been transmitted, the interrupt service routine must load the slave address and the data direction bit to the i 2 c data register (dat), and then cl ear the si bit. in this case, the data direction bit (r/w) should be 1 to indicate a read. when the slave address and data dire ction bit have been transmitted and an acknowledge bit has been received, the si bit is set, and the status register will show the status code. for master mode, the possible status codes are 0x40, 0x48, or 0x38. for slave mode, the possible status codes are 0x68, 0x78, or 0xb0. for details, refer to table 237 . table 232. i2c0conset and i2c1conset used to configure master mode bit 7 6 5 4 3 2 1 0 symbol - i2en sta sto si aa - - value- 10000- - fig 46. format in the ma ster transmitter mode a = acknowledge (sda low) a = not acknowledge (sda high) s = start condition p = stop condition s slave address rw=0 a data a a/a p from master to slave from slave to master data n bytes data transmitted
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 247 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller after a repeated start condition, i 2 c may switch to the master transmitter mode. 15.8.3 slave receiver mode in the slave receiver mode, data bytes are rece ived from a master tran smitter. to initialize the slave receiver mode, write any of the sl ave address registers (adr0-3) and write the i 2 c control set register (conset) as shown in table 233 . i2en must be set to 1 to enable the i 2 c function. aa bit must be set to 1 to acknowledge its own slave address or the general call address. the sta, sto and si bits are set to 0. after adr and conset are initialized, the i 2 c interface waits until it is addressed by its own address or general address followed by the data direction bit. if the direction bit is 0 (w), it enters slave receiver mode. if the direction bit is 1 (r), it enters slave transmitter mode. after the address and direction bit have been received, the si bit is set and a valid status code can be read from the status register (stat). refer to table 240 for the status codes and actions. fig 47. format of master receiver mode fig 48. a master receiver switches to mast er transmitter after sending repeated start data a = acknowledge (sda low) a = not acknowledge (sda high) s = start condition p = stop condition s slave address rw=1 a data p n bytes data received from master to slave from slave to master a a a = acknowledge (sda low) a = not acknowledge (sda high) s = start condition p = stop condition sla = slave address sr = repeated start condition data n bytes data transmitted from master to slave from slave to master a data a a sla r sr w p s sla data a a table 233. i2c0conset and i2c1conset used to configure slave mode bit 7 6 5 4 3 2 1 0 symbol - i2en sta sto si aa - - value- 10001- -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 248 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller 15.8.4 slave transmitter mode the first byte is received and handled as in the slave receiver mode. however, in this mode, the direction bit will be 1, indicating a read oper ation. serial data is transmitted via sda while the serial clock is input through scl. start and stop conditions are recognized as the beginning and end of a se rial transfer. in a given application, i 2 c may operate as a master and as a slave. in the slave mode, the i 2 c hardware looks for its own slave address and the general call address. if one of these addresses is detected, an interrupt is requested. when the microcontr ollers wishes to become the bus master, the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted. if bus arbi tration is lost in th e master mode, the i 2 c interface switches to the slave mode immediat ely and can detect its own slave address in the same serial transfer. 15.9 i 2 c implementation and operation figure 51 shows how the on-chip i 2 c-bus interface is implemented, and the following text describes the individual blocks. fig 49. format of slave receiver mode a a = acknowledge (sda low) a = not acknowledge (sda high) s = start condition p = stop condition sr = repeated start condition a a/a n bytes data received from master to slave from slave to master s slave address rw=0 data p/sr data fig 50. format of slave transmitter mode data a = acknowledge (sda low) a = not acknowledge (sda high) s = start condition p = stop condition a data n bytes data transmitted from master to slave from slave to master s slave address rw=1 a p a
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 249 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller 15.9.1 input filters and output stages input signals are synchronized with the internal clock, and spikes shorter than three clocks are filtered out. the output for i 2 c is a special pad designed to conform to the i 2 c specification. fig 51. i 2 c serial interface block diagram ap b bus status register i2cnstat control register and scl duty cyle registers i2cnconset, i2cnconclr, i2cnsclh, i2cnscll address registers mask and compare shift register i2cndat ack bit counter/ arbitration and monitor mode register i2cnmmctrl sync logic serial clock generator timing and control logic status decoder status bus interrupt pclk input filter output stage scl input filter output stage sda i2cnaddr0 to i2cnaddr3 mask registers i2cnmask0 to i2cnmask3 i2cndatabuffer matchall i2cnmmctrl[3] 8 8 8 16
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 250 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller 15.9.2 address regist ers, addr0 to addr3 these registers may be loaded with the 7-bit sl ave address (7 most significant bits) to which the i 2 c block will respond when programmed as a slave transmitter or receiver. the lsb (gc) is used to enable general call addre ss (0x00) recognition. when multiple slave addresses are enabled, the actual address receiv ed may be read from the dat register at the state where the own slave address has been received. 15.9.3 address mask regist ers, mask0 to mask3 the four mask registers each contain seven acti ve bits (7:1). any bit in these registers which is set to 1 will cause an automatic compare on the corresponding bit of the received address when it is compared to t he addrn register associated with that mask register. in other words, bits in an addrn register which are mask ed are not taken into account in determining an address match. when an address-match interrup t occurs, the processor will have to read the data register (dat) to determine what the received addr ess was that actually caused the match. 15.9.4 comparator the comparator compares the received 7-bit slave address with its own slave address (7 most significant bits in adr). it also compares the first received 8-bit byte with the general call address (0x00). if an equality is found, the appropriate status bits are set and an interrupt is requested. 15.9.5 shift register, dat this 8-bit register contains a byte of serial data to be transmitted or a byte which has just been received. data in dat is always shifted from right to left; the first bit to be transmitted is the msb (bit 7) and, after a byte has been received, the first bit of received data is located at the msb of dat. while data is being shifted out, data on the bus is simultaneously being shifted in; dat always contains the last byte present on the bus. thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in dat. 15.9.6 arbitration and synchronization logic in the master transmitter mode, the arbitratio n logic checks that every transmitted logic 1 actually appears as a logic 1 on the i 2 c-bus. if another device on the bus overrules a logic 1 and pulls the sda line low, arbitration is lost, and the i 2 c block immediately changes from master transmitter to slave receiver. the i 2 c block will continue to output clock pulses (on scl) until transmission of the current serial byte is complete. arbitration may also be lost in the master re ceiver mode. loss of arbitration in this mode can only occur while the i 2 c block is returning a not ackno wledge: (logic 1) to the bus. arbitration is lost when another device on th e bus pulls this signal low. since this can occur only at the end of a serial byte, the i 2 c block generates no further clock pulses. figure 52 shows the arbitration procedure.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 251 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller the synchronization logic will synchronize the serial clock generator with the clock pulses on the scl line from another device. if two or more master devices generate clock pulses, the mark duration is determ ined by the device that generat es the shortest marks, and the space duration is determined by the device that generates the longest spaces. figure 53 shows the synchronization procedure. a slave may stretch the space duration to slow down the bus master. the space duration may also be stretched for handshaking purposes. this can be done after each bit or after a complete byte transfer. the i 2 c block will stretch the scl space duration after a byte has been transmitted or received and the acknowle dge bit has been transferred. the serial interrupt flag (si) is set, and the stretching continues until the serial interrupt flag is cleared. 15.9.7 serial clock generator this programmable clock pulse generator provides the scl clock pulses when the i 2 c block is in the master transmitter or master re ceiver mode. it is sw itched off when the i 2 c block is in slave mode. the i 2 c output clock frequency and duty cycle is programmable (1) another device transmits serial data. (2) another device overrules a logic (dotted line) transmitted this i 2 c master by pulling the sda line low. arbitration is lost, and this i 2 c enters slave receiver mode. (3) this i 2 c is in slave receiver mode but still generates clock pulses until the current byte has been transmitted. this i 2 c will not generate clock pulses for the next byte. data on sda originates from the new master once it has won arbitration. fig 52. arbitration procedure (1) another device pulls the scl line low before this i 2 c has timed a complete high time. the other device effectively determines the (shorter) high period. (2) another device continues to pull the scl line low after this i 2 c has timed a complete low time and released scl. the i 2 c clock generator is forced to wait until scl goes high. the other device effectively determines the (longer) low period. (3) the scl line is released , and the cloc k generator begins timing the high time. fig 53. serial clock synchronization sda line scl line 12 34 8 9 ack (1) (2) (1) (3) sda line scl line (2) (1) (3) high period low period (1)
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 252 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller via the i 2 c clock control registers. see the description of the i2cscll and i2csclh registers for details. the output clock pulses have a duty cycle as programmed unless the bus is synchronizing with other scl clock sources as described above. 15.9.8 timing and control the timing and control logic generates the timing and control signals for serial byte handling. this logic block provides the shift pulses for dat, enables the comparator, generates and detects start and stop conditions, receives and transmits acknowledge bits, controls the master and slave modes, co ntains interrupt request logic, and monitors the i 2 c-bus status. 15.9.9 control register, conset and conclr the i 2 c control register contains bits used to control the following i 2 c block functions: start and restart of a serial transfer, termination of a serial transfer, bit rate, address recognition, and acknowledgment. the contents of the i 2 c control register may be read as conset. writing to conset will set bits in the i 2 c control register that correspond to ones in the value written. conversely, writing to conclr will clear bits in the i 2 c control register that correspond to ones in the value written. 15.9.10 status decoder and status register the status decoder takes all of the internal status bits and compresses them into a 5-bit code. this code is unique for each i 2 c-bus status. the 5-bit code may be used to generate vector addresses fo r fast processing of the various service routines. each service routine processes a particular bus status. there are 26 possible bus states if all four modes of the i 2 c block are used. the 5-bit status code is latched into the five most significant bits of the status register when th e serial interrupt flag is set (by hardware) and remains stable until the in terrupt flag is cleared by software. the three least significant bits of the status register are always zero. if the status code is used as a vector to service routines, then the routines are displaced by ei ght address locations. ei ght bytes of code is sufficient for most of the service routines (see the software example in this section). 15.10 details of i 2 c operating modes the four operating modes are: ? master transmitter ? master receiver ? slave receiver ? slave transmitter data transfers in each mode of operation are shown in figure 54 , figure 55 , figure 56 , figure 57 , and figure 58 . ta b l e 2 3 4 lists abbreviations used in these figures when describing the i 2 c operating modes.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 253 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller in figure 54 to figure 58 , circles are used to indicate when the serial interrupt flag is set. the numbers in the circles show the status code held in the stat register. at these points, a service routine must be executed to continue or complete the serial transfer. these service routines are not critical since th e serial transfer is suspended until the serial interrupt flag is cleared by software. when a serial interrupt routine is entered, the status code in stat is used to branch to the appropriate service routine. for each status co de, the required software action and details of the following serial transfer are given in tables from table 236 to table 242 . 15.10.1 master transmitter mode in the master transmitter mode, a number of data bytes are transmitted to a slave receiver (see figure 54 ). before the master transmitter mo de can be entered, i2con must be initialized as follows: the i 2 c rate must also be configured in the scll and sclh registers. i2en must be set to logic 1 to enable the i 2 c block. if the aa bit is reset, the i 2 c block will not acknowledge its own slave address or the general call address in the event of another device becoming master of the bus. in other words, if aa is reset, the i 2 c interface cannot enter slave mode. sta, sto, and si must be reset. table 234. abbreviations used to describe an i 2 c operation abbreviation explanation s start condition sla 7-bit slave address r read bit (high level at sda) w write bit (low level at sda) a acknowledge bit (low level at sda) a not acknowledge bit (high level at sda) data 8-bit data byte p stop condition table 235. i2c0conset used to initialize master transmitter mode bit 7 6 5 4 3 2 1 0 symbol - i2en sta sto si aa - - value- 1000x- -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 254 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller the master transmitter mode may now be entered by setting the sta bit. the i 2 c logic will now test the i 2 c-bus and generate a start condition as soon as the bus becomes free. when a start condition is transmitted, the seri al interrupt flag (si) is set, and the status code in the status register (stat) will be 0x08 . this status code is used by the interrupt service routine to enter the appropriate state service routine that lo ads dat with the slave address and the data direction bit (sla+w). the si bit in con must then be reset before the serial transfer can continue. when the slave address and the direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (si) is set again, and a number of status codes in stat are possible. there are 0x18, 0x20, or 0x38 for the master mode and also 0x68, 0x78, or 0xb0 if the slave mode was enabled (aa = logic 1). the appropriate action to be taken for eac h of these status codes is detailed in ta b l e 2 3 6 . after a repeated start condition (state 0x10). the i 2 c block may switch to the master receiver mode by loading dat with sla+r).
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 255 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller table 236. master transmitter mode status code (i2cstat ) status of the i 2 c-bus and hardware application software response next action taken by i 2 c hardware to/from dat to con sta sto si aa 0x08 a start condition has been transmitted. load sla+w; clear sta x 0 0 x sla+w will be transmitted; ack bit will be received. 0x10 a repeated start condition has been transmitted. load sla+w or x 0 0 x as above. load sla+r; clear sta x 0 0 x sla+r will be transmitted; the i 2 c block will be switched to mst/rec mode. 0x18 sla+w has been transmitted; ack has been received. load data byte or 0 0 0 x data byte will be transmitted; ack bit will be received. no dat action or 1 0 0 x repeated start will be transmitted. no dat action or 0 1 0 x stop condition will be transmitted; sto flag will be reset. no dat action 1 1 0 x stop condition followed by a start condition will be transmitted; sto flag will be reset. 0x20 sla+w has been transmitted; not ack has been received. load data byte or 0 0 0 x data byte will be transmitted; ack bit will be received. no dat action or 1 0 0 x repeated start will be transmitted. no dat action or 0 1 0 x stop condition will be transmitted; sto flag will be reset. no dat action 1 1 0 x stop condition followed by a start condition will be transmitted; sto flag will be reset. 0x28 data byte in dat has been transmitted; ack has been received. load data byte or 0 0 0 x data byte will be transmitted; ack bit will be received. no dat action or 1 0 0 x repeated start will be transmitted. no dat action or 0 1 0 x stop condition will be transmitted; sto flag will be reset. no dat action 1 1 0 x stop condition followed by a start condition will be transmitted; sto flag will be reset. 0x30 data byte in dat has been transmitted; not ack has been received. load data byte or 0 0 0 x data byte will be transmitted; ack bit will be received. no dat action or 1 0 0 x repeated start will be transmitted. no dat action or 0 1 0 x stop condition will be transmitted; sto flag will be reset. no dat action 1 1 0 x stop condition followed by a start condition will be transmitted; sto flag will be reset. 0x38 arbitration lost in sla+r/w or data bytes. no dat action or 0 0 0 x i 2 c-bus will be released; not addressed slave will be entered. no dat action 1 0 0 x a start condition will be transmitted when the bus becomes free.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 256 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller fig 54. format and states in the master transmitter mode data a r w sla s data a w sla to master receive mode, entry = mr mt to corresponding states in slave mode a or a a or a a other master continues other master continues a other master continues 20h 08h 18h 28h 30h 10h 68h 78h b0h 38h 38h arbitration lost in slave address or data byte not acknowledge received after a data byte not acknowledge received after the slave address next transfer started with a repeated start condition arbitration lost and addressed as slave successful transmission to a slave receiver from master to slave from slave to master any number of data bytes and their associated acknowledge bits n this number (contained in i2sta) corresponds to a defined state of the i 2 c bus a p p s p
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 257 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller 15.10.2 master receiver mode in the master receiver mode, a number of dat a bytes are received from a slave transmitter (see figure 55 ). the transfer is initialized as in the master transmitter mode. when the start condition has been transmitted, the in terrupt service routine must load dat with the 7-bit slave address and the data direction bit (sla+r). the si bit in con must then be cleared before the serial transfer can continue. when the slave address and the data direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (si) is set again, and a number of status codes in stat are possi ble. these are 0x40, 0x48, or 0x38 for the master mode and also 0x68, 0x78, or 0xb0 if the slave mode was enabled (aa = 1). the appropriate action to be taken for each of these status codes is detailed in table 237 . after a repeated start condition (state 0x10), the i 2 c block may switch to the master transmitter mode by loading dat with sla+w.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 258 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller table 237. master receiver mode status code (stat) status of the i 2 c-bus and hardware application software response next action taken by i 2 c hardware to/from dat to con sta sto si aa 0x08 a start condition has been transmitted. load sla+r x 0 0 x sla+r will be transmitted; ack bit will be received. 0x10 a repeated start condition has been transmitted. load sla+r or x 0 0 x as above. load sla+w x 0 0 x sla+w will be transmitted; the i 2 c block will be switched to mst/trx mode. 0x38 arbitration lost in not ack bit. no dat action or 0 0 0 x i 2 c-bus will be released; the i 2 c block will enter slave mode. no dat action 1 0 0 x a start condition will be transmitted when the bus becomes free. 0x40 sla+r has been transmitted; ack has been received. no dat action or 0 0 0 0 data byte will be received; not ack bit will be returned. no dat action 0 0 0 1 data byte will be received; ack bit will be returned. 0x48 sla+r has been transmitted; not ack has been received. no dat action or 1 0 0 x repeated start condition will be transmitted. no dat action or 0 1 0 x stop condition will be transmitted; sto flag will be reset. no dat action 1 1 0 x stop condition followed by a start condition will be transmitted; sto flag will be reset. 0x50 data byte has been received; ack has been returned. read data byte or 0 0 0 0 data byte will be received; not ack bit will be returned. read data byte 0 0 0 1 data byte will be received; ack bit will be returned. 0x58 data byte has been received; not ack has been returned. read data byte or 1 0 0 x repeated start condition will be transmitted. read data byte or 0 1 0 x stop condition will be transmitted; sto flag will be reset. read data byte 1 1 0 x stop condition followed by a start condition will be transmitted; sto flag will be reset.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 259 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller fig 55. format and states in the master receiver mode a to master transmit mode, entry = mt mr to corresponding states in slave mode a r sla s r sla s w a a or a a p other master continues other master continues a other master continues 48h 40h 58h 10h 68h 78h b0h 38h 38h arbitration lost in slave address or acknowledge bit not acknowledge received after the slave address next transfer started with a repeated start condition arbitration lost and addressed as slave successful transmission to a slave transmitter from master to slave from slave to master any number of data bytes and their associated acknowledge bits n this number (contained in i2sta) corresponds to a defined state of the i 2 c bus data a data 50h a data p 08h
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 260 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller 15.10.3 slave receiver mode in the slave receiver mode, a number of data bytes are received from a master transmitter (see figure 56 ). to initiate the slav e receiver mode, adr and con must be loaded as follows: the upper 7 bits are the address to which the i 2 c block will respond when addressed by a master. if the lsb (gc) is set, the i 2 c block will respond to the general call address (0x00); otherwise it ignore s the general call address. the i 2 c-bus rate settings do not affect the i 2 c block in the slave mode. i2en must be set to logic 1 to enable the i 2 c block. the aa bit must be set to enable the i 2 c block to acknowledge its own slave address or the gene ral call address. sta, sto, and si must be reset. when adr and con have been initialized, the i 2 c block waits until it is addressed by its own slave address followed by the data dire ction bit which must be 0 (w) for the i 2 c block to operate in the slave receiver mode. after its own slave address and the w bit have been received, the serial interrupt flag (s i) is set and a valid status code can be read from stat. this status code is used to vect or to a state service routine. the appropriate action to be taken for each of these status codes is detailed in table 240 . the slave receiver mode may also be entered if arbitration is lost while the i 2 c block is in the master mode (see status 0x68 and 0x78). if the aa bit is reset during a transfer, the i 2 c block will return a not acknowledge (logic 1) to sda after the next received data byte. while aa is reset, the i 2 c block does not respond to its own slave address or a general call address. however, the i 2 c-bus is still monitored and address recognition may be resumed at any time by setting aa. this means that the aa bit may be us ed to temporarily isolate the i 2 c block from the i 2 c-bus. table 238. i2c0adr and i2c1adr usage in slave receiver mode bit 7 6 5 4 3 2 1 0 symbol own slave 7-bit address gc table 239. i2c0conset and i2c1conset used to initialize slave receiver mode bit 7 6 5 4 3 2 1 0 symbol - i2en sta sto si aa - - value- 10001- -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 261 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller table 240. slave receiver mode status code (stat) status of the i 2 c-bus and hardware application software response next action taken by i 2 c hardware to/from dat to con sta sto si aa 0x60 own sla+w has been received; ack has been returned. no dat action or x 0 0 0 data byte will be received and not ack will be returned. no dat action x 0 0 1 data byte will be received and ack will be returned. 0x68 arbitration lost in sla+r/w as master; own sla+w has been received, ack returned. no dat action or x 0 0 0 data byte will be received and not ack will be returned. no dat action x 0 0 1 data byte will be received and ack will be returned. 0x70 general call address (0x00) has been received; ack has been returned. no dat action or x 0 0 0 data byte will be received and not ack will be returned. no dat action x 0 0 1 data byte will be received and ack will be returned. 0x78 arbitration lost in sla+r/w as master; general call address has been received, ack has been returned. no dat action or x 0 0 0 data byte will be received and not ack will be returned. no dat action x 0 0 1 data byte will be received and ack will be returned. 0x80 previously addressed with own slv address; data has been received; ack has been returned. read data byte or x 0 0 0 data byte will be received and not ack will be returned. read data byte x 0 0 1 data byte will be received and ack will be returned. 0x88 previously addressed with own sla; data byte has been received; not ack has been returned. read data byte or 0 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. read data byte or 0 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if adr[0] = logic 1. read data byte or 1 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free. read data byte 1 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if adr[0] = logic 1. a start condition will be transmitted when the bus becomes free. 0x90 previously addressed with general call; data byte has been received; ack has been returned. read data byte or x 0 0 0 data byte will be received and not ack will be returned. read data byte x 0 0 1 data byte will be received and ack will be returned.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 262 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller 0x98 previously addressed with general call; data byte has been received; not ack has been returned. read data byte or 0 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. read data byte or 0 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if adr[0] = logic 1. read data byte or 1 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free. read data byte 1 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if adr[0] = logic 1. a start condition will be transmitted when the bus becomes free. 0xa0 a stop condition or repeated start condition has been received while still addressed as slv/rec or slv/trx. no stdat action or 0 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. no stdat action or 0 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if adr[0] = logic 1. no stdat action or 1 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free. no stdat action 1 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if adr[0] = logic 1. a start condition will be transmitted when the bus becomes free. table 240. slave receiver mode ?continued status code (stat) status of the i 2 c-bus and hardware application software response next action taken by i 2 c hardware to/from dat to con sta sto si aa
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 263 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller fig 56. format and states in the slave receiver mode a a p or s a w sla s p or s a a 68h 60h 80h 88h reception of the general call address and one or more data bytes arbitration lost as master and addressed as slave last data byte received is not acknowledged arbitration lost as master and addressed as slave by general call reception of the own slave address and one or more data bytes all are acknowledged from master to slave from slave to master any number of data bytes and their associated acknowledge bits n this number (contained in i2sta) corresponds to a defined state of the i 2 c bus data a data 80h a0h last data byte is not acknowledged a p or s a 70h 90h data a data 90h a0h general call a 98h p or s a 78h data
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 264 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller 15.10.4 slave transmitter mode in the slave transmitter mode, a number of dat a bytes are transmitted to a master receiver (see figure 57 ). data transfer is initialized as in the slave receiver mode. when adr and con have been initialized, the i 2 c block waits until it is addressed by its own slave address followed by the data direction bit which must be 1 (r) for the i 2 c block to operate in the slave transmitter mode. after its own slave address and the r bit have been received, the serial interrupt flag (si) is set and a valid status code can be read from stat. this status code is used to vector to a state service routine, and the appropriate action to be taken for each of these status codes is detailed in table 241 . the slave transmitter mode may also be entered if arbitration is lost while the i 2 c block is in the master mode (see state 0xb0). if the aa bit is reset during a transfer, the i 2 c block will transmit the last byte of the transfer and enter state 0xc0 or 0xc8. the i 2 c block is switched to the not addressed slave mode and will ignore the master receiv er if it continues the transf er. thus the ma ster receiver receives all 1s as serial data. while aa is reset, the i 2 c block does not respond to its own slave address or a general call address. however, the i 2 c-bus is still m onitored, and address recognition may be resumed at any time by setting aa. this means that the aa bit may be used to temporarily isolate the i 2 c block from the i 2 c-bus.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 265 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller table 241. slave transmitter mode status code (stat) status of the i 2 c-bus and hardware application software response next action taken by i 2 c hardware to/from dat to con sta sto si aa 0xa8 own sla+r has been received; ack has been returned. load data byte or x 0 0 0 last data byte will be transmitted and ack bit will be received. load data byte x 0 0 1 data byte will be transmitted; ack will be received. 0xb0 arbitration lost in sla+r/w as master; own sla+r has been received, ack has been returned. load data byte or x 0 0 0 last data byte will be transmitted and ack bit will be received. load data byte x 0 0 1 data byte will be transmitted; ack bit will be received. 0xb8 data byte in dat has been transmitted; ack has been received. load data byte or x 0 0 0 last data byte will be transmitted and ack bit will be received. load data byte x 0 0 1 data byte will be transmitted; ack bit will be received. 0xc0 data byte in dat has been transmitted; not ack has been received. no dat action or 0 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. no dat action or 0 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if adr[0] = logic 1. no dat action or 1 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free. no dat action 1 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if adr[0] = logic 1. a start condition will be transmitted when the bus becomes free. 0xc8 last data byte in dat has been transmitted (aa = 0); ack has been received. no dat action or 0 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. no dat action or 0 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if adr[0] = logic 1. no dat action or 1 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free. no dat action 1 0 0 01 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if adr.0 = logic 1. a start condition will be transmitted when the bus becomes free.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 266 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller 15.10.5 miscellaneous states there are two stat codes that do not correspond to a defined i 2 c hardware state (see table 242 ). these are discussed below. 15.10.5.1 stat = 0xf8 this status code indicates that no relevant information is available because the serial interrupt flag, si, is not yet set. this occurs between other states and when the i 2 c block is not involved in a serial transfer. 15.10.5.2 stat = 0x00 this status code indicates that a bus error has occurred during an i 2 c serial transfer. a bus error is caused when a start or stop co ndition occurs at an ille gal position in the format frame. examples of such illegal positions are dur ing the serial transfer of an address byte, a data byte, or an acknowledge bit. a bus error may also be caused when external interference disturbs the internal i 2 c block signals. when a bus error occurs, si is set. to recover from a bus error, the sto flag must be set and si must be cleared. this fig 57. format and states in the slave transmitter mode data a a r sla s p or s a a b0h a8h c0h c8h last data byte transmitted. switched to not addressed slave (aa bit in i2con = ?0?) arbitration lost as master and addressed as slave reception of the own slave address and one or more data bytes all are acknowledged from master to slave from slave to master any number of data bytes and their associated acknowledge bits n this number (contained in i2sta) corresponds to a defined state of the i 2 c bus a data b8h all ones a data p or s
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 267 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller causes the i 2 c block to enter the not addressed slave mode (a defined state) and to clear the sto flag (no other bits in con are affected). the sda and scl lines are released (a stop condition is not transmitted). 15.10.6 some special cases the i 2 c hardware has facilities to handle the following spec ial cases that may occur during a serial transfer: ? simultaneous repeated start conditions from two masters ? data transfer after loss of arbitration ? forced access to the i 2 c-bus ? i 2 c-bus obstructed by a low level on scl or sda ? bus error 15.10.6.1 simultaneous repeated start conditions from two masters a repeated start condition may be generated in the master tran smitter or master receiver modes. a special case occurs if another master simultaneously generates a repeated start condition (see figure 58 ). until this occurs, arbi tration is not lost by either master since they were both transmitting the same data. if the i 2 c hardware detects a repeated start condition on the i 2 c-bus before generating a repeated start condition itself, it will rel ease the bus, and no interrupt request is generated. if another master frees the bu s by generating a stop condition, the i 2 c block will transmit a normal start condition (state 0x 08), and a retry of t he total serial data transfer can commence. table 242. miscellaneous states status code (stat) status of the i 2 c-bus and hardware application software response next action taken by i 2 c hardware to/from dat to con sta sto si aa 0xf8 no relevant state information available; si = 0. no dat action no con action wait or proceed current transfer. 0x00 bus error during mst or selected slave modes, due to an illegal start or stop condition. state 0x00 can also occur when interference causes the i 2 c block to enter an undefined state. no dat action 0 1 0 x only the internal hardware is affected in the mst or addressed slv modes. in all cases, the bus is released and the i 2 c block is switched to the not addressed slv mode. sto is reset.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 268 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller 15.10.6.2 data transfer after loss of arbitration arbitration may be lost in the master transmitter and master receiver modes (see figure 52 ). loss of arbitration is indicated by the following states in stat; 0x38, 0x68, 0x78, and 0xb0 (see figure 54 and figure 55 ). if the sta flag in con is set by the routines which service these states, then, if the bus is free again, a start condition (state 0x08) is transmitted without inte rvention by the cpu, and a retry of the total serial transfer can commence. 15.10.6.3 forced access to the i 2 c-bus in some applications, it may be possible for an uncontrolled source to cause a bus hang-up. in such situations, the problem may be caused by interference, temporary interruption of the bus or a temporary short-circuit between sda and scl. if an uncontrolled source generates a superfluous start or masks a stop condition, then the i 2 c-bus stays busy indefinitely. if the sta flag is set and bus access is not obtained within a reasonable amount of time, then a forced access to the i 2 c-bus is possible. this is achieved by setting the sto flag while the sta flag is still set. no stop condition is transmitted. the i 2 c hardware behaves as if a stop condition was received and is able to transmit a start condition. the sto flag is cleared by hardware (see figure 59 ). fig 58. simultaneous repeated start conditions from two masters sla aw sla s 18h 08h a data 28h 08h other master continues other master sends repeated start earlier s retry s p fig 59. forced access to a busy i 2 c-bus sda line scl line sta flag sto flag time limit start condition
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 269 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller 15.10.6.4 i 2 c-bus obstructed by a low level on scl or sda an i 2 c-bus hang-up can occur if either the sda or scl line is held low by any device on the bus. if the scl line is obstructed (pulled lo w) by a device on the bus, no further serial transfer is possible, and the problem must be resolved by t he device that is pulling the scl bus line low. typically, the sda line may be obstructed by another device on the bus that has become out of synchronization with the current bus master by either missing a clock, or by sensing a noise pulse as a clock. in this case, the pr oblem can be solved by transmitting additional clock pulses on the scl line (see figure 60 ). the i 2 c interface does not include a dedicated time-out timer to detect an obstru cted bus, but this can be implemented using another timer in the system. when detected, software can force clocks (up to 9 may be required) on scl until sda is released by the offending device. at that point, the slave may still be out of synchronization, so a star t should be generated to insure that all i 2 c peripherals are synchronized. 15.10.6.5 bus error a bus error occurs when a start or stop condition is detected at an illegal position in the format frame. examples of illegal positions are during the serial transfer of an address byte, a data bit, or an acknowledge bit. the i 2 c hardware only reacts to a bus error when it is involved in a serial transfer either as a master or an addressed slave. when a bus error is detected, the i 2 c block immediately switches to the not addressed slave mode, releases the sda and scl lines, sets the interrupt flag, and loads the status register with 0x00. this status code may be used to vector to a state service routine which either attempts the aborted serial transfer again or simply recovers from the error condition as shown in table 242 . 15.10.7 i 2 c state service routines this section provides examples of operations that must be performed by various i 2 c state service routines. this includes: ? initialization of the i 2 c block after a reset. ? i 2 c interrupt service ? the 26 state service routines providing support for all four i 2 c operating modes. (1) unsuccessful attempt to send a start condition. (2) sda line is released. (3) successful attempt to send a start condition. state 08h is entered. fig 60. recovering from a bus obstruction caused by a low level on sda sda line scl line (1) (2) (1) (3) sta flag start condition
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 270 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller 15.10.8 initialization in the initialization example, the i 2 c block is enabled for both master and slave modes. for each mode, a buffer is used for transmissi on and reception. the initialization routine performs the following functions: ? adr is loaded with the parts own slav e address and the general call bit (gc) ? the i 2 c interrupt enable and interrupt priority bits are set ? the slave mode is enabled by simultaneous ly setting the i2en and aa bits in con and the serial clock frequency (for master mo des) is defined by is defined by loading the sclh and scll registers . the master routines must be started in the main program. the i 2 c hardware now begins checking the i 2 c-bus for its own slave address and general call. if the general call or the own slave add ress is detected, an interrupt is requested and stat is loaded with the appropriate state information. 15.10.9 i 2 c interrupt service when the i 2 c interrupt is entered, stat contains a status code which identifies one of the 26 state services to be executed. 15.10.10 the state service routines each state routine is part of the i 2 c interrupt routine and handles one of the 26 states. 15.10.11 adapting state servi ces to an application the state service examples show the typical actions that must be performed in response to the 26 i 2 c state codes. if one or more of the four i 2 c operating modes are not used, the associated state services can be omitted, as long as care is taken that the those states can never occur. in an application, it may be desirable to implement some kind of time-out during i 2 c operations, in order to trap an inoper ative bus or a lost service routine. 15.11 software example 15.11.1 initialization routine example to initialize i 2 c interface as a slave and/or master. 1. load adr with own slave address, enab le general call rec ognition if needed. 2. enable i 2 c interrupt. 3. write 0x44 to conset to set the i2en and aa bits, enabling slave functions. for master only functions, write 0x40 to conset. 15.11.2 start master transmit function begin a master transmit operation by settin g up the buffer, pointer, and data count, then initiating a start. 1. initialize master data counter.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 271 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller 2. set up the slave address to which data will be transmitted, and add the write bit. 3. write 0x20 to conset to set the sta bit. 4. set up data to be transmitted in master transmit buffer. 5. initialize the master data counter to ma tch the length of the message being sent. 6. exit 15.11.3 start master receive function begin a master receive operation by setting up the buffer, pointer, and data count, then initiating a start. 1. initialize master data counter. 2. set up the slave address to which data will be transmitted, and add the read bit. 3. write 0x20 to conset to set the sta bit. 4. set up the master receive buffer. 5. initialize the master data counter to match the length of the message to be received. 6. exit 15.11.4 i 2 c interrupt routine determine the i 2 c state and which state routin e will be used to handle it. 1. read the i 2 c status from sta. 2. use the status value to branch to one of 26 possible state routines. 15.11.5 non mode specific states 15.11.5.1 state: 0x00 bus error. enter not addressed slave mode and release bus. 1. write 0x14 to conset to set the sto and aa bits. 2. write 0x08 to conclr to clear the si flag. 3. exit 15.11.5.2 master states state 08 and state 10 are for both master transmit and master receive modes. the r/w bit decides whether the next state is within master transmit mode or master receive mode. 15.11.5.3 state: 0x08 a start condition has been transmitted. the slave address + r/w bit will be transmitted, an ack bit will be received. 1. write slave address with r/w bit to dat. 2. write 0x04 to conset to set the aa bit. 3. write 0x08 to conclr to clear the si flag. 4. set up master transmit mode data buffer.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 272 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller 5. set up master receive mode data buffer. 6. initialize master data counter. 7. exit 15.11.5.4 state: 0x10 a repeated start condition ha s been transmitted. the slav e address + r/w bit will be transmitted, an ack bit will be received. 1. write slave address with r/w bit to dat. 2. write 0x04 to conset to set the aa bit. 3. write 0x08 to conclr to clear the si flag. 4. set up master transmit mode data buffer. 5. set up master receive mode data buffer. 6. initialize master data counter. 7. exit 15.11.6 master transmitter states 15.11.6.1 state: 0x18 previous state was state 8 or state 10, sl ave address + write has been transmitted, ack has been received. the first data byte will be transmitted, an ack bit will be received. 1. load dat with first data byte from master transmit buffer. 2. write 0x04 to conset to set the aa bit. 3. write 0x08 to conclr to clear the si flag. 4. increment master transmit buffer pointer. 5. exit 15.11.6.2 state: 0x20 slave address + write has been transmitted, not ack has been received. a stop condition will be transmitted. 1. write 0x14 to conset to set the sto and aa bits. 2. write 0x08 to conclr to clear the si flag. 3. exit 15.11.6.3 state: 0x28 data has been transmitted, ack has been received. if the transmitted data was the last data byte then transmit a stop conditio n, otherwise transmit the next data byte. 1. decrement the master data counter, skip to step 5 if not the last data byte. 2. write 0x14 to conset to set the sto and aa bits. 3. write 0x08 to conclr to clear the si flag. 4. exit 5. load dat with next data byte from master transmit buffer.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 273 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller 6. write 0x04 to conset to set the aa bit. 7. write 0x08 to conclr to clear the si flag. 8. increment master transmit buffer pointer 9. exit 15.11.6.4 state: 0x30 data has been transmitted, not ack received. a stop c ondition will be transmitted. 1. write 0x14 to conset to set the sto and aa bits. 2. write 0x08 to conclr to clear the si flag. 3. exit 15.11.6.5 state: 0x38 arbitration has been lost during slave address + write or data. the bus has been released and not addr essed slave mode is entered. a new start condition will be transmitted when the bus is free again. 1. write 0x24 to conset to set the sta and aa bits. 2. write 0x08 to conclr to clear the si flag. 3. exit 15.11.7 master receive states 15.11.7.1 state: 0x40 previous state was state 08 or state 10. slave address + read has been transmitted, ack has been received. data will be received and ack returned. 1. write 0x04 to conset to set the aa bit. 2. write 0x08 to conclr to clear the si flag. 3. exit 15.11.7.2 state: 0x48 slave address + read has been transmitt ed, not ack has been received. a stop condition will be transmitted. 1. write 0x14 to conset to set the sto and aa bits. 2. write 0x08 to conclr to clear the si flag. 3. exit 15.11.7.3 state: 0x50 data has been received, ack has been returned . data will be read fr om dat. additional data will be received. if this is the last data byte then no t ack will be returned, otherwise ack will be returned. 1. read data byte from dat into master receive buffer. 2. decrement the master data counter, skip to step 5 if not the last data byte. 3. write 0x0c to conclr to clear the si flag and the aa bit.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 274 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller 4. exit 5. write 0x04 to conset to set the aa bit. 6. write 0x08 to conclr to clear the si flag. 7. increment master receive buffer pointer 8. exit 15.11.7.4 state: 0x58 data has been received, not ack has been returned. data will be read from dat. a stop condition will be transmitted. 1. read data byte from dat into master receive buffer. 2. write 0x14 to conset to set the sto and aa bits. 3. write 0x08 to conclr to clear the si flag. 4. exit 15.11.8 slave receiver states 15.11.8.1 state: 0x60 own slave address + write has been received, ack has been returned. data will be received and ack returned. 1. write 0x04 to conset to set the aa bit. 2. write 0x08 to conclr to clear the si flag. 3. set up slave receive mode data buffer. 4. initialize slave data counter. 5. exit 15.11.8.2 state: 0x68 arbitration has been lost in slave address and r/w bit as bus master. own slave address + write has been received, ac k has been returned. data will be received and ack will be returned. sta is set to restart master mode after the bus is free again. 1. write 0x24 to conset to set the sta and aa bits. 2. write 0x08 to conclr to clear the si flag. 3. set up slave receive mode data buffer. 4. initialize slave data counter. 5. exit. 15.11.8.3 state: 0x70 general call has been received, ack has bee n returned. data will be received and ack returned. 1. write 0x04 to conset to set the aa bit. 2. write 0x08 to conclr to clear the si flag. 3. set up slave receive mode data buffer.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 275 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller 4. initialize slave data counter. 5. exit 15.11.8.4 state: 0x78 arbitration has been lost in slave address + r/w bit as bus master. general call has been received and ack has been returned. data will be received and ack returned. sta is set to restart master mode af ter the bus is free again. 1. write 0x24 to conset to set the sta and aa bits. 2. write 0x08 to conclr to clear the si flag. 3. set up slave receive mode data buffer. 4. initialize slave data counter. 5. exit 15.11.8.5 state: 0x80 previously addressed with ow n slave address. data has been received and ack has been returned. additional data will be read. 1. read data byte from dat into the slave receive buffer. 2. decrement the slave data counter, skip to step 5 if not the last data byte. 3. write 0x0c to conclr to clear the si flag and the aa bit. 4. exit. 5. write 0x04 to conset to set the aa bit. 6. write 0x08 to conclr to clear the si flag. 7. increment slave receive buffer pointer. 8. exit 15.11.8.6 state: 0x88 previously addressed with ow n slave address. data has been received and not ack has been returned. received data will not be saved. not addressed slave mode is entered. 1. write 0x04 to conset to set the aa bit. 2. write 0x08 to conclr to clear the si flag. 3. exit 15.11.8.7 state: 0x90 previously addressed with general call. data has been received, ack has been returned. received data will be saved. only the first data byte will be received with ack. additional data will be received with not ack. 1. read data byte from dat into the slave receive buffer. 2. write 0x0c to conclr to clear the si flag and the aa bit. 3. exit
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 276 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller 15.11.8.8 state: 0x98 previously addressed with general call. da ta has been received, not ack has been returned. received data will not be saved. no t addressed slave mode is entered. 1. write 0x04 to conset to set the aa bit. 2. write 0x08 to conclr to clear the si flag. 3. exit 15.11.8.9 state: 0xa0 a stop condition or repeated start has been receiv ed, while still addressed as a slave. data will not be saved. not addressed slave mode is entered. 1. write 0x04 to conset to set the aa bit. 2. write 0x08 to conclr to clear the si flag. 3. exit 15.11.9 slave tran smitter states 15.11.9.1 state: 0xa8 own slave address + read has been rece ived, ack has been returned. data will be transmitted, ack bit will be received. 1. load dat from slave transmit buffer with first data byte. 2. write 0x04 to conset to set the aa bit. 3. write 0x08 to conclr to clear the si flag. 4. set up slave transmit mode data buffer. 5. increment slave transmit buffer pointer. 6. exit 15.11.9.2 state: 0xb0 arbitration lost in slave address and r/w bit as bus master. own slave address + read has been received, ack has been returned. data will be tran smitted, ack bit will be received. sta is set to restart master mode after the bus is free again. 1. load dat from slave transmit buffer with first data byte. 2. write 0x24 to conset to set the sta and aa bits. 3. write 0x08 to conclr to clear the si flag. 4. set up slave transmit mode data buffer. 5. increment slave transmit buffer pointer. 6. exit 15.11.9.3 state: 0xb8 data has been transmitted, ac k has been received. data will be transmitted, ack bit will be received. 1. load dat from slave transmit buffer with data byte.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 277 of 543 nxp semiconductors um10398 chapter 15: lpc111x/lpc11cxx i2c-bus controller 2. write 0x04 to conset to set the aa bit. 3. write 0x08 to conclr to clear the si flag. 4. increment slave transmit buffer pointer. 5. exit 15.11.9.4 state: 0xc0 data has been transmitted, not ack has bee n received. not addressed slave mode is entered. 1. write 0x04 to conset to set the aa bit. 2. write 0x08 to conclr to clear the si flag. 3. exit. 15.11.9.5 state: 0xc8 the last data byte has been transmitted, ack has been received. not addressed slave mode is entered. 1. write 0x04 to conset to set the aa bit. 2. write 0x08 to conclr to clear the si flag. 3. exit
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 278 of 543 16.1 how to read this chapter the c_can block is available in lpc11cxx parts only (lpc11c00 series). the lpc11c22 and lpc11c24 parts include an on-chip, high-speed transceiver. for these parts, the can_rxd and can_txd signal s are connected internally to the on-chip transceiver, and the transceiver signals are pinned out (see table 244 ). 16.2 basic configuration the c_can is configured using the following registers: 1. power: in the sysahbclkct rl register, set bit 17 ( ta b l e 2 1 ). 2. clocking: for an accurate peripheral clock to the c_can block, select the system oscillator either as the main clock ( ta b l e 1 8 ) or as input to the system pll ( ta b l e 1 6 ). do not select the irc if c_can baud rates above 100 kbit/s are required. 3. reset: before accessing the c_can block, ensure that the can_rst_n bit (bit 3) in the presetctrl register ( ta b l e 9 ) is set to 1. this de-asserts the reset signal to the c_can block. the peripheral clock to the c_can (the c_ can system clock) and to the programmable c_can clock divider (see table 275 ) is provided by the system clock (see ta b l e 2 1 ). this clock can be disabled throug h bit 17 in the sysahbclkctrl register for power savings. remark: if c_can baudrates above 100 kbit/s are required, the system oscillator must be selected as the clock source for the system clock. for lower baudrates, the irc may also be used as clock source. 16.3 features ? conforms to protocol version 2.0 parts a and b. ? supports bit rate of up to 1 mbit/s. ? supports 32 message objects. ? each message object has its own identifier mask. ? provides programmable fifo mode (concatenation of message objects). ? provides maskable interrupts. ? supports disabled automatic retransmission (dar) mode for time-triggered can applications. ? provides programmable loop-back mode for self-test operation. um10398 chapter 16: lpc111x/lpc11cxx c_can controller rev. 12.1 ? 7 august 2013 user manual
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 279 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller 16.4 general description controller area network (can) is the definition of a high performance communication protocol for serial data communication. the c_ can controller is designed to provide a full implementation of the can protocol accordin g to the can specification version 2.0b. the c_can controller allows to build powerful local networks with low-cost multiplex wiring by supporting distributed real-time control with a very high level of security. the can controller consists of a can core, message ram, a message handler, control registers, and the apb interface. for communication on a can network, indivi dual message objects are configured. the message objects and identifier masks for acceptance filtering of received messages are stored in the message ram. all functions concerning the handling of messages are implemented in the message handler. those functions are the acceptance filtering, the transfer of messages between the can core and the message ram, and the handling of transmission requests as well as the generation of the module interrupt. the register set of the can controller can be accessed directly by an external cpu via the apb bus. these registers are used to control/configure the can core and the message handler and to access the message ram. fig 61. c_can block diagram can core message ram register interface message handler apb bus apb interface can_txd can_rxd c_can
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 280 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller 16.5 pin description 16.6 register description the c_can registers are organized as 32-bit wide registers. the two sets of interface registers (if1 and if2) control the cpu access to the message ram. they buffer the data to be transferr ed to and from the ram, avoiding conflicts between cpu accesses and mess age reception/transmission. table 243. can pin description (lpc11c12/c14) pin type description can_txd o c_can transmit output can_rxd i c_can receive input table 244. can pin description (lpc11c22/c24) pin type description canl i/o low-level can bus line. canh i/o high-level can bus line. stb i silent mode control input for can transceiver (low = normal mode, high = silent mode). vdd_can - supply voltage for i/o level of can transceiver. v cc - supply voltage for can transceiver. gnd - ground for can transceiver. table 245. register overview : ccan (base address 0x4005 0000) name access address offset description reset value cancntl r/w 0x000 can control 0x0001 canstat r/w 0x004 status register 0x0000 canec ro 0x008 error counter 0x0000 canbt r/w 0x00c bit timing register 0x2301 canint ro 0x010 interrupt register 0x0000 cantest r/w 0x014 test register - canbrpe r/w 0x018 baud rate prescaler extension register 0x0000 - - 0x01c reserved - canif1_cmdreq r/w 0x020 message interface 1 command request 0x0001 canif1_cmdmsk_w r/w 0x024 message interface 1 command mask (write direction) 0x0000 canif1_cmdmsk_r r/w 0x024 message interface 1 command mask (read direction) 0x0000 canif1_msk1 r/w 0x028 message interface 1 mask 1 0xffff canif1_msk2 r/w 0x02c message interface 1 mask 2 0xffff canif1_arb1 r/w 0x030 message interface 1 arbitration 1 0x0000 canif1_arb2 r/w 0x034 message interface 1 arbitration 2 0x0000 canif1_mctrl r/w 0x038 message interface 1 message control 0x0000
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 281 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller canif1_da1 r/w 0x03c message interface 1 data a1 0x0000 canif1_da2 r/w 0x040 message interface 1 data a2 0x0000 canif1_db1 r/w 0x044 message interface 1 data b1 0x0000 canif1_db2 r/w 0x048 message interface 1 data b2 0x0000 -- 0 x 0 4 c - 0x07c reserved - canif2_cmdreq r/w 0x080 message interface 2 command request 0x0001 canif2_cmdmsk_w r/w 0x084 message interface 2 command mask (write direction) 0x0000 canif2_cmdmsk_r r/w 0x084 message interface 2 command mask (read direction) 0x0000 canif2_msk1 r/w 0x088 message interface 2 mask 1 0xffff canif2_msk2 r/w 0x08c message interface 2 mask 2 0xffff canif2_arb1 r/w 0x090 message interface 2 arbitration 1 0x0000 canif2_arb2 r/w 0x094 message interface 2 arbitration 2 0x0000 canif2_mctrl r/w 0x098 message interface 2 message control 0x0000 canif2_da1 r/w 0x09c message interface 2 data a1 0x0000 canif2_da2 r/w 0x0a0 message interface 2 data a2 0x0000 canif2_db1 r/w 0x0a4 message interface 2 data b1 0x0000 canif2_db2 r/w 0x0a8 message interface 2 data b2 0x0000 -- 0 x 0 a c - 0x0fc reserved - cantxreq1 ro 0x100 transmission request 1 0x0000 cantxreq2 ro 0x104 transmission request 2 0x0000 - - 0x108 - 0x11c reserved - cannd1 ro 0x120 new data 1 0x0000 cannd2 ro 0x124 new data 2 0x0000 - - 0x128 - 0x13c reserved - canir1 ro 0x140 interrupt pending 1 0x0000 canir2 ro 0x144 interrupt pending 2 0x0000 - - 0x148 - 0x15c reserved - canmsgv1 ro 0x160 message valid 1 0x0000 canmsgv2 ro 0x164 message valid 2 0x0000 - - 0x168 - 0x17c reserved - canclkdiv r/w 0x180 can clock divider register 0x0001 table 245. register overview : ccan (base address 0x4005 0000) name access address offset description reset value
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 282 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller 16.6.1 can protocol registers 16.6.1.1 can control register the reset value 0x0001 of the canctl register enables initialization by software (init = 1). the c_can does not influence the can bus until the cpu resets the init bit to 0. table 246. can control regi sters (cancntl, address 0x4 005 0000) bit description bit symbol value description reset value access 0 init initialization 1 r/w 0 normal operation. 1 started. initialization is started. on reset, software needs to initialize the can controller. 1 ie module interrupt enable 0 r/w 0 disable can interrupts. the interrupt line is always high. 1 enable can interrupts. the interrupt line is set to low and remains low until all pending interrupts are cleared. 2 sie status change interrupt enable 0 r/w 0 disable status change interrupts. no status change interrupt will be generated. 1 enable status change interrupts. a status change interrupt will be generated when a message transfer is su ccessfully completed or a can bus error is detected. 3 eie error interrupt enable 0 r/w 0 disable error inte rrupt. no error status interrupt will be generated. 1 enable error interrupt. a change in the bits boff or ewarn in the canstat registers will generate an interrupt. 4 - - reserved 0 - 5 dar disable automatic retransmission 0 r/w 0 enabled. automatic retransmission of disturbed messages enabled. 1 disabled. automatic retransmission disabled. 6 cce configuration change enable 0 r/w 0 no write access. the cpu has no write access to the bit timing register. 1 write access. the cpu has write access to the canbt register while the init bit is one. 7 test test mode enable 0 r/w 0 normal operation. 1 test mode. 31:8 - reserved - -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 283 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller remark: the busoff recovery sequence (see can specification rev. 2.0 ) cannot be shortened by setting or resetting the init bit. if the device goes into busoff st ate, it will set init, stopping all bus activities. once init has been cleared by the cpu, the device will then wait for 129 occurr ences of bus idle (129 ? 11 consecutive high/recessive bits) before resuming normal operations. at the end of the busoff recovery sequence, the error management co unters will be reset. during the waiting time afte r the resetting of init, each time a sequence of 11 high/recessive bits has been monitored, a bit0 error code is written to the status register canstat, enabling the cpu to monitor the proceeding of the busoff recovery sequence and to determine whether the can bus is stuck at low/dominan t or continuously disturbed. 16.6.1.2 can status register a status interrupt is generated by bits boff, ewarn, rxok, txok, or lec. boff and ewarn generate an error interrupt, and rxok, txok, and lec generate a status change interrupt if eie and sie respectively are set to enabled in the canctrl register. a change of bit epass and a write to rxok , txok, or lec will never create a status interrupt. reading the canstat register will clear the status interrupt valu e (0x8000) in the canint register.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 284 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller table 247. can status register (cansta t, address 0x4005 0004) bit description bit symbol value description reset value access 2:0 lec last error code type of the last error to occur on the can bus.the lec field holds a code which indicates the type of the last error to occur on the can bus. this field will be cleared to 0 when a message has been transferred (reception or transmission) without error. the unused code 111 may be written by the cpu to check for updates. 000 r/w 0x0 no error . 0x1 stuff error . more than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 0x2 form error . a fixed format part of a received frame has the wrong format. 0x3 ackerror . the message this can core transmitted was not acknowledged. 0x4 bit1error . during the transmission of a message (with the exception of the arbitration field), the device wanted to send a high/recessive level (bit of logical value 1), but the monitored bus value was low/dominant. 0x5 bit0error . during the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a low/dominant level (data or identifie r bit logical value 0), but the monitored bus value was high/recessive. during busoff recovery this status is set each time a sequence of 11 high/recessive bits has been monitored. this enables the cpu to monitor the proceeding of the busoff recovery sequence (indicating the bus is not stuck at low/dominant or conti nuously disturbed). 0x6 crcerror . the crc checksum was incorrect in the message received. 0x7 unused. no can bus event was detected (written by the cpu). 3 txok transmitted a message successfully this bit must be reset by the cpu. it is never reset by the can controller. 0r/w 0 no transmit. since this bit was last reset by the cpu, no message has been successfully transmitted. 1 successful transmit. since this bi t was last reset by the cpu, a message has been successfully transmitted (error free and acknowledged by at least one other node). 4 rxok received a message successfully this bit must be reset by the cpu. it is never reset by the can controller. 0r/w 0 no receive. since this bit was last reset by the cpu, no message has been successfully received. 1 successful receive.since this bit wa s last set to zero by the cpu, a message has been successfully received independent of the result of acceptance filtering.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 285 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller 16.6.1.3 can error counter 5 epass error passive 0 ro 0 active. the can controller is in the error active state. 1 passive. the can controller is in the error passive state as defined in the can 2.0 specification . 6 ewarn warning status 0 ro 0 below limit. both error counters are below the error warning limit of 96. 1 at limit. at least one of the error counters in the ec has reached the error warning limit of 96. 7 boff busoff status 0 ro 0 the can module is not in busoff. 1 the can controller is in busoff state. 31:8 - - reserved table 247. can status register (cansta t, address 0x4005 0004) bit description ?continued bit symbol value description reset value access table 248. can error counter (canec, address 0x4005 0008) bit description bit symbol value description reset value access 7:0 tec7_0 transmit error counter current value of the transmit error counter (maximum value 255) 0ro 14:8 rec6_0 receive error counter current value of the receive error counter (maximum value 127). -ro 15 rp receive error passive - ro 0 below error level. the receive counter is below the error passive level. 1 at error level. the receive counter has reached the error passive level as defined in the can2.0 specification . 31:16 - - reserved - -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 286 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller 16.6.1.4 can bit timing register [1] hardware interprets the value programmed into these bits as the bit value ? 1. for example, with a lpc11cx system clock set to of 8 mhz, the reset value of 0x2301 configures the c_can for a bit rate of 500 kbit/s. the registers are only writable if a configuration change is enabled in canctrl and the controller is initialized by software (bits cc e and init in the can control register are set). for details on bit timing, see section 16.7.5 and the bosch c_can user?s manual, revision 1.2 . baud rate prescaler the bit time quanta t q are determined by the brp value: t q = brp / f sys (f sys is the lpc11cx system clock to the c_can block). time segments 1 and 2 time segments tseg1 and tseg2 determine the number of time quanta per bit time and the location of the sample point: t tseg1/2 = t q ? (tseg1/2 + 1) synchronization jump width to compensate for phase shifts between clock oscillators of different bus controllers, any bus controller must re-synch ronize on any relevant signal edge of the current transmission. the synchro nization jump width t sjw defines the maximum number of clock cycles a certain bit period may be shortened or lengthened by one re-synchronization: t sjw = t q ? (sjw + 1) table 249. can bit timing register (canbt , address 0x4005 000c) bit description bit symbol description reset value access 5:0 brp baud rate prescaler the value by which the oscillator frequency is divided for generating the bit time quanta. the bit time is built up from a multiple of this quanta. valid values for the baud rate prescaler are 0 to 63. [1] 000001 r/w 7:6 sjw (re)synchronization jump width valid programmed values are 0 to 3. [1] 00 r/w 11:8 tseg1 time segment before the sample point valid values are 1 to 15. [1] 0011 r/w 14:12 tseg2 time segment after the sample point valid values are 0 to 7. [1] 010 r/w 31:15 - reserved - -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 287 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller 16.6.1.5 can interrupt register if several interrupts are pending, the can in terrupt regist er will point to the pending interrupt with the highest priority, disregarding their chronological order. an interrupt remains pending until the cpu has cleared it. if intid is different from 0x0000 and ie is set, the interrupt line to the cpu is active. th e interrupt line remains active until intid is back to value 0x0000 (the cause of the interrupt is reset) or until ie is reset. the status interrupt has the highest priority . among the message interrupts, the message object s interrupt prio rity decreases with in creasing message number. a message interrupt is cleared by clearin g the message objects intpnd bit. the statusinterrupt is cleared by reading the status register. 16.6.1.6 can test register write access to the test register is enabled by setting bit test in the can control register. the different test functions may be combined, but when tx[1:0] ? 00 is selected, the message transfer is disturbed. table 250. can interrupt register (cani nt, address 0x4005 0010) bit description bit symbol description reset value access 15:0 intid 0x0000 = no interrupt is pending. 0x0001 - 0x0020 = number of message object which caused the interrupt. 0x0021 - 0x7fff = unused 0x8000 = status interrupt 0x8001 - 0xffff = unused 0r 31:16 - reserved - - table 251. can test register (cantest , address 0x4005 0014) bit description bit symbol value description reset value access 1:0 - - reserved - 2 basic basic mode 0 r/w 0 disabled. basic mode disabled. 1 enabled. if1 registers used as tx buffer, if2 registers used as rx buffer. 3 silent silent mode 0 r/w 0 normal operation. 1 silent mode. the module is in silent mode. 4 lback loop back mode 0 r/w 0 disabled. loop back mode is disabled. 1 enabled. loop back mode is enabled.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 288 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller 16.6.1.7 can baud rate prescaler extension register 16.6.2 message interface registers there are two sets of interface registers which are used to control the cpu access to the message ram. the interface registers avoid conflicts between cpu access to the message ram and can message reception and tr ansmission by buffering the data to be transferred. a complete message object (see section 16.6.2.1 ) or parts of the message object may be transferred between the message ram and the ifx message buffer registers in one single transfer. the function of the two interface register sets is identical (except for test mode basic). one set of registers may be used for data transfer to the message ram while the other set of registers may be used for the data transfer from the message ram, allowing both processes to be interrupted by each other. 6:5 tx control of can_txd pins 00 r/w 0x0 controller. level at the can_txd pin is controlled by the can controller. this is the value at reset. 0x1 sample point. the sample point can be monitored at the can_txd pin. 0x2 low. can_txd pin is driven low/dominant. 0x3 high. can_txd pin is driven high/recessive. 7 rx monitors the actual value of the can_rxd pin. 0r 0 recessive. the can bus is recessive (can_rxd = 1). 1 dominant. the can bus is dominant (can_rxd = 0). 31:8 - r/w - table 251. can test register (cantest , address 0x4005 0014) bit description bit symbol value description reset value access table 252. can baud rate prescaler extension register (canbrpe, address 0x4005 0018) bit description bit symbol description reset value access 3:0 brpe baud rate prescaler extension by programming brpe the baud rate prescaler can be extended to values up to 1023. hardware interprets the value as the value of brpe (msbs) and brp (lsbs) plus one. allowed values are 0 to 15. 0x0000 r/w 31:4 - reserved - -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 289 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller each set of interface registers consists of message buffer registers controlled by their own command registers. the command mask register specifies the direction of the data transfer and which parts of a message objec t will be transferred. the command request register is used to select a message object in the message ram as target or source for the transfer and to start the action specified in the command mask register. there are 32 message objects in the message ram. to avoid conflicts between cpu access to the message ram and can message reception and transmission, the cpu cannot directly access the message objects. the message objects are accessed through the ifx interface registers. for details of message handling, see section 16.7.3 . 16.6.2.1 message objects a message object contains the information from the various bits in the message interface registers. table 254 below shows a schematic representation of the structure of the message object. the bits of a message object and the respective interface register where this bit is set or cleared are shown. for bit functions see the corresponding interface register. 16.6.2.2 can message interface command request registers a message transfer is started as soon as the cpu has written the message number to the command request register. with this write opera tion the busy bit is automatically set to 1 and the signal can_wait_b is pulled low to notify the cpu that a transfer is in progress. after a wait time of 3 to 6 can_clk periods, the transfer between the interface register and the message ram has completed. the busy bit is set back to zero and the signal can_wait_b is set back. table 253. message interface registers if1 register names if1 register set if2 register names if2 register set canif1_cmdreq if1 command request canif2_cmdreq if2 command request canif1_cmdmask if1 command mask canif2_cmdmask if2 command mask canif1_mask1 if1 mask 1 canif2_msk1 if2 mask 1 canif1_mask2 if1 mask 2 canif2_msk2 if2 mask 2 canif1_arb1 if1 arbitration 1 canif2_arb1 if2 arbitration 1 canif1_arb2 if1 arbitration 2 canif2_arb2 if2 arbitration 2 canif1_mctrl if1 message control canif2_mctrl if2 message control canif1_da1 if1 data a1 canif2_da1 if2 data a1 canif1_da2 if1 data a2 canif2_da2 if2 data a2 canif1_db1 if1 data b1 canif2_db1 if2 data b1 canif1_db2 if1 data b2 canif2_db2 if2 data b2 table 254. structure of a message object in the message ram umask msk[28:0] mxtd mdir eob newdat msglst rxie txie intpnd if1/2_mctrl if1/2_msk1/2 if1/2_mctrl rmten txrqst msgval id[28:0] xtd dir dlc3 dlc2 dlc1 dlc0 if1/2_mctrl if1/2_arb1/2 if1/2_mctrl data0 data1 data2 data3 data4 data5 data6 data7 if1/2_da1 if1/2_da2 if1/2_db1 if1/2_db2
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 290 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller [1] when a message number that is not valid is written into the command request registers, the message number will be transformed into a valid va lue and that message object will be transferred. 16.6.2.3 can message interface command mask registers the control bits of the ifx command mask re gister specify the transfer direction and select which of the ifx messa ge buffer registers are source or target of the data transfer.the functions of the register bits depend on the transfer direction (read or write) which is selected in the wr/rd bit (b it 7) of this command mask register. select the wr/rd to one for the write transfer direction (write to message ram) zero for the read transfer direction (read from message ram) table 255. can message interface command re quest registers (canif1_cmdreq, address 0x4005 0020 and canif2_cmdreq, address 0x4005 0080) bit description bit symbol value description reset value access 5:0 mn message number 0x01 - 0x20 = valid message numbers. the message object in the message ram is selected for data transfer. 0x00 = not a valid message number. this value is interpreted as 0x20. [1] 0x21 - 0x3f = not a valid message number. this value is interpreted as 0x01 - 0x1f. [1] 0x00 r/w 14:6 - reserved - - 15 busy busy flag 0 ro 0 done. set to zero by hardware when read/write action to this command request register has finished. 1 busy. set to one by hardware when writing to this command request register. 31:16 - - reserved - - table 256. can message interface command mask registers (canif1_cmdmsk_w, address 0x4005 0024 and canif2_cmdmsk_w, addr ess 0x4005 0084) bit description for write direction bit symbol value description reset value access 0 data_b access data bytes 4-7 0 r/w 0 unchanged. data bytes 4-7 unchanged. 1 transfer. transfer data bytes 4-7 to message object. 1 data_a access data bytes 0-3 0 r/w 0 unchanged. data bytes 0-3 unchanged. 1 transfer. transfer data bytes 0-3 to message object.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 291 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller 2 txrqst access transmission request bit 0 r/w 0 no transmission request. txrqst bit unchanged in if1/2_mctrl. remark: if a transmission is requested by programming this bit, the txrqst bit in the canifn_mctrl register is ignored. 1 request a transmission. set the txrqst bit if1/2_mctrl. 3 clrintpnd - this bit is ignored in the write direction. 0 r/w 4 ctrl access control bits 0 r/w 0 unchanged. control bits unchanged. 1 transfer. transfer control bits to message object 5 arb access arbitration bits 0 r/w 0 unchanged. arbitration bits unchanged. 1 transfer. transfer ident ifier, dir, xtd, and msgval bits to message object. 6 mask access mask bits 0 r/w 0 unchanged. mask bits unchanged. 1 transfer. transfer identifier msk + mdir + mxtd to message object. 7 wr/rd 1 write transfer transfer data from the selected message buffer registers to the message object addressed by the command request register canifn_cmdreq. 0r/w 31:8 - - reserved 0 - table 257. can message interface command m ask registers (canif1_cmdmsk_r, address 0x4005 0024 and canif2_cmdmsk_r, addre ss 0x4005 0084) bit description for read direction bit symbol value description reset value access 0 data_b access data bytes 4-7 0 r/w 0 unchanged. data bytes 4-7 unchanged. 1 transfer. transfer data bytes 4-7 to ifx message buffer register. 1 data_a access data bytes 0-3 0 r/w 0 unchanged. data bytes 0-3 unchanged. 1 transfer. transfer data bytes 0-3 to ifx message buffer. table 256. can message interface command mask registers (canif1_cmdmsk_w, address 0x4005 0024 and canif2_cmdmsk_w, addr ess 0x4005 0084) bit description for write direction ?continued bit symbol value description reset value access
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 292 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller 16.6.2.4 if1 and if2 message buffer registers the bits of the message buffer registers mirror the message objects in the message ram. 2 newdat access new data bit 0 r/w 0 unchanged. newdat bit remains unchanged. remark: a read access to a message object can be combined with the reset of the control bits intpnd and newdat in if1/2_mctrl. the values of these bits transferred to the ifx message control register always reflect the status before resetting these bits. 1 clear. clear newdat bit in the message object. 3 clrintpnd clear interrupt pending bit. 0 r/w 0 unchanged. intpnd bit remains unchanged. 1 clear. clear intpnd bit in the message object. 4 ctrl access control bits 0 r/w 0 unchanged. control bits unchanged. 1 transfer. transfer control bits to ifx message buffer. 5 arb access arbitration bits 0 r/w 0 unchanged. arbitration bits unchanged. 1 transfer. transfer ident ifier, dir, xtd, and msgval bits to ifx message buffer register. 6 mask access mask bits 0 r/w 0 unchanged. mask bits unchanged. 1 transfer. transfer identifier msk + mdir + mxtd to ifx message buffer register. 7 wr/rd 0 read transfer transfer data from the message object addressed by the command request register to the selected message buffer registers canifn_cmdreq. 0r/w 31:8 - - reserved 0 - table 257. can message interface command m ask registers (canif1_cmdmsk_r, address 0x4005 0024 and canif2_cmdmsk_r, addre ss 0x4005 0084) bit description for read direction ?continued bit symbol value description reset value access
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 293 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller 16.6.2.4.1 can message interface command mask 1 registers 16.6.2.4.2 can message interface command mask 2 registers table 258. can message interface command ma sk 1 registers (canif1_msk1, address 0x4005 0028 and canif2_mas k1, address 0x4005 0088) bit description bit symbol value description reset value access 15:0 msk15_0 identifier mask [15:0] 0xffff r/w 0 match. the corresponding bit in the identifier of the message cannot inhibit the match in the acceptance filtering. 1 mask. the corresponding identifier bit is used for acceptance filtering. 31:16 - - reserved 0 - table 259. can message interface command ma sk 2 registers (canif1_msk2, address 0x4005 002c and canif2_mask2, addr ess 0x4005 008c) bit description bit symbol value description reset value access 12:0 msk28_16 identifier mask [28:16] 0xfff r/w 0 match. the corresponding bit in the identifier of the message cannot inhibit the match in the acceptance filtering. 1 mask. the corresponding identifier bit is used for acceptance filtering. 13 - reserved 1 - 14 mdir mask message direction 1 r/w 0 without dir bit. the message direction bit (dir) has no effect on acceptance filtering. 1 with dir bit. the message direction bit (dir) is used for acceptance filtering. 15 mxtd mask extend identifier 1 r/w 0 without xtd. the extended identifier bit (xtd) has no effect on acceptance filtering. 1 with xtd. the extended identifier bit (xtd) is used for acceptance filtering. 31:16 - - reserved 0 -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 294 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller 16.6.2.4.3 can message interface command arbitration 1 registers [1] 16.6.2.4.4 can message interface command arbitration 2 registers [1] table 260. can message interface command arbitr ation 1 registers ( canif1_arb1, address 0x4005 0030 and canif2_arb1, address 0x4005 0090) bit description bit symbol description reset value access 15:0 id15_0 message identifier [15:0] 29-bit identifier (extended frame) 11-bit identifier (standard fram e). these bits are not used for 11-bit identifiers. 0x00 r/w 31:16 - reserved 0 - table 261. can message interface command arbitratio n 2 registers (canif1_arb2, address 0x4005 0034 and canif2_arb2, address 0x4005 0094) bit description bit symbol value description reset value access 12:0 id[28:16] id[28:18] message identifier 29-bit identifier (extended frame) 11-bit identifier (standard frame) . id[17:16] are not used for 11-bit identifiers. 0x00 r/w 13 dir message direction 0x00 r/w 0 receive. on txrqst, a remote frame with the id entifier of this message object is transmitted. on reception of a data frame with matching identifier, that message is stored in this message object. 1transmit. on txrqst, the respective message object is transmitted as a data frame. on reception of a remote frame with matching identifier, the txrqst bit of this message object is set (if rmten = one). 14 xtd extend identifier 0x00 r/w 0 standard. the 11-bit standard identifier will be used for this message object. 1 extended. the 29-bit extended identifi er will be used for this message object. 15 msgval message valid remark: the cpu must reset the msgval bit of all unused messages objects during the initialization before it resets bit init in the can control register. this bit must also be reset be fore the identifier id28:0, the control bits xtd, dir, or the data length c ode dlc3:0 are modified, or if the messages object is no longer required. 0r/w 0 invalid. the message object is ignored by the message handler. 1 valid. the message object is config ured and should be considered by the message handler. 31:16 - - reserved 0 -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 295 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller 16.6.2.4.5 can message interface message control registers table 262. can message interface message control registers (canif1_mctrl, address 0x4005 0038 and canif2_mctrl, address 0x4005 0098) bit description bit symbol value description reset value access 3:0 dlc3_0 data length code 3:0 remark: the data length code of a messa ge object must be defined the same as in all the corresponding objects with the same identifier at other nodes. when the message handler stores a data frame, it will write the dlc to the value given by the received message. 0000 - 1000 = data frame has 0 - 8 data bytes. 1001 - 1111 = data frame has 8 data bytes. 0000 r/w 6:4 - reserved - - 7 eob end of buffer 0 r/w 0 not end of buffer. message object belong s to a fifo buffer and is not the last message object of that fifo buffer. 1 end of buffer. single message object or last message object of a fifo buffer. 8 txrqst transmit request 0 r/w 0 not waiting. this message object is not waiting for transmission. 1 waiting. the transmission of this message object is requested and is not yet done 9 rmten remote enable 0 r/w 0 txrqst unchanged. at the reception of a remote frame, txrqst is left unchanged. 1 txrqst set. at the reception of a remote frame, txrqst is set. 10 rxie receive interrupt enable 0 r/w 0 intpnd unchanged. intpnd will be left unchanged after successful reception of a frame. 1 intpnd set. intpnd will be set after successful reception of a frame. 11 txie transmit interrupt enable 0 r/w 0 intpnd unchanged. the intpnd bit will be left unchanged after a successful transmission of a frame. 1 intpnd set. intpnd will be set after a successful transmission of a frame. 12 umask use acceptance mask remark: if umask is set to 1, the message objects mask bits have to be programmed during initialization of the message object before magval is set to 1. 0r/w 0 ignore. mask ignored. 1 use. use mask (msk[28:0], mxtd, and mdir) for acceptance filtering. 13 intpnd interrupt pending 0 r/w 0 not pending. this message object is not the source of an interrupt. 1 pending. this message object is the source of an interrupt. the interrupt identifier in the interrupt register wil l point to this message object if there is no other interrupt source with higher priority.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 296 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller 16.6.2.4.6 can message interface data a1 registers in a can data frame, data0 is the first, data7 (in can_if1b2 and can_if2b2) is the last byte to be transmitted or received. in cans serial bit stream, the msb of each byte will be transmitted first. remark: byte data0 is the first data byte shifted into the shift regist er of the can core during a reception, byte data7 is the las t. when the message handler stores a data frame, it will write all the eigh t data bytes into a message ob ject. if the data length code is less than 8, the remain ing bytes of the message obje ct will be overwritten by non specified values. 16.6.2.4.7 can message interface data a2 registers 14 msglst message lost (only valid for message objects in the direction receive). 0 r/w 0 not lost. no message lost since this bit was reset last by the cpu. 1 lost. the message handler stored a new message into this object when newdat was still set, the cpu has lost a message. 15 newdat new data 0 r/w 0 no new data. no new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the cpu. 1 new data. the message handler or the cpu has written new data into the data portion of this message object. 31:16 - - reserved 0 - table 262. can message interface message control registers (canif1_mctrl, address 0x4005 0038 and canif2_mctrl, address 0x4005 0098) bit description ?continued bit symbol value description reset value access table 263. can message interface data a1 registers (canif1_da1, address 0x4005 003c and canif2_da1, address 0x4005 009c) bit description bit symbol description reset value access 7:0 data0 data byte 0 0x00 r/w 15:8 data1 data byte 1 0x00 r/w 31:16 - reserved - - table 264. can message interface data a2 registers (canif1_da2, address 0x4005 0040 and canif2_da2, address 0x4005 00a0) bit description bit symbol description reset value access 7:0 data2 data byte 2 0x00 r/w 15:8 data3 data byte 3 0x00 r/w 31:16 - reserved - -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 297 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller 16.6.2.4.8 can message interface data b1 registers 16.6.2.4.9 can message interface data b2 registers 16.6.3 message handler registers all message handler registers are read-only. their contents (txrqst, newdat, intpnd, and msgval bits of each message obje ct and the interrupt id entifier) is status information provided by the message handler fsm. 16.6.3.1 can transmission request 1 register this register contains the txrqst bits of message objects 1 to 16. by reading out the txrqst bits, the cpu can check for which me ssage object a transmission request is pending. the txrqst bit of a specific mess age object can be set/reset by the cpu via the ifx message interface registers or by the message handler after reception of a remote frame or after a successful transmission. 16.6.3.2 can transmission request 2 register this register contains the txrqst bits of message objects 32 to 17. by reading out the txrqst bits, the cpu can check for which me ssage object a transmission request is pending. the txrqst bit of a specific mess age object can be set/reset by the cpu via the ifx message interface registers or by the message handler after reception of a remote frame or after a successful transmission. table 265. can message interface data b1 registers (canif1_db1, address 0x4005 0044 and canif2_db1, address 0x4005 00a4) bit description bit symbol description reset value access 7:0 data4 data byte 4 0x00 r/w 15:8 data5 data byte 5 0x00 r/w 31:16 - reserved - - table 266. can message interface data b2 registers (canif1_db2, address 0x4005 0048 and canif2_db2, address 0x4005 00a8) bit description bit symbol description reset value access 7:0 data6 data byte 6 0x00 r/w 15:8 data7 data byte 7 0x00 r/w 31:16 - reserved - - table 267. can transmission request 1 regi ster (cantxreq1, address 0x4005 0100) bit description bit symbol description reset value access 15:0 txrqst16_1 transmission request bit of message objects 16 to 1. 0 = this message object is not waiting for transmission. 1 = the transmission of this message object is requested and not yet done. 0x00 r 31:16 - reserved - -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 298 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller 16.6.3.3 can new data 1 register this register contains the newdat bits of message objects 16 to 1. by reading out the newdat bits, the cpu can check for which message object the data portion was updated. the newdat bit of a specific mess age object can be set/reset by the cpu via the ifx message interface registers or by the message handler after reception of a data frame or after a successful transmission. 16.6.3.4 can new data 2 register this register contains the newdat bits of message objects 32 to 17. by reading out the newdat bits, the cpu can check for which message object the data portion was updated. the newdat bit of a specific mess age object can be set/reset by the cpu via the ifx message interface registers or by the message handler after reception of a data frame or after a successful transmission. table 268. can transmission request 2 regi ster (cantxreq2, address 0x4005 0104) bit description bit symbol description reset value access 15:0 txrqst32_17 transmission request bit of message objects 32 to 17. 0 = this message object is not waiting for transmission. 1 = the transmission of this message object is requested and not yet done. 0x00 r 31:16 - reserved - - table 269. can new data 1 register (ca nnd1, address 0x4005 0120) bit description bit symbol description reset value access 15:0 newdat16_1 new data bits of message objects 16 to 1. 0 = no new data has been written into the data portion of this message object by the message handler since last time this flag was cleared by the cpu. 1 = the message handler or the cpu has written new data into the data portion of this message object. 0x00 r 31:16 - reserved - - table 270. can new data 2 register (ca nnd2, address 0x4005 0124) bit description bit symbol description reset value access 15:0 newdat32_17 new data bits of message objects 32 to 17. 0 = no new data has been written into the data portion of this message object by the message handler since last time this flag was cleared by the cpu. 1 = the message handler or the cpu has written new data into the data portion of this message object. 0x00 r 31:16 - reserved - -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 299 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller 16.6.3.5 can interrupt pending 1 register this register contains the intpnd bits of message objects 16 to 1. by reading out the intpnd bits, the cpu can check for which me ssage object an interrupt is pending. the intpnd bit of a specific message object can be set/reset by the cpu via the ifx message interface registers or by the message handler after reception or after a successful transmission of a frame. this will also affect the value of intpnd in the interrupt register. 16.6.3.6 can interrupt pending 2 register this register contains the intpnd bits of message objects 32 to 17. by reading out the intpnd bits, the cpu can check for which me ssage object an interrupt is pending. the intpnd bit of a specific message object can be set/reset by the cpu via the ifx message interface registers or by the message handler after reception or after a successful transmission of a frame. this will also affect the value of intpnd in the interrupt register. 16.6.3.7 can message valid 1 register this register contains the msgval bits of message objects 16 to 1. by reading out the msgval bits, the cpu can check which messa ge object is valid. the msgval bit of a specific message object can be set/reset by the cpu via the ifx message interface registers. table 271. can interrupt pending 1 register ( canir1, address 0x4005 0140) bit description bit symbol description reset value access 15:0 intpnd16_1 interrupt pending bits of message objects 16 to 1. 0 = this message object is ignored by the message handler. 1 = this message object is the source of an interrupt. 0x00 r 31:16 - reserved - - table 272. can interrupt pending 2 regi ster (canir2, addresses 0x4005 0144) bit description bit symbol description reset value access 15:0 intpnd32_17 interrupt pending bits of message objects 32 to 17. 0 = this message object is ignored by the message handler. 1 = this message object is the source of an interrupt. 0x00 r 31:16 - reserved - - table 273. can message valid 1 register (canmsgv1, addresses 0x4005 0160) bit description bit symbol description reset value access 15:0 msgval16_1 message valid bits of message objects 16 to 1. 0 = this message object is ignored by the message handler. 1 = this message object is configured and should be considered by the message handler. 0x00 r 31:16 - reserved - -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 300 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller 16.6.3.8 can message valid 2 register this register contains the msgval bits of message objects 32 to 17. by reading out the msgval bits, the cpu can check which messa ge object is valid. the msgval bit of a specific message object can be set/reset by the cpu via the ifx message interface registers. 16.6.4 can timing register 16.6.4.1 can clock divider register this register determines the can clock signal. the can_clk is derived from the peripheral clock pclk divided by the values in this register. 16.7 functional description 16.7.1 c_can controller state after reset after a hardware reset, the registers hold the values described in table 245 . additionally, the busoff state is reset and the output ca n_txd is set to recessive (high). the value 0x0001 (init = 1) in the ca n control register enables the software initialization. the can controller does not communicate with th e can bus until the cpu resets init to 0. the data stored in the message ram is not affected by a hardware reset. after power-on, the contents of the message ram is undefined. table 274. can message valid 2 register ( canmsgv2, address 0x4005 0164) bit description bit symbol description access reset value 15:0 msgval32_17 message valid bits of message objects 32 to 17. 0 = this message object is ignored by the message handler. 1 = this message object is configured and should be considered by the message handler. r 0x00 31:16 - reserved - - table 275. can clock divider register (c anclkdiv, address 0x4005 0180) bit description bit symbol description reset value access 3:0 clkdivval clock divider value. can_clk = pclk/(clkdivval +1) 0000: can_clk = pclk divided by 1. 0001: can_clk = pclk divided by 2. 0010: can_clk = pclk divided by 3 0011: can_clk = pclk divided by 4. ... 1111: can_clk = pclk divided by 16. 1r/w 31:4 - reserved - -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 301 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller 16.7.2 c_can operating modes 16.7.2.1 software initialization the software initialization is started by setti ng the bit init in the can control register, either by software or by a hardware reset, or by entering the busoff state. during software initialization (init bit is set), the following conditions are present: ? all message transfer from and to the can bus is stopped. ? the status of the can output can_txd is recessive (high). ? the ec counters are unchanged. ? the configuration registers are unchanged. ? access to the bit timing register and the br p extension register is enabled if the cce bit in the can control register is also set. to initialize the can controller, software has to set up the bit timing register and each message object. if a message object is not needed, it is sufficient to set its msgval bit to not valid. otherwise, the whole mess age object has to be initialized. resetting the init bit finishes the software init ialization. afterwards the bit stream processor bsp synchronizes itself to the data transfer on the can bus by waiting for the occurrence of a sequence of 11 consecutive re cessive bits (bus idle) before it can take part in bus activities and starts the message transfer. remark: the initialization of the message objects is independent of init and also can be done on the fly, but the message objects should all be configured to particular identifiers or set to not valid during so ftware initialization before the bsp starts the message transfer. to change the configuration of a message object during normal operation, the cpu has to start by setting the msgval bit to not valid. when the configuration is completed, msagvalis set to valid again. 16.7.2.2 can message transfer once the can controller is initialized and init is reset to zero, the can core synchronizes itself to the can bus and starts the message transfer. received messages are stored into their app ropriate message objects if they pass the message handlers acceptance filtering. the whole message including all arbitration bits, dlc and eight data bytes is stored into the message object. if the identifier mask is used, the arbitration bits which are masked to dont care may be overwritten in the message object. the cpu may read or write each message an y time via the interface registers. the message handler guarantees data consiste ncy in case of concurrent accesses. messages to be transmitted are updated by the cpu. if a permanent message object (arbitration and control bits set up during c onfiguration) exists for the message, only the data bytes are updated and then txrqst bit with newdat bit are set to start the transmission. if several tran smit messages are assigned to the same message object (when the number of message objects is not sufficient), the whole message object has to be configured before the transmissi on of this message is requested.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 302 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller the transmission of any number of message objects may be requested at the same time, and they are transmitted subsequently according to their internal priority. messages may be updated or set to not valid any time, even when their r equested transmission is still pending. the old data will be discarded when a message is update d before its pending transmission has started. depending on the configuration of the message object, the transmission of a message may be requested autonomously by the reception of a remote frame with a matching identifier. 16.7.2.3 disabled automatic retransmission (dar) according to the can specification (iso11898, 6.3.3 recovery management) , the can controller provides means for automatic retransmission of frames that have lost arbitration or that have been disturbed by errors durin g transmission. the frame transmission service will not be confirmed to the user before the transmission is successfully completed. by default, the automatic retransmission on lost arbitration or error is enabled. it can be disabled to enable the can controller to wo rk within a time trig gered can (ttcan, see iso11898-1) environment. the disable automatic retransmission mode is enabled by programming bit dar in the can control register to one. in this operat ion mode the programmer has to consider the different behavior of bits txrqst and newdat in the control registers of the message buffers: ? when a transmission starts, bit txrqst of the respective message buffer is reset while bit newdat remains set. ? when the transmission completed su ccessfully, bit newdat is reset. ? when a transmission failed (lost arbitration or error), bit newdat remains set. to restart the transmission, the cpu has to set txrqst back to one. 16.7.2.4 test modes the test mode is entered by setting bit test in the can control register to one. in test mode the bits tx[1:0], tx0, lback, silent, and basic in the test register are writable. bit rx monitors the state of pin can_rxd and th erefore is only readable. all test register functions are disabled when bit test is reset to zero. 16.7.2.4.1 silent mode the can core can be set in silent mode by programming the test register bit silent to one. in silent mode, the can controller is able to receive valid data frames and valid remote frames, but it sends only recessive bits on the can bus, and it cannot start a transmission. if the can core is required to send a dominant bit (ack bit, overload flag, active error flag), the bit is rerouted internally so that the can core monitors this dominant bit, although the can bus may remain in recessive state. the silent mode can be used to analyze the traffic on a can bus without affect ing it by the transmission of dominant bits (acknowledge bits, error frames).
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 303 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller 16.7.2.4.2 loop-back mode the can core can be set in loop-back mode by programming the test register bit lback to one. in loop-back mode, the can co re treats its own transmitted messages as received messages and stores them (if they pass acceptance filtering) into a receive buffer. this mode is provided for self-test functions. to be independent from external stimulation, the can core ignores acknowledge errors (recessive bit sampled in the acknowledge slot of a data/remote frame) in loop-back mode. in this mode the can core performs an internal feedback from its can_txd output to its can_rxd input. the actual value of the can_rxd input pin is disregarded by the can core. the transmitted messages can be monitored at the can_txd pin. 16.7.2.4.3 loop-back mode combined with silent mode it is also possible to combine loop-back mode and silent mode by programming bits lback and silent to one at the same time. th is mode can be used for a hot selftest, meaning the c_can can be tested without af fecting a running can system connected to the pins can_txd and can_rxd. in this mo de the can_rxd pin is disconnected from the can core and the can_tx d pin is held recessive. fig 62. can core in silent mode can core can_txd can_rxd c_can = 1 rx tx fig 63. can core in loop-back mode can core can_txd can_rxd c_can rx tx
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 304 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller 16.7.2.4.4 basic mode the can core can be set in ba sic mode by progra mming the test regi ster bit basic to one. in this mode the can controller runs without the message ram. the if1 registers are used as transmit buffer . the transmission of the contents of the if1 registers is requested by writing the bu sy bit of the if1 command request register to 1. the if1 registers are locked while the busy bit is se t. the busy bit indicates that the transmission is pending. as soon the can bus is idle, the if1 registers are loaded into the shift register of the can core and the transmission is started. when the transmission has completed, the busy bit is reset and the locked if1 registers are released. a pending transmission can be aborted at any time by resetting the busy bit in the if1 command request register while the if1 registers are locked. if the cpu has reset the busy bit, a possible retransmission in case of lo st arbitration or in case of an error is disabled. the if2 registers are used as receive buff er. after the reception of a message the contents of the shift register is stored in to the if2 registers, without any acceptance filtering. additionally, the actual contents of the shift register can be monitored during the message transfer. each time a read message object is initiated by writing the busy bit of the if2 command request register to 1, the contents of the shift register is stored into the if2 registers. in basic mode the evaluation of all message ob ject related control and status bits and of the control bits of the ifx command mask registers is turned off. the message number of the command request registers is not evalua ted. the newdat and msglst bits of the if2 message control register retain their function, dlc3-0 will show the received dlc, the other control bits will be read as 0. in basic mode the ready output can_wait_b is disabled (always 1) 16.7.2.4.5 soft ware control of pin can_txd four output functions are available for the can transmit pin can_txd: 1. serial data output (default). fig 64. can core in loop-back mo de combined with silent mode can core can_txd can_rxd c_can = 1 rx tx
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 305 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller 2. drives can sample point signal to monitor the can controllers timing. 3. drives recessive constant value. 4. drives dominant constant value. the last two functions, combined with the re adable can receive pin can_rxd, can be used to check the can bus physical layer. the output mode of pin can_txd is selected by programming the test register bits tx1 and tx0 as described section 16.6.1.6 . remark: the three test functions for pin can_txd interfere with all can protocol functions. the can_txd pin must be left in its default function when can message transfer or any of the test modes loo-back mode, silent mode, or basic mode are selected. 16.7.3 can message handler the message handler controls the data transfer between the rx/tx shift register of the can core, the message ram a nd the ifx registers, see figure 65 . the message handler controls the following functions: ? data transfer between ifx registers and the message ram ? data transfer from shift register to the message ram ? data transfer from mess age ram to shift register ? data transfer from shift register to the acceptance filtering unit ? scanning of message ram for a matching message object ? handling of txrqst flags ? handling of interrupts
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 306 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller 16.7.3.1 management of message objects the configuration of the messa ge objects in the message ram will (with the exception of the bits msgval, newdat, intpnd, and txrqst) is not be affected by resetting the chip. all the message objects mu st be initialized by the cpu or they must be set to not valid (msgval = 0).the bit timing must be conf igured before the cpu clears the init bit in the can control register. the configuration of a message object is don e by programming mask, arbitration, control and data field of one of the two interface regist er sets to the desired values. by writing to the corresponding ifx command request regist er, the ifx message buffer registers are loaded into the addressed message object in the message ram. when the init bit in the can control regist er is cleared, the can protocol controller state machine of the can core and the mess age handler state machine control the can controllers internal data flow. received messages that pass the acceptance filtering are stored into the message ram, and messa ges with pending transmission request are loaded into the can cores shift register and are transmitted via the can bus. the cpu reads received messages and updates messages to be transmitted via the ifx interface registers. depending on the configur ation, the cpu is interrupted on certain can message and can error events. fig 65. block diagram of a message object transfer if1 mask1, 2 if1 arbitration 1/2 if1 message ctrl if1 data a1/2 if1 data b1/2 if2 mask1, 2 if2 arbitration 1/2 if2 message ctrl if2 data a1/2 if2 data b1/2 message ram message object 1 message object 2 . . . message object 32 transfer a message object read transfer write transfer apb bus message buffer registers if1 command request if1 command mask if2 command request if2 command mask interface command registers message handler transmission request 1/2 new data 1/2 interrupt pending1/2 message valid1/2 can bus receive transfer a can frame transmit can core/ shift registers
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 307 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller 16.7.3.2 data transfer between ifx registers and the message ram when the cpu initiates a data transfer between the ifx registers and message ram, the message handler sets the busy bit in the resp ective command register to 1. after the transfer has completed, the busy bit is set back to 0. the command mask register spec ifies whether a complete messa ge object or only parts of it will be transferred. due to the structure of the message ram it is not possible to write single bits/bytes of one message object. soft ware must always write a complete message object into the message ram. therefore the data transfer from the ifx registers to the message ram requires a read-modify-write cycle: 1. read the parts of the message object that are not to be changed from the message ram using the command mask register. ? after the partial read of a message object, the message buffer registers that are not selected in the command ma sk register will be left unchanged. 2. write the complete contents of the message buffer registers into the message object. ? after the partial write of a message object , the message buffer registers that are not selected in the comman d mask register will set to th e actual contents of the selected message object. 16.7.3.3 transmission of messages between t he shift registers in the can core and the message buffer if the shift register of the can core cell is ready for loading and if there is no data transfer between the ifx registers and message ram, the msgval bits in the message valid register txrqst bits in the transmission request register are evaluated. the valid message object with the highest priority pendi ng transmission request is loaded into the shift register by the message handler and the transmission is started. the message objects newdat bit is reset. after a successful transmission and if no ne w data was written to the message object (newdat = 0) since the start of the transmission, the tx rqst bit will be reset. if txie is set, intpnd will be set after a successful transmission. if the can controller has lost the arbitration or if an error occurred during the tr ansmission, the message will be retransmitted as soon as the can bus is free again. if meanwhile the transmission of a message with higher priority has been requested, the messag es will be transmitted in the order of their priority. 16.7.3.4 acceptance filtering of received messages when the arbitration and control field (ide ntifier + ide + rtr + dlc) of an incoming message is completely shifte d into the rx/tx shift regi ster of the can core, the message handler state machine starts the scanning of the message ram for a matching valid message object. to scan the message ram for a matching me ssage object, the acceptance filtering unit is loaded with the arbitration bits from the can core shift register. then the arbitration and mask fields (including msgval, umask, ne wdat, and eob) of message object 1 are loaded into the acceptance filtering unit and compared with the arbitration field from the shift register. this is repeated with each following message obje ct until a matching message object is found or until the end of the message ram is reached.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 308 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller if a match occurs, the scanning is stopped and the message handler state machine proceeds depending on the type of frame (data frame or remote frame) received. 16.7.3.4.1 reception of a data frame the message handler state machine stores the message from the can core shift register into the respective message object in the message ram. the data bytes, all arbitration bits, and the data length code are stored into the corresponding message object. this is implemented to keep the data bytes connected with the identifier even if arbitration mask registers are used. the newdat bit is set to indicate that new data (not yet seen by the cpu) has been received. the cpu/software s hould reset newdat when it reads the message object. if at the time of the reception the newdat bit was already set, msglst is set to indicate that the previous data (supposedly not seen by the cpu) is lost. if the rxie bit is set, the intpnd bit is also set, causing the interrupt register to point to this message object. the txrqst bit of this message object is re set to prevent the transmission of a remote frame, while the requested data frame has just been received. 16.7.3.4.2 reception of a remote frame when a remote frame is received, three di fferent configurations of the matching message object have to be considered: 1. dir = 1 (direction = transmit), rmten = 1, umask = 1 or0 on the reception of a matching remote frame, the txrqst bit of this message object is set. the rest of the message object remains unchanged. 2. dir = 1 (direction = transm it), rmten = 0, umask = 0 on the reception of a matching remote frame, the txrqst bit of this message object remains unchanged; the remote frame is ignored. 3. dir = 1 (direction = transm it), rmten = 0, umask = 1 on the reception of a matching remote frame, the txrqst bit of this message object is reset. the arbitration and control field (identifier + ide + rtr + dlc) from the shift register is stored into the me ssage object in the message ram, and the newdat bit of this message object is se t. the data field of the message object remains unchanged; the remote frame is treated similar to a received data frame. 16.7.3.5 receive/transmit priority the receive/transmit priority for the message objects is attached to the message number. message object 1 has the highest priority, while message object 32 has the lowest priority. if more than one transmission requ est is pending, they are serviced due to the priority of the corresponding message object. 16.7.3.6 configuration of a transmit object table 276 shows how a transmit object should be initialized by software (see also table 254 ):
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 309 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller the arbitration registers (id28:0 and xtd bit) are given by the application. they define the identifier and the type of the outgoing message. if an 11-bit id entifier (standard frame) is used, it is programmed to id28. in this case id18, id17 to id0 can be disregarded. if the txie bit is set, the in tpnd bit will be set after a successful transmission of the message object. if the rmten bit is set, a matching received remote frame will cause the txrqst bit to be set, and the remote fr ame will autonomously be answered by a data frame. the data registers (dlc3:0, data0:7) are given by the application. txrqst and rmten may not be set before the data is valid. the mask registers (msk28 -0, umask, mxtd, and md ir bits) may be used (umask=1) to allow groups of remote frames with similar identifier s to set the txrqst bit. for details see section 16.7.3.4.2 . the dir bit should not be masked. 16.7.3.7 updating a transmit object the cpu may update the data bytes of a transm it object any time via the ifx interface registers. neither msgval nor txrqst have to be reset before the update. even if only a part of the data bytes are to be updated, all four bytes of the corresponding ifx data a register or ifx data b register have to be valid before the content of that register is transferred to the message object . either the cpu has to write all four bytes into the ifx data register or the message object is transferred to the ifx data register before the cpu writes the new data bytes. when only the (eight) data bytes are updated, first 0x0087 is written to the command mask register. then the number of the me ssage object is written to the command request register, concurrently updati ng the data bytes and setting txrqst. to prevent the reset of txrqst at the end of a transmission that may already be in progress while the data is updated, newdat has to be set together with txrqst. for details see section 16.7.3.3 . when newdat is set togeth er with txrqst, newdat will be reset as soon as the new transmission has started. 16.7.3.8 configuration of a receive object table 277 shows how a receive object should be initialized by software (see also table 254 ) table 276. initialization of a transmit object msgval arbitration bits data bits mask bits eob dir newdat 1 application dependent application dependent application dependent 110 msglst rxie txie intpnd rmten txrqst 0 0 application dependent 0 application dependent 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 310 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller the arbitration registers (id28-0 and xtd bit) are given by the application. they define the identifier and type of accepted received messages. if an 11-bit identifier (standard frame) is used, it is programmed to id[28: 18]. id17 to id0 can then be disregarded. when a data frame with an 11-b it identifier is received, id17 to id0 will be set to 0. if the rxie bit is set, the intpnd bit will be set when a received data frame is accepted and stored in the message object. the data length code (dlc[3:0] is given by the application. when the message handler stores a data frame in the message object, it will store the received data length code and eight data bytes. if the data length code is less than 8, the remaining bytes of the message object will be overwri tten by non specified values. the mask registers (msk[28:0], umask, mxtd, and mdir bits) may be used (umask=1) to allow groups of data frames with similar identifiers to be accepted. for details see section section 16.7.3.4.1 . the dir bit should not be masked in typical applications. 16.7.3.9 handling of received messages the cpu may read a received message any time via the ifx interface registers. the data consistency is guaranteed by the message handler state machine. to transfer the entire received message from message ram into the message buffer, software must write first 0x007f to the command mask register and then the number of the message object to the command request register. additionally, the bits newdat and intpnd are cleared in the message ram (not in the message buffer). if the message object uses masks for acceptance filtering, the arbitration bits show which of the matching messages has been received. the actual value of newdat shows whet her a new message has been received since last time this message obje ct was read. the actual value of msglst shows whether more than one message has been received since last time this message object was read. msglst will not be automatically reset. using a remote frame, the cpu may request another can node to provide new data for a receive object. setting the tx rqst bit of a receive object will cause the tran smission of a remote frame with the receive objects identifier. this remote frame triggers the other can node to start the transmission of the matching data frame. if the matching data frame is received before the remote frame could be transmitted, the txrqst bit is automatically reset. table 277. initialization of a receive object msgval arbitration bits data bits mask bits eob dir newdat 1 application dependent application dependent application dependent 100 msglst rxie txie intpnd rmten txrqst 0 application dependent 000 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 311 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller 16.7.3.10 configuration of a fifo buffer with the exception of the eob bit, the conf iguration of receive ob jects belonging to a fifo buffer is the same as the configuratio n of a (single) receive object, see section section 16.7.3.8 . to concatenate two or more message object s into a fifo buffer, the identifiers and masks (if used) of these message objects have to be programmed to matching values. due to the implicit pr iority of the message objects, th e message object with the lowest number will be the first message object of th e fifo buffer. the eo b bit of all message objects of a fifo buffer except the last have to be programmed to zero. the eob bits of the last message object of a fifo buffer is set to one, configuring it as the end of the block. 16.7.3.10.1 recepti on of messages with fifo buffers received messages with identifiers matching to a fifo buffer are stored into a message object of this fifo buffer starting with the message object with the lowest message number. when a message is stored into a message object of a fifo buffer the newdat bit of this message object is set. by setting newdat while eob is zero the message object is locked for further write accesses by the me ssage handler until the cpu has written the newdat bit back to zero. messages are stored into a fifo buffer until the last message object of this fifo buffer is reached. if none of the preceding message objects is released by writing newdat to zero, all further messag es for this fifo buffer will be wri tten into the last message object of the fifo buffer and therefore overwrite previous messages. 16.7.3.10.2 reading from a fifo buffer when the cpu transfers the contents of me ssage object to the ifx message buffer registers by writing its number to the ifx command request register, bits newdat and intpnd in the corresponding command mask register should be reset to zero (txrqst/newdat = 1 and clrintpnd = 1). th e values of these bits in the message control register always reflect the status before resetting the bits. to assure the correct function of a fifo buffer, the cpu should read out the message objects starting at the fifo object with the lowest message number.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 312 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller 16.7.4 interrupt handling if several interrupts are pending, the can in terrupt regist er will point to the pending interrupt with the highest priority, disregarding their chronological order. an interrupt remains pending until the cpu has cleared it. fig 66. reading a message from the fifo buffer to the message buffer start end read canir messagenum = intid read canifx_mctrl write messagenum to canifx_cmdreq read data from canifx_da/b messagenum = messagenum +1 read message to message buffer reset newdat = 0 reset intpnd = 0 intid = 0x8000 ? newdat = 1 eob = 1 intid = 0x0001 to 0x0020 ? intid = 0x0000 ? status change interrupt handling yes yes yes yes no no yes
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 313 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller the status interrupt has the highest priority . among the message interrupts, the message objects interrupt priority decreases with increasing message number. a message interrupt is cleared by clearing the message objects intpnd bit. the status interrupt is cleared by reading the status register. the interrupt identifier intid in the interrupt register indicates the cause of the interrupt. when no interrupt is p ending, the register will hold the value zero. if the value of the interrupt register is different fr om zero, then there is an interr upt pending and, if ie is set, the interrupt line to the cpu, irq_b, is acti ve. the interrupt line re mains active until the interrupt register is ba ck to value zero (the cause of the interrupt is reset) or until ie is reset. the value 0x8000 indicates that an interrupt is pending because the can core has updated (not necessarily changed) the status register (error interrupt or status interrupt). this in terrupt has the highest priority. the cpu can update (reset) the status bits rxok, txok and lec, but a write access of the cpu to the status register can never generate or reset an interrupt. all other values indicate that the source of the interrupt is one of the message objects where intid points to the pending message interrupt with the highest interrupt priority. the cpu controls whether a change of the stat us register may cause an interrupt (bits eie and sie in the can control register) and whether the interrupt line becomes active when the interrupt register is different from ze ro (bit ie in the can control register). the interrupt register will be updated even when ie is reset. the cpu has two possibilities to follow the source of a message interrupt: ? software can follow the intid in the interrupt register. ? software can poll the interrupt pending register, see section 16.6.3.5 . an interrupt service routine reading the message that is the source of the interrupt may read the message and reset the message objects intpnd at the same time (bit clrintpnd in the command ma sk register). when intpnd is cleared, the interrupt register will point to the next message object with a pending in terrupt. 16.7.5 bit timing even if minor errors in the configuration of the can bit timing do not result in immediate failure, the performance of a can network can be reduced significantly. in many cases, the can bit synchronization will amend a faulty c onfiguration of the can bit timing to such a degree that only occasionally an error fr ame is generated. in the case of arbitration however, when two or more can nodes simultaneously try to transmit a frame, a misplaced sample point may cause one of the transmitters to become error passive. the analysis of such sporadic errors requires a detailed knowledge of the can bit synchronization inside a can node and of the can nodes interaction on the can bus.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 314 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller 16.7.5.1 bit time and bit rate can supports bit rates in the range of lower than 1 kbit/s up to 1000 kbit/s. each member of the can network has its own clock generator, usually a quartz oscillator. the timing parameter of the bit time (i.e. the reciprocal of the bit rate) can be configured individually for each can node, creating a common bit rate even though the can nodes oscillator periods (f osc ) may be different. the frequencies of these oscilla tors are not absolutely stab le, as small variations are caused by changes in temperature or voltage and by deteriorating components. as long as the variations remain inside a specific oscillator tolerance rang e (df), the can nodes are able to compensate for the different bit rates by re-synchronizing to the bit stream. according to the can specification, the bit time is divided into four segments ( figure 67 ). the synchronization segment, the propagation time segment, the phase buffer segment 1, and the phase buffer segment 2. each segment consists of a specific, programmable number of time quanta (see table 278 ). the length of the time quantum (t q ), which is the basic time unit of the bit ti me, is defined by the can controllers system clock f and the baud rate prescaler (brp): t q = brp / f sys . the c_cans system clock f sys is the frequency of the lpc11cx system clock (see section 16.2 ). the synchronization segment sync_seg is the part of the bit time where edges of the can bus level are expected to occur; the distance between an edge that occurs outside of sync_seg and the sync_seg is called the phase error of that edge. the propagation time segment prop_seg is intended to comp ensate for the physical delay times within the can network. the phase buffer segments phase_seg1 and phase_seg2 surround the sample point. the (re-)synchronization jump width (sjw) defines how far a re-synchronization may move the sample point inside the limits defined by the phase buffer segments to compensate for edge phase errors. table 278 describes the minimum programmable ra nges required by the can protocol. bit time parameters are programmed through the canbt register, table 249 . for details on bit timing and examples, see the c_can user?s manual, revision 1.2 . table 278. parameters of the c_can bit time parameter range function brp (1...32) defines the leng th of the time quantum t q . sync_seg 1t q synchronization segment. fixe d length. synchronization of bus input to system clock. prop_seg (1...8) ? t q propagation time segment. compensates for physical delay times. this parameter is determined by the system delay times in the c_can network. tseg1 (1...8) ? t q phase buffer segment 1. may be lengthened temporarily by synchronization. tseg2 (1...8) ? t q phase buffer segment 2. may be shortened temporarily by synchronization. sjw (1...4) ? t q (re-) synchronization jump width. may not be longer than either phase buffer segment.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 315 of 543 nxp semiconductors um10398 chapter 16: lpc111x/lpc11cxx c_can controller fig 67. bit timing
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 316 of 543 17.1 how to read this chapter the c_can block is available in lpc11cxx parts only (lpc11c00 series). 17.2 features the on-chip drivers are stored in boot rom and offer can and canopen initialization and communication features to user applications via a defined api. the following functions are included in the api: ? can set-up and initialization ? can send and receive messages ? can status ? canopen object dictionary ? canopen sdo expedited communication ? canopen sdo segmented communication primitives ? canopen sdo fall-back handler 17.3 general description in addition to the can isp, the boot rom provides a can and canopen api to simplify can application development. it covers in itialization, configuration, basic can send/receive as well as a canopen sdo inte rface. callback functions are available to process receive events. 17.3.1 differences to fully-compliant canopen while the bootloader uses the sdo communica tion protocol and the object dictionary data organization method, it is not a fully cia 301 standard compliant canopen node. in particular, the following features are not available or different to the standard: ? no network management (nmt) message processing. ? no heartbeat message, no entry 0x1017. ? uses proprietary sdo abort codes to indicate device errors ? empty sdo responses during sdo segmented download/write to the node are shortened to one data byte, rather than full eight data bytes as the standard describes. this to speed up the communication. ? entry [1018h,1] vendor id reads 0x0000 0000 rather than an official cia-assigned unique vendor id. this in pa rticular because the chip will be incorporated into designs of customers who will become the vendor of th e whole device. the host will have to use a different method to identify the can isp devices. ? the maximum od entries allowed is 255. um10398 chapter 17: lpc11cxx c_ can on-chip drivers rev. 12.1 ? 7 august 2013 user manual
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 317 of 543 nxp semiconductors um10398 chapter 17: lpc11cxx c_can on-chip drivers 17.4 api description 17.4.1 calling the c_can api a fixed location in rom contains a pointer to the rom driver table i.e. 0x1fff 1ff8. this location is the same for all lpc11cxx parts. the rom driver table contains pointer to the can api table. pointers to the various can api functions are stored in this table. can api functions can be called by using a c structure. figure 68 illustrates the pointer mechanism used to access the on-chip can api. on-chip ram from address 0x1000 0050 to 0x1000 00b8 is used by the can api. this address range should not be used by the application. for applications using the on-chip can api, the linker control file should be modified appropriately to prevent usage of this area for applications variable storage. in c, the structure with the function list that is referenced to call the api functions looks as follows: typedef struct _cand { void (*init_can) (uint32_t * can_cfg, uint8_t isr_ena); void (*isr) (void); void (*config_rxmsgobj) (can_msg_obj * msg_obj); uint8_t (*can_receive) (can_msg_obj * msg_obj); void (*can_transmit) (can_msg_obj * msg_obj); void (*config_canopen) (can_canopencfg * canopen_cfg); void (*canopen_handler) (void); void (*config_calb) (can_callbacks * callback_cfg); } cand; fig 68. can api pointer structure ptr to c_can api table ptr to device table 1 ptr to device table 0 ptr to device table n init_can isr config_canopen canopen_handler config_calb ptr to function 2 ptr to function 0 ptr to function 1 ptr to function n c_can api device n rom driver table 0x1fff 1ff8 0x1fff 1ffc 0x1fff 2000 config_rxmsgobj can_receive can_transmit
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 318 of 543 nxp semiconductors um10398 chapter 17: lpc11cxx c_can on-chip drivers 17.4.2 can initialization the can controller clock divider, the can bi t rate is set, and the can controller is initialized based on an array of register values that are passed on via a pointer. void init_can (uint32_t * can_cfg, uint8_t isr_ena) the first 32-bit value in the array is applied to the canclkdiv register, the second value is applied to the can_btr register. the second parameter enables interrupts on the can controller level. set to false for polled communication. example call: rom **rom = (rom **)(0x1fff1ff8); uint32_t canapiclkinittable[2] = { 0x00000000ul, // canclkdiv 0x00004dc5ul // can_btr }; (*rom)->pcand->init_can(&c anapicaninittable[0], 1); 17.4.3 can interrupt handler when the user application is active, the interrupt handlers are mapped in the user flash space. the user application must provide an interrupt handler for the can interrupt. in order to process can events and call the callback functions the application must call the can api interrupt handler directly from the interrupt handler routine. the can api interrupt handler takes appropriate action according to the data received and the status detected on the can bus. void isr (void) the can interrupt handler does not process canopen messages. example call: (*rom)->pcand->isr(); for polled communication, the interrupt handler may be called manually as often as required. the callback function s for receive, transmit, an d error will be executed as described and on the same level the interrupt handler was called from. 17.4.4 can rx message object configuration the can api supports and uses the full can model with 32 message objects. any of the message objects can be used for receive or transmit of either 11-bit or 29-bit can messages. can messages that have their rtr-bit set (remote transmit) are also supported. for receive objects, a mask pattern for the message identifi er allows to receive ranges of messages, up to receiving all can messages on the bus in a single message object. see also section 16.7.3.4 .
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 319 of 543 nxp semiconductors um10398 chapter 17: lpc11cxx c_can on-chip drivers transmit message objects are automatically configured when used. // control bits for can_msg_obj.mode_id #define can_msgobj_std 0x00000000ul // can 2.0a 11-bit id #define can_msgobj_ext 0x20000000ul // can 2.0b 29-bit id #define can_msgobj_dat 0x00000000ul // data frame #define can_msgobj_rtr 0x40000000ul // rtr frame typedef struct _can_msg_obj { uint32_t mode_id; uint32_t mask; uint8_t data[8]; uint8_t dlc; uint8_t msgobj; } can_msg_obj; void config_rxmsgobj (can_msg_obj * msg_obj) example call: // configure message object 1 to receive all 11-bit messages 0x000-0x00f msg_obj.msgobj = 1; msg_obj.mode_id = 0x000; msg_obj.mask = 0x7f0; (*rom)->pcand-> config_rxmsgobj(&msg_obj); 17.4.5 can receive the can receive function allows reading messag es that have been received by an rx message object. a pointer to a message object structure is passed to the receive function. before calling, the number of th e message object that is to be read has to be set in the structure. void config_rxmsgobj (can_msg_obj * msg_obj) example call: // read out received message msg_obj.msgobj = 5; (*rom)->pcand->can_receive(&msg_obj); 17.4.6 can transmit the can transmit function allows setting up a message object and triggering the transmission of a can message on the bus. 11-bit standard and 29-bit extended messages are supported as well as both standard data and remote-transmit (rtr) messages. void config_txmsgobj (can_msg_obj * msg_obj) example call: msg_obj.msgobj = 3; msg_obj.mode_id = 0x123ul;
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 320 of 543 nxp semiconductors um10398 chapter 17: lpc11cxx c_can on-chip drivers msg_obj.mask = 0x0ul; msg_obj.dlc = 1; msg_obj.data[0] = 0x00; (*rom)->pcand->can_transmit(&msg_obj); 17.4.7 canopen configuration the can api supports an object dictionary in terface and the sdo pr otocol. in order to activate it, the canopen configuration func tion has to be called with a pointer to a structure with the canopen node id (1...127), the message object numbers to use for receive and transmit sdos, a flag to decide whether the canopen sdo handling should happen in the interrupt serving function automa tically or via the dedicated api function, and two pointers to object dictionary configuration tables and their sizes. one table contains all read-only, constant entries of four bytes or less. the second table contains all variable and writable entries as well as sdo segmented entries. typedef struct _can_odconstentry { uint16_t index; uint8_t subindex; uint8_t len; uint32_t val; } can_odconstentry; // upper-nibble values for can_odentry.entrytype_len #define od_none 0x00 // object dictionary entry doesn't exist #define od_exp_ro 0x10 // object dictionary entry expedited, read-only #define od_exp_wo 0x20 // object dictionary entry expedited, write-only #define od_exp_rw 0x30 // object dictionary entry expedited, read-write #define od_seg_ro 0x40 // object dictionary entry segmented, read-only #define od_seg_wo 0x50 // object dictionary entry segmented, write-only #define od_seg_rw 0x60 // object dictionary entry segmented, read-write typedef struct _can_odentry { uint16_t index; uint8_t subindex; uint8_t entrytype_len; unint8_t isr_handled; uint8_t *val; } can_odentry; typedef struct _can_canopencfg { uint8_t node_id; uint8_t msgobj_rx; uint8_t msgobj_tx; uint8_t isr_handled; uint32_t od_const_num; can_odconstentry *od_const_table; uint32_t od_num; can_odentry *od_table; } can_canopencfg;
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 321 of 543 nxp semiconductors um10398 chapter 17: lpc11cxx c_can on-chip drivers example od tables and cano pen configuration structure: // list of fixed, read-only object dictionary (od) entries // expedited sdo only, length=1/2/4 bytes const can_odconstentry myconstod [] = { // index subindex length value { 0x1000, 0x00, 4, 0x54534554ul }, // "test" { 0x1018, 0x00, 1, 0x00000003ul }, { 0x1018, 0x01, 4, 0x00000003ul }, { 0x2000, 0x00, 1, (uint32_t)'m' }, }; // list of variable od entries // expedited sdo with length=1/2/4 bytes // segmented sdo application-handled with length and value_pointer don't care const can_odentry myod [] = { // index subindex access_type|length value_pointer { 0x1001, 0x00, od_exp_ro | 1, (uint8_t *)&error_register }, { 0x1018, 0x02, od_exp_ro | 4, (uint8_t *)&device_id }, { 0x1018, 0x03, od_exp_ro | 4, (uint8_t *)&fw_ver }, { 0x2001, 0x00, od_exp_rw | 2, (uint8_t *)¶m }, { 0x2200, 0x00, od_seg_rw, (uint8_t *)null }, }; // canopen configuration structure const can_canopencfg mycanopen = { 20, // node_id 5, // msgobj_rx 6, // msgobj_tx true, // isr_handled sizeof(myconstod)/sizeof(myconstod[0]), // od_const_num (can_odconstentry *)myconstod, // od_const_table sizeof(myod)/sizeof(myod[0]), // od_num (can_odentry *)myod, // od_table }; example call: // initialize canopen handler (*rom)->pcand->config_canopen((can_canopencfg *)&mycanopen[0]);
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 322 of 543 nxp semiconductors um10398 chapter 17: lpc11cxx c_can on-chip drivers 17.4.8 canopen handler the canopen handler processes the canope n sdo messages to a ccess the object dictionary and calls the canopen callback fu nctions when initialized. it can either be called by the interrupt handler automati cally (isr_handled == true in canopen initialization structur e) or manually via the canopen handler api function. if called manually, the canopen handler has to be called cyclically as often as needed for the application. in a typical canopen application, sdo handling has the lowest priority and is done in the foreground rather than through interrupt processing. example call: // call canopen handler (*rom)->pcand->c anopen_handler(); 17.4.9 can/canopen callback functions the can api supports callback functions for various events. the callback functions are published via an api function. typedef struct _can_callbacks { void (*can_rx)(uint8_t msg_obj); void (*can_tx)(uint8_t msg_obj); void (*can_error)(uint32_t error_info); uint32_t (*canopen_sdo_read)(uint16_t index, uint8_t subindex); uint32_t (*canopen_sdo_write)( uint16_t index, uint8_t subindex, uint8_t *dat_ptr); uint32_t (*canopen_sdo_seg_read)( uint16_t index, uint8_t subindex, uint8_t openclose, uint8_t *length, uint8_t *data, uint8_t *last); uint32_t (*canopen_sdo_seg_write)( uint16_t index, uint8_t subindex, uint8_t openclose, uint8_t length, uint8_t *data, uint8_t *fast_resp); uint8_t (*canopen_sdo_req)( uint8_t length_req, uint8_t *req_ptr, uint8_t *length_resp, uint8_t *resp_ptr); } can_callbacks; example callback table definition: // list of callback function pointers const can_callbacks callbacks = { can_rx, can_tx, can_error, canopen_sdo_exp_read, canopen_sdo_exp_write, canopen_sdo_seg_read, canopen_sdo_seg_write, canopen_sdo_req, };
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 323 of 543 nxp semiconductors um10398 chapter 17: lpc11cxx c_can on-chip drivers /* callback function prototypes */ void can_rx(uint8_t msg_obj_num); void can_tx(uint8_t msg_obj_num); void can_error(uint32_t error_info); /* canopen callback function prototypes */ uint32_t canopen_sdo_exp_read (uint16_t index, uint8_t subindex); uint32_t canopen_sdo_exp_write(uint16_t index, uint8_t subindex, uint8_t *dat_ptr); uint32_t canopen_sdo_seg_read(uint16_t index, uint8_t subindex, uint8_t openclose, uint8_t *length, uint8_t *data, uint8_t *last); uint32_t canopen_sdo_seg_write(uint16_t index, uint8_t subi ndex, uint8_t openclose, uint8_t length, uint8_t *data, uint8_t *fast_resp); uint8_t canopen_sdo_req(uint8_t length_req, uint8_t *req_ptr, uint8_t *length_resp, uint8_t *resp_ptr); example call: // publish callbacks (*rom)->pcand->config_calb(&callbacks); 17.4.10 can message received callback the can message received callback function is called on the interr upt level by the can interrupt handler. example call: // can receive handler void can_rx(uint8_t msgobj_num) { // read out received message msg_obj.msgobj = msgobj_num; (*rom)->pcand->can_receive(&msg_obj); return; } remark: the callback is not called if the user canopen handler is activated for the message object that is used for sdo receive. 17.4.11 can message transmit callback called on the interrupt level by the can interrupt handler after a message has been successfully transm itted on the bus. example call: // can transmit handler void can_tx(uint8_t msgobj_num) { // reset flag used by application to wait for transmission finished if (wait_for_tx_finished == msgobj_num) wait_for_tx_finished = 0; return; }
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 324 of 543 nxp semiconductors um10398 chapter 17: lpc11cxx c_can on-chip drivers remark: the callback is not called after the user canopen handler has used a message object to transmit an sdo response. 17.4.12 can error callback the can error callback function is called on the interrupt level by the can interrupt handler. // error status bits #define can_error_none 0x00000000ul #define can_error_pass 0x00000001ul #define can_error_warn 0x00000002ul #define can_error_boff 0x00000004ul #define can_error_stuf 0x00000008ul #define can_error_form 0x00000010ul #define can_error_ack 0x00000020ul #define can_error_bit1 0x00000040ul #define can_error_bit0 0x00000080ul #define can_error_crc 0x00000100ul example call: // can error handler void can_error(uint32_t error_info) // if we went into bus off state, tell the application to // re-initialize the can controller if (error_info & can_error_boff) reset_can = true; return; } 17.4.13 canopen sdo expedited read callback the canopen sdo expedited read callback f unction is called by the canopen handler. the callback function is called before the sdo response is generated, allowing to modify or update the data. example call: // canopen callback for expedited read accesses uint32_t canopen_sdo_exp_read(uint16_t index, uint8_t subindex) { // every read of [2001h,0] increases param by one if ((index == 0x2001) && (subindex==0)) param++; return 0; } remark: if the flag isr_handled was set to true when initializing cano pen, this callback function will be called by the can api interr upt handler and theref ore will execute on the interrupt level.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 325 of 543 nxp semiconductors um10398 chapter 17: lpc11cxx c_can on-chip drivers 17.4.14 canopen sdo expedited write callback the canopen sdo expedited write callback func tion is called by the canopen handler. the callback passes on the new data and is called before the new data has been written, allowing to reject or condition the data. example call: // canopen callback for expedited write accesses uint32_t canopen_sdo_exp_write(uint16_t index, uint8_t subindex, uint8_t *dat_ptr) { // writing 0xaa55 to entry [2001h,0] unlocks writing the config table if ((index == 0x2001) && (subindex == 0)) if (*(uint16_t *)dat_ptr == 0xaa55) { write_config_ena = true; return(true); } else return(false); // reject any other value } remark: if the flag isr_handled wa s set true when initializing canopen, this callback function will be called by the can api interr upt handler and theref ore will execute on the interrupt level. 17.4.15 canopen sdo segme nted read callback the canopen sdo segmented read callback function is called by the canopen handler. the callback function allows the following actions: ? inform about the opening of the read channel. ? provide data segments of up to seven bytes to the reading host. ? close the channel when all data has been read. ? abort the transmission at any time. // values for canopen_sdo_seg_read/write() callback 'openclose' parameter #define can_sdoseg_segment 0 // segment read/write #define can_sdoseg_open 1 // channel is opened #define can_sdoseg_close 2 // channel is closed example call (reading a buffer): uint8_t read_buffer[0x123]; // canopen callback for segmented read accesses uint32_t canopen_sdo_seg_read( uint16_t index, uint8_t subindex, uint8_t openclose, uint8_t *length, uint8_t *data, uint8_t *last) { static uint16_t read_ofs; uint16_t i;
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 326 of 543 nxp semiconductors um10398 chapter 17: lpc11cxx c_can on-chip drivers if ((index == 0x2200) && (subindex==0)) { if (openclose == can_sdoseg_open) { // initialize the read buffer with "something" for (i=0; i um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 327 of 543 nxp semiconductors um10398 chapter 17: lpc11cxx c_can on-chip drivers #define can_sdoseg_segment 0 // segment read/write #define can_sdoseg_open 1 // channel is opened #define can_sdoseg_close 2 // channel is closed example call (writing a buffer): uint8_t write_buffer[0x321]; // canopen callback for segmented write accesses uint32_t canopen_sdo_seg_write( uint16_t index, uint8_t subindex, uint8_t openclose, uint8_t length, uint8_t *data, uint8_t *fast_resp) { static uint16_t write_ofs; uint16_t i; if ((index == 0x2200) && (subindex==0)) { if (openclose == can_sdoseg_open) { // initialize the write buffer for (i=0; i= sizeof(write_buffer))) // too much data to write { return sdo_abort_transfer; // data could not be written } } else if (openclose == can_sdoseg_close) { // write has successfully finished: mark the buffer valid etc. } return 0; } else { return sdo_abort_not_exists; } }
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 328 of 543 nxp semiconductors um10398 chapter 17: lpc11cxx c_can on-chip drivers remark: if the flag isr_handled wa s set true when initializing canopen, this callback function will be called by the can api interr upt handler and theref ore will execute on the interrupt level. 17.4.17 canopen fall-back sdo handler callback the canopen fall-back sdo handler callback function is called by the canopen handler. this function is called whenever an sdo requ est could not be processed or would end in an sdo abort response. it is ca lled with the full data buffer of the request and allows to generate any type of sdo response. this can be used to implement custom sdo handlers, for example to implement the sdo block transfer method. // return values for canopen_sdo_req() callback #define can_sdoreq_nothandled 0 // process regularly, no impact #define can_sdoreq_handled_send 1 // processed in callback, auto-send // returned msg #define can_sdoreq_handled_nosend 2 // processed in callback, don't send // response example call (not implementing custom processing): // canopen callback for custom sdo request handler uint8_t canopen_sdo_req ( uint8_t length, uint8_t *req_ptr, uint8_t *length_resp, uint8_t *resp_ptr) { return can_sdoreq_nothandled; } remark: if the flag isr_handled wa s set true when initializing canopen, this callback function will be called by the can api interr upt handler and theref ore will execute on the interrupt level.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 329 of 543 18.1 how to read this chapter the 16-bit timer blocks are identical for all lpc111x, lpc11d14, and lpc11cxx parts in the lpc1100, lpc1100c, and lpc1100l series. pin-out variations the match output mat0 of timer 1 (ct16b1_mat0) is not pinned out on parts lpc11c22 and lpc11c24. 18.2 basic configuration the ct16b0/1 are configured using the following registers: 1. pins: the ct16b0/1 pins must be co nfigured in the ioconfig register block ( section 7.4 ). 2. power and peripheral clock: in the sysah bclkctrl register, set bit 7 and bit 8 ( ta b l e 2 1 ). the peripheral clock is provided by the system clock (see ta b l e 2 0 ). 18.3 features ? two 16-bit counter/timers with a programmable 16-bit prescaler. ? counter or timer operation. ? one 16-bit capture channel that can take a snapshot of the timer value when an input signal transitions. a capture event may also optionally generate an interrupt. ? four 16-bit match registers that allow: ? continuous operation with optional interrupt generation on match. ? stop timer on match with optional interrupt generation. ? reset timer on match with optional interrupt generation. ? up to three (ct16b0) or two (ct16b1) external outputs corresponding to match registers with the fo llowing capabilities: ? set low on match. ? set high on match. ? toggle on match. ? do nothing on match. ? for each timer, up to four match registers can be configured as pwm allowing to use up to three match outputs as single edge controlled pwm outputs. um10398 chapter 18: lpc1100/lpc1100c/ lpc1100l series: 16-bit counter/timer ct16b0/1 rev. 12.1 ? 7 august 2013 user manual
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 330 of 543 nxp semiconductors um10398 chapter 18: lpc1100/lpc1100c/lpc1100l series: 16-bit counter/timer 18.4 applications ? interval timer for counting internal events ? pulse width demodulator via capture input ? free-running timer ? pulse width modulator via match outputs 18.5 description each counter/timer is designed to count cycl es of the peripheral clock (pclk) or an externally supplied clock and can optionally gene rate interrupts or perform other actions at specified timer values based on four match registers. the peripheral clock is provided by the system clock (see figure 8 ). each counter/timer also includes one capture input to trap the timer value when an input signal tr ansitions, optionally generating an interrupt. in pwm mode, three match registers on ct16 b0 and two match registers on ct16b1 can be used to provide a single-edge controlled pwm output on the match output pins. it is recommended to use the match registers that are not pinned out to control the pwm cycle length. remark: the 16-bit counter/timer0 (ct16b0) and the 16-bit counter/timer1 (ct16b1) are functionally identical except for the peripheral base address. 18.6 pin description table 279 gives a brief summary of each of the counter/timer related pins. 18.7 register description the 16-bit counter/timer0 contains the registers shown in table 280 and the 16-bit counter/timer1 contains the registers shown in table 281 . more detailed descriptions follow. table 279. counter/timer pin description pin type description ct16b0_cap0 ct16b1_cap0 input capture signal: a transition on a capture pin can be configured to load the capture register with the value in the counter/timer and optionally generate an interrupt. counter/timer block can select a capture signal as a clock source instead of the pclk derived clock. for more details see section 18.7.11 . ct16b0_mat[2:0] ct16b1_mat[1:0] output external match outputs of ct16b0/1: when a match register of ct16b0/1 (mr3:0) equals the timer counter (tc), this output can either toggle, go low, go high, or do nothing. the external match register (emr) and the pwm control register (pwm con) control the functionality of this output.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 331 of 543 nxp semiconductors um10398 chapter 18: lpc1100/lpc1100c/lpc1100l series: 16-bit counter/timer [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. table 280. register overview: 16-bit counte r/timer 0 ct16b0 (base address 0x4000 c000) name access address offset description reset value [1] tmr16b0ir r/w 0x000 interrupt register (ir). the ir can be written to clear interrupts. the ir can be read to identify which of fi ve possible interrupt sources are pending. 0 tmr16b0tcr r/w 0x004 timer control register (tcr). the tcr is used to control the timer counter functions. the timer counter can be disabled or reset through the tcr. 0 tmr16b0tc r/w 0x008 timer counte r (tc). the 16-bit tc is incr emented every pr+1 cycles of pclk. the tc is controlled through the tcr. 0 tmr16b0pr r/w 0x00c prescale register (pr). when the prescale counter (below) is equal to this value, the next clock increments the tc and clears the pc. 0 tmr16b0pc r/w 0x010 prescale counter (pc). the 16-bit pc is a counter which is incremented to the value stored in pr. when the value in pr is reached, the tc is incremented and the pc is cleared. the pc is observable and controllable through the bus interface. 0 tmr16b0mcr r/w 0x014 match control register (mcr). the mcr is used to control if an interrupt is generated and if the tc is reset when a match occurs. 0 tmr16b0mr0 r/w 0x018 match register 0 (mr0). mr0 can be enabled through the mcr to reset the tc, stop both the tc and pc, and/or generate an interrupt every time mr0 matches the tc. 0 tmr16b0mr1 r/w 0x01c match register 1 (mr1). see mr0 description. 0 tmr16b0mr2 r/w 0x020 match register 2 (mr2). see mr0 description. 0 tmr16b0mr3 r/w 0x024 match register 3 (mr3). see mr0 description. 0 tmr16b0ccr r/w 0x028 capture control register (ccr). the ccr controls which edges of the capture inputs are used to load the capture registers and whether or not an interrupt is generated when a capture takes place. 0 tmr16b0cr0 ro 0x02c capture register 0 (cr0). cr0 is loaded with the value of tc when there is an event on the ct16b0_cap0 input. 0 tmr16b0emr r/w 0x03c external match register (emr). the emr controls the match function and the external match pins ct16b0_mat[2:0]. 0 - - 0x040 - 0x06c reserved - tmr16b0ctcr r/w 0x070 count control register (ctcr). the ctcr selects between timer and counter mode, and in counter mode selects the signal and edge(s) for counting. 0 tmr16b0pwmc r/w 0x074 pwm control register (pwmcon). the pwmcon enables pwm mode for the external match pins ct16b0_mat[2:0]. 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 332 of 543 nxp semiconductors um10398 chapter 18: lpc1100/lpc1100c/lpc1100l series: 16-bit counter/timer [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. 18.7.1 interrupt register (tmr16b0ir and tmr16b1ir) the interrupt register (ir) consists of four bits for the match interrupts and one bit for the capture interrupt. if an interrupt is g enerated then the corresponding bit in the ir will be high. otherwise, the bit will be low. writing a logic one to the corresponding ir bit will reset the interrupt. writing a zero has no effect. table 281. register overview: 16-bit counter/timer 1 ct16b1 (base address 0x4001 0000) name access address offset description reset value [1] tmr16b1ir r/w 0x000 interrupt register (ir). the ir can be written to clear interrupts. the ir can be read to identify which of five possible interrupt sources are pending. 0 tmr16b1tcr r/w 0x004 timer control register (tcr). the tcr is used to control the timer counter functions. the timer counter can be disabled or reset through the tcr. 0 tmr16b1tc r/w 0x008 timer counter (tc). the 16-bit tc is incremented every pr+1 cycles of pclk. the tc is controlled through the tcr. 0 tmr16b1pr r/w 0x00c prescale register (pr). when the prescale counter (below) is equal to this value, the next clock increments the tc and clears the pc. 0 tmr16b1pc r/w 0x010 prescale counter (pc). the 16 -bit pc is a counter which is incremented to the value stored in pr. when the value in pr is reached, the tc is incremented and the pc is cleared. the pc is observable and controllable through the bus interface. 0 tmr16b1mcr r/w 0x014 match control register (mcr). the mcr is used to control if an interrupt is generated and if the tc is reset when a match occurs. 0 tmr16b1mr0 r/w 0x018 match register 0 (mr0). mr 0 can be enabled through the mcr to reset the tc, stop both the tc and pc, and/or generate an interrupt every time mr0 matches the tc. 0 tmr16b1mr1 r/w 0x01c match register 1 (mr1). see mr0 description. 0 tmr16b1mr2 r/w 0x020 match register 2 (mr2). see mr0 description. 0 tmr16b1mr3 r/w 0x024 match register 3 (mr3). see mr0 description. 0 tmr16b1ccr r/w 0x028 capture control register (ccr). the ccr controls which edges of the capture inputs are used to load the capture registers and whether or not an interrupt is generated when a capture takes place. 0 tmr16b1cr0 ro 0x02c capture register 0 (cr0). cr0 is loaded with the value of tc when there is an event on the ct16b1_cap0 input. 0 tmr16b1emr r/w 0x03c external match register (e mr). the emr controls the match function and the external match pins ct16b1_mat[1:0]. 0 - - 0x040 - 0x06c reserved - tmr16b1ctcr r/w 0x070 count control register (ctcr). the ctcr selects between timer and counter mode, and in counter mode selects the signal and edge(s) for counting. 0 tmr16b1pwmc r/w 0x074 pwm control register (pwmcon). the pwmcon enables pwm mode for the external match pins ct16b1_mat[1:0]. 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 333 of 543 nxp semiconductors um10398 chapter 18: lpc1100/lpc1100c/lpc1100l series: 16-bit counter/timer 18.7.2 timer control register (tmr16b0tcr and tmr16b1tcr) the timer control register (tcr) is used to control the operation of the counter/timer. 18.7.3 timer counter (tmr16b0 tc - address 0x4000 c008 and tmr16b1tc - address 0x4001 0008) the 16-bit timer counter is incremented when the prescale counter reaches its terminal count. unless it is reset be fore reaching its upper limit, th e tc will count up through the value 0x0000 ffff and then wrap back to the value 0x0000 0000. this event does not cause an interrupt, but a match register can be used to detect an overflow if needed. 18.7.4 prescale register (tmr 16b0pr - address 0x4000 c00c and tmr16b1pr - address 0x4001 000c) the 16-bit prescale register specifies the maximum value for the prescale counter. table 282. interrupt register (tmr16b0ir - address 0x4000 c000 and tmr16b1ir - address 0x4001 0000) bit description bit symbol description reset value 0 mr0 interrupt interrupt flag for match channel 0. 0 1 mr1 interrupt interrupt flag for match channel 1. 0 2 mr2 interrupt interrupt flag for match channel 2. 0 3 mr3 interrupt interrupt flag for match channel 3. 0 4 cr0 interrupt interrupt flag for capture channel 0 event. 0 31:5 - reserved - table 283. timer control register (tmr16b0tcr - address 0x4000 c004 and tmr16b1tcr - address 0x4001 0004) bit description bit symbol description reset value 0 cen counter enable. when one, the timer counter and prescale counter are enabled for counting. when zero, the counters are disabled. 0 1 crst counter reset. when one, the timer counter and the prescale counter are synchronously reset on the next positive edge of pclk. the counters remain reset until tcr[1] is returned to zero. 0 31:2 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na table 284: timer counter registers (tmr16b0tc, address 0x4000 c008 and tmr16b1tc 0x4001 0008) bit description bit symbol description reset value 15:0 tc timer counter value. 0 31:16 - reserved. -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 334 of 543 nxp semiconductors um10398 chapter 18: lpc1100/lpc1100c/lpc1100l series: 16-bit counter/timer 18.7.5 prescale counter register (tmr16b0pc - addr ess 0x4000 c010 and tmr16b1pc - address 0x4001 0010) the 16-bit prescale counter controls division of pclk by some constant value before it is applied to the timer counter. this allows control of the relationship between the resolution of the timer and the maximum time before t he timer overflows. the prescale counter is incremented on every pclk. when it reaches the value stored in the prescale register, the timer counter is incremented, and the prescale counter is reset on the next pclk. this causes the tc to increment on every pclk when pr = 0, every 2 pclks when pr = 1, etc. 18.7.6 match control register (tmr16b0mcr and tmr16b1mcr) the match control register is used to contro l what operations are performed when one of the match registers matches the timer counter. the function of each of the bits is shown in table 287 . table 285: prescale registers (tmr16b0pr, address 0x4000 c00c and tmr16b1pr 0x4001 000c) bit description bit symbol description reset value 15:0 pr prescale max value. 0 31:16 - reserved. - table 286: prescale counter registers (tmr16b0pc, address 0x4001 c010 and tmr16b1pc 0x4000 0010) bit description bit symbol description reset value 15:0 pc prescale counter value. 0 31:16 - reserved. - table 287. match control register (tmr16b0mcr - address 0x4000 c014 and tmr16b1mcr - address 0x4001 0014) bit description bit symbol value description reset value 0 mr0i interrupt on mr0: an interrupt is ge nerated when mr0 matches the value in the tc. 0 1 enabled 0 disabled 1 mr0r reset on mr0: the tc will be reset if mr0 matches it. 0 1 enabled 0 disabled 2 mr0s stop on mr0: the tc and pc will be stopped and tcr[0] will be set to 0 if mr0 matches the tc. 0 1 enabled 0 disabled 3 mr1i interrupt on mr1: an interrupt is ge nerated when mr1 matches the value in the tc. 0 1 enabled 0 disabled
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 335 of 543 nxp semiconductors um10398 chapter 18: lpc1100/lpc1100c/lpc1100l series: 16-bit counter/timer 18.7.7 match registers (tmr 16b0mr0/1/2/3 - addresses 0x4000 c018/1c/20/24 and tmr16b1m r0/1/2/3 - addresses 0x4001 0018/1c/20/24) the match register values are continuously compared to the timer counter value. when the two values are equal, acti ons can be triggere d automatically. the action possibilities are to generate an interrupt, reset the timer counter, or stop the timer. actions are controlled by the settings in the mcr register. 4 mr1r reset on mr1: the tc will be reset if mr1 matches it. 0 1 enabled 0 disabled 5 mr1s stop on mr1: the tc and pc will be stopped and tcr[0] will be set to 0 if mr1 matches the tc. 0 1 enabled 0 disabled 6 mr2i interrupt on mr2: an interrupt is ge nerated when mr2 matches the value in the tc. 0 1 enabled 0 disabled 7 mr2r reset on mr2: the tc will be reset if mr2 matches it. 0 1 enabled 0 disabled 8 mr2s stop on mr2: the tc and pc will be stopped and tcr[0] will be set to 0 if mr2 matches the tc. 0 1 enabled 0 disabled 9 mr3i interrupt on mr3: an interrupt is ge nerated when mr3 matches the value in the tc. 0 1 enabled 0 disabled 10 mr3r reset on mr3: the tc will be reset if mr3 matches it. 0 1 enabled 0 disabled 11 mr3s stop on mr3: the tc and pc will be stopped and tcr[0] will be set to 0 if mr3 matches the tc. 0 1 enabled 0 disabled 31:12 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na table 287. match control register (tmr16b0mcr - address 0x4000 c014 and tmr16b1mcr - address 0x4001 0014) bit description ?continued bit symbol value description reset value
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 336 of 543 nxp semiconductors um10398 chapter 18: lpc1100/lpc1100c/lpc1100l series: 16-bit counter/timer 18.7.8 capture control register (tmr16b0ccr and tmr16b1ccr) the capture control register is used to control whether the capture register is loaded with the value in the counter/timer when the capture event occurs, and whether an interrupt is gene rated by the captur e event. setting bo th the rising and falling bits at the same time is a valid configuration, resulting in a capture event for both edges. in the description below, n represents the timer number, 0 or 1. 18.7.9 capture register (ct16b 0cr0 - address 0x4000 c02c and ct16b1cr0 - address 0x4001 002c) each capture register is associated with a device pin and may be loaded with the counter/timer value when a specified event occurs on that pin. the settings in the capture control register register determine whether the capture function is enabled, and whether a capture event happens on the rising edge of the associated pin, the falling edge, or on both edges. table 288: match registers (tmr16b0mr0 to 3, addresses 0x4000 c018 to 24 and tmr16b1mr0 to 3, addresses 0x4001 0018 to 24) bit description bit symbol description reset value 15:0 match timer counter match value. 0 31:16 - reserved. - table 289. capture control register (tmr16b0ccr - address 0x4000 c028 and tmr16b1ccr - address 0x4001 0028) bit description bit symbol value description reset value 0 cap0re capture on ct16bn_cap0 rising edge: a sequence of 0 then 1 on ct16bn_cap0 will cause cr0 to be loaded with the contents of tc. 0 1 enabled 0 disabled 1 cap0fe capture on ct16bn_cap0 falling edge: a sequence of 1 then 0 on ct16bn_cap0 will cause cr0 to be loaded with the contents of tc. 0 1 enabled 0 disabled 2 cap0i interrupt on ct16bn_cap0 event: a cr0 load due to a ct16bn_cap0 event will generate an interrupt. 0 1 enabled 0 disabled 31:3 - - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na table 290: capture registers (tmr16b0cr0, address 0x4000 c02c and tmr16b1cr0, address 0x4001 002c) bit description bit symbol description reset value 15:0 cap timer counter capture value. 0 31:16 - reserved. -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 337 of 543 nxp semiconductors um10398 chapter 18: lpc1100/lpc1100c/lpc1100l series: 16-bit counter/timer 18.7.10 external match register (tmr16b0emr and tmr16b1emr) the external match register provides both control and status of the external match channels and external match pins ct16b0_mat[2:0] and ct16b1_mat[1:0]. if the match outputs are configured as pwm output in the pwmcon registers ( section 18.7.12 ), the function of the external matc h registers is determined by the pwm rules ( section 18.7.13 rules for single edge controlled pwm outputs on page 340 ). table 291. external match register (tmr16b0emr - address 0x4000 c03c and tmr16b1emr - address 0x4001 003c) bit description bit symbol value description reset value 0 em0 external match 0. this bit reflects the state of output ct16b0_mat0/ct16b1_mat0, whether or not this output is connected to its pin. when a match occurs between the tc and mr0, this bit can either toggle, go low, go high, or do nothing. bits emr[5:4] control the functionality of this ou tput. this bit is driven to the ct16b0_mat0/ct16b1_mat0 pins if the ma tch function is selected in the iocon registers (0 = low, 1 = high). 0 1 em1 external match 1. this bit reflects the state of output ct16b0_mat1/ct16b1_mat1, whether or not this output is connected to its pin. when a match occurs between the tc and mr1, this bit can either toggle, go low, go high, or do nothing. bits emr[7:6] control the functionality of this ou tput. this bit is driven to the ct16b0_mat1/ct16b1_mat1 pins if the ma tch function is selected in the iocon registers (0 = low, 1 = high). 0 2 em2 external match 2. this bit reflects the st ate of output match chan nel 2, whether or not this output is connected to its pin. when a match occurs between the tc and mr2, this bit can either toggle, go low, go high, or do nothing. bits em r[9:8] control the functionality of this output. no te that on counter/timer 0 this match channel is not pinned out. this bit is driven to the ct16b1_mat2 pi n if the match function is selected in the iocon registers (0 = low, 1 = high). 0 3 em3 external match 3. this bit reflects the st ate of output of match channel 3. when a match occurs between the tc and mr3, this bit can either toggle, go low, go high, or do nothing. bits emr[11:10] control the functionality of this out put. there is no output pin available for this channel on either of the 16-bit timers. 0 5:4 emc0 external match control 0. determines the functional ity of external match 0. 00 0x0 do nothing. 0x1 clear the corresponding external match bi t/output to 0 (ct16bn_matm pin is low if pinned out). 0x2 set the corresponding external match bit/ output to 1 (ct16bn_matm pin is high if pinned out). 0x3 toggle the corresponding external match bit/output. 7:6 emc1 external match control 1. determines the functional ity of external match 1. 00 0x0 do nothing. 0x1 clear the corresponding external match bi t/output to 0 (ct16bn_matm pin is low if pinned out). 0x2 set the corresponding external match bit/ output to 1 (ct16bn_matm pin is high if pinned out). 0x3 toggle the corresponding external match bit/output.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 338 of 543 nxp semiconductors um10398 chapter 18: lpc1100/lpc1100c/lpc1100l series: 16-bit counter/timer 18.7.11 count control register (tmr16b0ctcr and tmr16b1ctcr) the count control register (ctcr) is used to select between timer and counter mode, and in counter mode to select the pin and edges for counting. when counter mode is chosen as a mode of operation, the cap input (selected by the ctcr bits 3:2) is sampled on every rising edge of the pclk clock. after comparing two consecutive samples of this cap input, one of the following four events is recognized: rising edge, falling edge, either of edges or no changes in th e level of the selected cap input. only if the identified event occurs, and the event corresponds to the one selected by bits 1:0 in the ctcr register, will the timer counter regist er be incremented. effective processing of the externally supplie d clock to the counter has some limitations. since two successive rising edges of the pclk clock are used to identify only one edge on the cap selected input, the frequency of th e cap input can not exceed one half of the pclk clock. consequently, duration of the high/low levels on the same cap input in this case can not be shorter than 1/(2 ? pclk). 9:8 emc2 external match control 2. determines the functional ity of external match 2. 00 0x0 do nothing. 0x1 clear the corresponding external match bi t/output to 0 (ct16bn_matm pin is low if pinned out). 0x2 set the corresponding external match bit/ output to 1 (ct16bn_matm pin is high if pinned out). 0x3 toggle the corresponding external match bit/output. 11:10 emc3 external match control 3. determines the functional ity of external match 3. 00 0x0 do nothing. 0x1 clear the corresponding external match bi t/output to 0 (ct16bn_matm pin is low if pinned out). 0x2 set the corresponding external match bit/ output to 1 (ct16bn_matm pin is high if pinned out). 0x3 toggle the corresponding external match bit/output. 31:12 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na table 291. external match register (tmr16b0emr - address 0x4000 c03c and tmr16b1emr - address 0x4001 003c) bit description bit symbol value description reset value table 292. external match control emr[11:10], emr[9:8], emr[7:6], or emr[5:4] function 00 do nothing. 01 clear the corresponding external match bit/ou tput to 0 (ct16bn_matm pin is low if pinned out). 10 set the corresponding external match bit/output to 1 (ct16bn_matm pin is high if pinned out). 11 toggle the corresponding external match bit/output.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 339 of 543 nxp semiconductors um10398 chapter 18: lpc1100/lpc1100c/lpc1100l series: 16-bit counter/timer 18.7.12 pwm control register (tmr16b0pwmc and tmr16b1pwmc) the pwm control register is used to config ure the match outputs as pwm outputs. each match output can be independently set to pe rform either as pwm output or as match output whose function is controlled by the external match register (emr). for timer 0, three single-edge controlled pwm outputs can be selected on the ct16b0_mat[2:0] outputs. for timer 1, two single-edged pwm outputs can be selected on the ct16b1_mat[1:0] outputs. one additi onal match register determines the pwm cycle length. when a match occurs in any of th e other match registers, the pwm output is set to high. the timer is reset by the match register that is conf igured to set the pwm cycle length. when the timer is reset to zero, all currently high match outputs configured as pwm outputs are cleared. table 293. count control register (tmr16b0ctcr - address 0x4000 c070 and tmr16b1ctcr - address 0x4001 0070) bit description bit symbol value description reset value 1:0 ctm counter/timer mode. this field selects which rising pclk edges can increment timers prescale counter (pc), or clear pc and increment ti mer counter (tc). 00 0x0 timer mode: every rising pclk edge 0x1 counter mode: tc is incremented on rising edges on the cap input selected by bits 3:2. 0x2 counter mode: tc is incremented on falling edges on the cap input selected by bits 3:2. 0x3 counter mode: tc is incremented on both edges on the cap input selected by bits 3:2. 3:2 cis count input select. in counter mode (when bits 1:0 in this register are not 00), these bits select which cap pin is sampled for clocking. note: if counter mode is selected in the ctcr register, bits 2:0 in the capture control register (ccr) must be programmed as 000. 00 0x0 ct16bn_cap0 0x1 ct16bn_cap1 0x2 reserved. 0x3 reserved. 31:4 - - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - table 294. pwm control register (tmr16b0pwmc - address 0x4000 c074 and tmr16b1pwmc- address 0x4001 0074) bit description bit symbol value description reset value 0 pwmen0 pwm channel0 enable 0 0 ct16bn_mat0 is controlled by em0. 1 pwm mode is enabled for ct16bn_mat0.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 340 of 543 nxp semiconductors um10398 chapter 18: lpc1100/lpc1100c/lpc1100l series: 16-bit counter/timer 18.7.13 rules for single e dge controlled pwm outputs 1. all single edge controlled pwm outputs go low at the beginning of each pwm cycle (timer is set to zero) unless their match value is equal to zero. 2. each pwm output will go high when its matc h value is reached. if no match occurs (i.e. the match value is greater than the pwm cycle length), the pwm output remains continuously low. 3. if a match value larger than the pwm cycle length is written to the match register, and the pwm signal is high already, then the pwm signal will be cleared on the next start of the next pwm cycle. 4. if a match register contains the same value as the timer reset value (the pwm cycle length), then the pwm output will be reset to low on the next clock tick. therefore, the pwm output will always consist of a one clock tick wide positive pulse with a period determined by the pwm cycle length (i.e. the timer reload value). 5. if a match register is set to zero, then the pwm output will go to high the first time the timer goes back to zero and will stay high continuously. note: when the match outputs are selected to serve as pwm outputs, the timer reset (mrnr) and timer stop (mrns) bits in the match control register mcr must be set to 0 except for the match register setting the pwm cycle length. for th is register, set the mrnr bit to 1 to enable the timer reset w hen the timer value matches the value of the corresponding match register. 1 pwmen1 pwm channel1 enable 0 0 ct16bn_mat1 is controlled by em1. 1 pwm mode is enabled for ct16bn_mat1. 2 pwmen2 pwm channel2 enable 0 0 match channel 2 or pin ct16b0_mat2 is controlled by em2. match channel 2 is not pinned out on timer 1. 1 pwm mode is enabled for match channel 2 or pin ct16b0_mat2. 3 pwmen3 pwm channel3 enable note: it is recommended to use match channel 3 to set the pwm cycle because it is not pinned out. 0 0 match channel 3 match channel 3 is controlled by em3. 1 pwm mode is enabled for match channel 3match channel 3. 31:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na table 294. pwm control register (tmr16b0pwmc - address 0x4000 c074 and tmr16b1pwmc- address 0x4001 0074) bit description bit symbol value description reset value
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 341 of 543 nxp semiconductors um10398 chapter 18: lpc1100/lpc1100c/lpc1100l series: 16-bit counter/timer 18.8 example timer operation figure 70 shows a timer configured to reset the count and generate an interrupt on match. the prescaler is set to 2 and the match register set to 6. at the end of the timer cycle where the match occurs, the timer count is re set. this gives a full length cycle to the match value. the interrupt indicating that a ma tch occurred is generated in the next clock after the timer reached the match value. figure 71 shows a timer configured to stop and generate an interrupt on match. the prescaler is again set to 2 and the match register set to 6. in the next clock after the timer reaches the match value, the timer enable bit in tcr is cleare d, and the interrupt indicating that a match occurred is generated. fig 69. sample pwm waveforms with a pwm cycl e length of 100 (selected by mr2) and mat2:0 enabled as pwm outputs by the pwcm register. 100 (counter is reset) 04165 pwm0/mat0 pwm1/mat1 pwm2/mat2 mr2 = 100 mr1 = 41 mr0 = 65 fig 70. a timer cycle in which pr =2, mrx=6, and both interrupt and reset on match are enabled pclk prescale counter interrupt timer counter timer counter reset 2 2 2 2000 0 1111 45 6 0 1 fig 71. a timer cycle in which pr=2, mrx=6, and both interrupt and stop on match are enabled pclk prescale counter interrupt timer counter tcr[0] (counter enable) 2 20 0 1 45 6 1 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 342 of 543 nxp semiconductors um10398 chapter 18: lpc1100/lpc1100c/lpc1100l series: 16-bit counter/timer 18.9 architecture the block diagram for counter/timer0 and counter/timer1 is shown in figure 72 . fig 72. 16-bit counter/ timer block diagram reset maxval timer control register prescale register prescale counter pclk enable capture register 0 match register 3 match register 2 match register 1 match register 0 capture control register control timer counter csn tci ce = = = = interrupt register external match register match control register matn[2:0] interrupt cap0 stop on match reset on match load[3:0]
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 343 of 543 19.1 how to read this chapter the 16-bit timer blocks are identical for all lpc1100xl parts. compared to the timer block for the lpc1100/lpc1100l/lpc1100c series, the following features have been added: ? one additional capture input for each timer. ? capture-clear function for easy pulse-width measurement (see section 19.7.11 ). 19.2 basic configuration the ct16b0/1 are configured using the following registers: 1. pins: the ct16b0/1 pins must be co nfigured in the ioconfig register block ( section 7.4 ). 2. power and peripheral clock: in the sysah bclkctrl register, set bit 7 and bit 8 ( ta b l e 2 1 ). the peripheral clock is provided by the system clock (see ta b l e 2 0 ). 19.3 features ? two 16-bit counter/timers with a programmable 16-bit prescaler. ? counter or timer operation. ? the timer and prescaler may be configured to be cleared on a designated capture event. this feature permits easy pulse-width measurement by clearing the timer on the leading edge of an input pulse and capt uring the timer value on the trailing edge. ? two 16-bit capture channels that can take a snapshot of the timer value when an input signal transitions. a capture event may also optionally generate an interrupt. ? four 16-bit match registers that allow: ? continuous operation with optional interrupt generation on match. ? stop timer on match with optional interrupt generation. ? reset timer on match with optional interrupt generation. ? up to three (ct16b0) or two (ct16b1) external outputs corresponding to match registers with the fo llowing capabilities: ? set low on match. ? set high on match. ? toggle on match. ? do nothing on match. ? for each timer, up to four match registers can be configured as pwm allowing to use up to three match outputs as single edge controlled pwm outputs. um10398 chapter 19: lpc1100xl series: 16-bit counter/timer ct16b0/1 rev. 12.1 ? 7 august 2013 user manual
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 344 of 543 nxp semiconductors um10398 chapter 19: lpc1100xl series: 16-bit counter/timer ct16b0/1 19.4 applications ? interval timer for counting internal events ? pulse width demodulator via capture input ? free-running timer ? pulse width modulator via match outputs 19.5 description each counter/timer is designed to count cycl es of the peripheral clock (pclk) or an externally supplied clock and can optionally gene rate interrupts or perform other actions at specified timer values based on four match registers. the peripheral clock is provided by the system clock (see figure 8 ). each counter/timer also includes one capture input to trap the timer value when an input signal tr ansitions, optionally generating an interrupt. in pwm mode, three match registers on ct16 b0 and two match registers on ct16b1 can be used to provide a single-edge controlled pwm output on the match output pins. it is recommended to use the match registers that are not pinned out to control the pwm cycle length. remark: the 16-bit counter/timer0 (ct16b0) and the 16-bit counter/timer1 (ct16b1) are functionally identical except for the peripheral base address. 19.6 pin description table 295 gives a brief summary of each of the counter/timer related pins. 19.7 register description the 16-bit counter/timer0 contains the registers shown in table 296 and the 16-bit counter/timer1 contains the registers shown in table 297 . more detailed descriptions follow. table 295. counter/timer pin description pin type description ct16b0_cap[1:0] ct16b1_cap0[1:0] input capture signal: a transition on a capture pin can be configured to load the capture register with the value in the counter/timer and optionally generate an interrupt. counter/timer block can select a capture signal as a clock source instead of the pclk derived clock. for more details see section 19.7.11 . ct16b0_mat[2:0] ct16b1_mat[1:0] output external match outputs of ct16b0/1: when a match register of ct16b0/1 (mr3:0) equals the timer counter (tc), this output can either toggle, go low, go high, or do nothing. the external match register (emr) and the pwm control register (pwm con) control the functionality of this output.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 345 of 543 nxp semiconductors um10398 chapter 19: lpc1100xl series: 16-bit counter/timer ct16b0/1 [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. table 296. register overview: 16-bit counte r/timer 0 ct16b0 (base address 0x4000 c000) name access address offset description reset value [1] tmr16b0ir r/w 0x000 interrupt register (ir). the ir can be written to clear interrupts. the ir can be read to identify which of fi ve possible interrupt sources are pending. 0 tmr16b0tcr r/w 0x004 timer control register (tcr). the tcr is used to control the timer counter functions. the timer counter can be disabled or reset through the tcr. 0 tmr16b0tc r/w 0x008 timer counte r (tc). the 16-bit tc is incr emented every pr+1 cycles of pclk. the tc is controlled through the tcr. 0 tmr16b0pr r/w 0x00c prescale register (pr). when the prescale counter (below) is equal to this value, the next clock increments the tc and clears the pc. 0 tmr16b0pc r/w 0x010 prescale counter (pc). the 16-bit pc is a counter which is incremented to the value stored in pr. when the value in pr is reached, the tc is incremented and the pc is cleared. the pc is observable and controllable through the bus interface. 0 tmr16b0mcr r/w 0x014 match control register (mcr). the mcr is used to control if an interrupt is generated and if the tc is reset when a match occurs. 0 tmr16b0mr0 r/w 0x018 match register 0 (mr0). mr0 can be enabled through the mcr to reset the tc, stop both the tc and pc, and/or generate an interrupt every time mr0 matches the tc. 0 tmr16b0mr1 r/w 0x01c match register 1 (mr1). see mr0 description. 0 tmr16b0mr2 r/w 0x020 match register 2 (mr2). see mr0 description. 0 tmr16b0mr3 r/w 0x024 match register 3 (mr3). see mr0 description. 0 tmr16b0ccr r/w 0x028 capture control register (ccr). the ccr controls which edges of the capture inputs are used to load the capture registers and whether or not an interrupt is generated when a capture takes place. 0 tmr16b0cr0 ro 0x02c capture register 0 (cr0). cr0 is loaded with the value of tc when there is an event on the ct16b0_cap0 input. 0 tmr16b0cr1 ro 0x030 capture register 1 (cr1). cr1 is loaded with the value of tc when there is an event on the ct16b0_cap1 input. 0 - - 0x034 - 0x038 reserved - tmr16b0emr r/w 0x03c external match register (emr). the emr controls the match function and the external match pins ct16b0_mat[2:0]. 0 - - 0x040 - 0x06c reserved - tmr16b0ctcr r/w 0x070 count control register (ctcr). the ctcr selects between timer and counter mode, and in counter mode selects the signal and edge(s) for counting. 0 tmr16b0pwmc r/w 0x074 pwm control register (pwmcon). the pwmcon enables pwm mode for the external match pins ct16b0_mat[2:0]. 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 346 of 543 nxp semiconductors um10398 chapter 19: lpc1100xl series: 16-bit counter/timer ct16b0/1 [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. table 297. register overview: 16-bit counter/timer 1 ct16b1 (base address 0x4001 0000) name access address offset description reset value [1] tmr16b1ir r/w 0x000 interrupt register (ir). the ir can be written to clear interrupts. the ir can be read to identify which of five possible interrupt sources are pending. 0 tmr16b1tcr r/w 0x004 timer control register (tcr). the tcr is used to control the timer counter functions. the timer counter can be disabled or reset through the tcr. 0 tmr16b1tc r/w 0x008 timer counter (tc). the 16-bit tc is incremented every pr+1 cycles of pclk. the tc is controlled through the tcr. 0 tmr16b1pr r/w 0x00c prescale register (pr). when the prescale counter (below) is equal to this value, the next clock increments the tc and clears the pc. 0 tmr16b1pc r/w 0x010 prescale counter (pc). the 16 -bit pc is a counter which is incremented to the value stored in pr. when the value in pr is reached, the tc is incremented and the pc is cleared. the pc is observable and controllable through the bus interface. 0 tmr16b1mcr r/w 0x014 match control register (mcr). the mcr is used to control if an interrupt is generated and if the tc is reset when a match occurs. 0 tmr16b1mr0 r/w 0x018 match register 0 (mr0). mr 0 can be enabled through the mcr to reset the tc, stop both the tc and pc, and/or generate an interrupt every time mr0 matches the tc. 0 tmr16b1mr1 r/w 0x01c match register 1 (mr1). see mr0 description. 0 tmr16b1mr2 r/w 0x020 match register 2 (mr2). see mr0 description. 0 tmr16b1mr3 r/w 0x024 match register 3 (mr3). see mr0 description. 0 tmr16b1ccr r/w 0x028 capture control register (ccr). the ccr controls which edges of the capture inputs are used to load the capture registers and whether or not an interrupt is generated when a capture takes place. 0 tmr16b1cr0 ro 0x02c capture register 0 (cr0). cr0 is loaded with the value of tc when there is an event on the ct16b1_cap0 input. 0 tmr16b1cr1 ro 0x030 capture register 1 (cr1). cr1 is loaded with the value of tc when there is an event on the ct16b1_cap1 input. 0 - - 0x034 - 0x038 reserved - tmr16b1emr r/w 0x03c external match register (e mr). the emr controls the match function and the external match pins ct16b1_mat[1:0]. 0 - - 0x040 - 0x06c reserved - tmr16b1ctcr r/w 0x070 count control register (ctcr). the ctcr selects between timer and counter mode, and in counter mode selects the signal and edge(s) for counting. 0 tmr16b1pwmc r/w 0x074 pwm control register (pwmcon). the pwmcon enables pwm mode for the external match pins ct16b1_mat[1:0]. 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 347 of 543 nxp semiconductors um10398 chapter 19: lpc1100xl series: 16-bit counter/timer ct16b0/1 19.7.1 interrupt register (tmr16b0ir and tmr16b1ir) the interrupt register (ir) consists of four bits for the match interrupts and one bit for the capture interrupt. if an interrupt is g enerated then the corresponding bit in the ir will be high. otherwise, the bit will be low. writing a logic one to the corresponding ir bit will reset the interrupt. writing a zero has no effect. 19.7.2 timer control register (tmr16b0tcr and tmr16b1tcr) the timer control register (tcr) is used to control the operation of the counter/timer. 19.7.3 timer counter (tmr16b0 tc - address 0x4000 c008 and tmr16b1tc - address 0x4001 0008) the 16-bit timer counter is incremented when the prescale counter reaches its terminal count. unless it is reset be fore reaching its upper limit, th e tc will count up through the value 0x0000 ffff and then wrap back to the value 0x0000 0000. this event does not cause an interrupt, but a match register can be used to detect an overflow if needed. table 298. interrupt register (tmr16b0ir - address 0x4000 c000 and tmr16b1ir - address 0x4001 0000) bit description bit symbol description reset value 0 mr0int interrupt flag for match channel 0. 0 1 mr1int interrupt flag for match channel 1. 0 2 mr2int interrupt flag for match channel 2. 0 3 mr3int interrupt flag for match channel 3. 0 4 cr0int interrupt flag for capture channel 0 event. 0 5 cr1int interrupt flag for capture channel 1 event. 0 31:6 - reserved - table 299. timer control register (tmr16b0tcr - address 0x4000 c004 and tmr16b1tcr - address 0x4001 0004) bit description bit symbol description reset value 0 cen counter enable. when one, the timer counter and prescale counter are enabled for counting. when zero, the counters are disabled. 0 1 crst counter reset. when one, the timer counter and the prescale counter are synchronously reset on the next positive edge of pclk. the counters remain reset until tcr[1] is returned to zero. 0 31:2 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na table 300: timer counter registers (tmr16b0tc, address 0x4000 c008 and tmr16b1tc 0x4001 0008) bit description bit symbol description reset value 15:0 tc timer counter value. 0 31:16 - reserved. -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 348 of 543 nxp semiconductors um10398 chapter 19: lpc1100xl series: 16-bit counter/timer ct16b0/1 19.7.4 prescale register (tmr 16b0pr - address 0x4000 c00c and tmr16b1pr - address 0x4001 000c) the 16-bit prescale register specifies the maximum value for the prescale counter. 19.7.5 prescale counter register (tmr16b0pc - addr ess 0x4000 c010 and tmr16b1pc - address 0x4001 0010) the 16-bit prescale counter controls division of pclk by some constant value before it is applied to the timer counter. this allows control of the relationship between the resolution of the timer and the maximum time before t he timer overflows. the prescale counter is incremented on every pclk. when it reaches the value stored in the prescale register, the timer counter is incremented, and the prescale counter is reset on the next pclk. this causes the tc to increment on every pclk when pr = 0, every 2 pclks when pr = 1, etc. 19.7.6 match control register (tmr16b0mcr and tmr16b1mcr) the match control register is used to contro l what operations are performed when one of the match registers matches the timer counter. the function of each of the bits is shown in table 303 . table 301: prescale registers (tmr16b0pr, address 0x4000 c00c and tmr16b1pr 0x4001 000c) bit description bit symbol description reset value 15:0 pr prescale max value. 0 31:16 - reserved. - table 302: prescale counter registers (tmr16b0pc, address 0x4001 c010 and tmr16b1pc 0x4000 0010) bit description bit symbol description reset value 15:0 pc prescale counter value. 0 31:16 - reserved. - table 303. match control register (tmr16b0mcr - address 0x4000 c014 and tmr16b1mcr - address 0x4001 0014) bit description bit symbol value description reset value 0 mr0i interrupt on mr0: an interrupt is ge nerated when mr0 matches the value in the tc. 0 1 enabled 0 disabled 1 mr0r reset on mr0: the tc will be reset if mr0 matches it. 0 1 enabled 0 disabled 2 mr0s stop on mr0: the tc and pc will be stopped and tcr[0] will be set to 0 if mr0 matches the tc. 0 1 enabled 0 disabled
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 349 of 543 nxp semiconductors um10398 chapter 19: lpc1100xl series: 16-bit counter/timer ct16b0/1 19.7.7 match registers (tmr 16b0mr0/1/2/3 - addresses 0x4000 c018/1c/20/24 and tmr16b1m r0/1/2/3 - addresses 0x4001 0018/1c/20/24) the match register values are continuously compared to the timer counter value. when the two values are equal, acti ons can be triggere d automatically. the action possibilities are to generate an interrupt, reset the timer counter, or stop the timer. actions are controlled by the settings in the mcr register. 3 mr1i interrupt on mr1: an interrupt is ge nerated when mr1 matches the value in the tc. 0 1 enabled 0 disabled 4 mr1r reset on mr1: the tc will be reset if mr1 matches it. 0 1 enabled 0 disabled 5 mr1s stop on mr1: the tc and pc will be stopped and tcr[0] will be set to 0 if mr1 matches the tc. 0 1 enabled 0 disabled 6 mr2i interrupt on mr2: an interrupt is ge nerated when mr2 matches the value in the tc. 0 1 enabled 0 disabled 7 mr2r reset on mr2: the tc will be reset if mr2 matches it. 0 1 enabled 0 disabled 8 mr2s stop on mr2: the tc and pc will be stopped and tcr[0] will be set to 0 if mr2 matches the tc. 0 1 enabled 0 disabled 9 mr3i interrupt on mr3: an interrupt is ge nerated when mr3 matches the value in the tc. 0 1 enabled 0 disabled 10 mr3r reset on mr3: the tc will be reset if mr3 matches it. 0 1 enabled 0 disabled 11 mr3s stop on mr3: the tc and pc will be stopped and tcr[0] will be set to 0 if mr3 matches the tc. 0 1 enabled 0 disabled 31:12 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na table 303. match control register (tmr16b0mcr - address 0x4000 c014 and tmr16b1mcr - address 0x4001 0014) bit description ?continued bit symbol value description reset value
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 350 of 543 nxp semiconductors um10398 chapter 19: lpc1100xl series: 16-bit counter/timer ct16b0/1 19.7.8 capture control register (tmr16b0ccr and tmr16b1ccr) the capture control register is used to control whether the capture register is loaded with the value in the counter/timer when the capture event occurs, and whether an interrupt is gene rated by the captur e event. setting bo th the rising and falling bits at the same time is a valid configuration, resulting in a capture event for both edges. in the description below, n represents the timer number, 0 or 1. table 304: match registers (tmr16b0mr0 to 3, addresses 0x4000 c018 to 24 and tmr16b1mr0 to 3, addresses 0x4001 0018 to 24) bit description bit symbol description reset value 15:0 match timer counter match value. 0 31:16 - reserved. - table 305. capture control register (tmr16b0ccr - address 0x4000 c028 and tmr16b1ccr - address 0x4001 0028) bit description bit symbol value description reset value 0 cap0re capture on ct16bn_cap0 rising edge: a sequence of 0 then 1 on ct16bn_cap0 will cause cr0 to be loaded with the contents of tc. 0 1 enabled 0 disabled 1 cap0fe capture on ct16bn_cap0 falling edge: a sequence of 1 then 0 on ct16bn_cap0 will cause cr0 to be loaded with the contents of tc. 0 1 enabled 0 disabled 2 cap0i interrupt on ct16bn_cap0 event: a cr0 load due to a ct16bn_cap0 event will generate an interrupt. 0 1 enabled 0 disabled 3 cap1re capture on ct16bn_cap1 rising edge: a sequence of 0 then 1 on ct16bn_cap1 will cause cr1 to be loaded with the contents of tc. 0 1 enabled 0 disabled 4 cap1fe capture on ct16bn_cap1 falling edge: a sequence of 1 then 0 on ct16bn_cap1 will cause cr1 to be loaded with the contents of tc. 0 1 enabled 0 disabled 5 cap1i interrupt on ct16bn_cap1 event: a cr1 load due to a ct16bn_cap1 event will generate an interrupt. 0 1 enabled 0 disabled 31:6 - - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 351 of 543 nxp semiconductors um10398 chapter 19: lpc1100xl series: 16-bit counter/timer ct16b0/1 19.7.9 capture register (ct16b0cr0 /1 - address 0x4000 c02c/30 and ct16b1cr0/1 - ad dress 0x4001 002c/30) each capture register is associated with a device pin and may be loaded with the counter/timer value when a specified event occurs on that pin. the settings in the capture control register register determine whether the capture function is enabled, and whether a capture event happens on the rising edge of the associated pin, the falling edge, or on both edges. 19.7.10 external match register (tmr16b0emr and tmr16b1emr) the external match register provides both control and status of the external match channels and external match pins ct16b0_mat[2:0] and ct16b1_mat[1:0]. if the match outputs are configured as pwm output in the pwmcon registers ( section 19.7.12 ), the function of the external matc h registers is determined by the pwm rules ( section 19.7.13 rules for single edge controlled pwm outputs on page 355 ). table 306: capture registers (tmr16b0cr0/1, address 0x4000 c02c/30 and tmr16b1cr0/1, address 0x4001 002c/30) bit description bit symbol description reset value 15:0 cap timer counter capture value. 0 31:16 - reserved. - table 307. external match register (tmr16b0emr - address 0x4000 c03c and tmr16b1emr - address 0x4001 003c) bit description bit symbol value description reset value 0 em0 external match 0. this bit reflects the state of output ct16b0_mat0/ct16b1_mat0, whether or not this output is connected to its pin. when a match occurs between the tc and mr0, this bit can either toggle, go low, go high, or do nothing. bits emr[5:4] control the functionality of this ou tput. this bit is driven to the ct16b0_mat0/ct16b1_mat0 pins if the ma tch function is selected in the iocon registers (0 = low, 1 = high). 0 1 em1 external match 1. this bit reflects the state of output ct16b0_mat1/ct16b1_mat1, whether or not this output is connected to its pin. when a match occurs between the tc and mr1, this bit can either toggle, go low, go high, or do nothing. bits emr[7:6] control the functionality of this ou tput. this bit is driven to the ct16b0_mat1/ct16b1_mat1 pins if the ma tch function is selected in the iocon registers (0 = low, 1 = high). 0 2 em2 external match 2. this bit reflects the st ate of output match chan nel 2, whether or not this output is connected to its pin. when a match occurs between the tc and mr2, this bit can either toggle, go low, go high, or do nothing. bits em r[9:8] control the functionality of this output. no te that on counter/timer 0 this match channel is not pinned out. this bit is driven to the ct16b1_mat2 pi n if the match function is selected in the iocon registers (0 = low, 1 = high). 0 3 em3 external match 3. this bit reflects the st ate of output of match channel 3. when a match occurs between the tc and mr3, this bit can either toggle, go low, go high, or do nothing. bits emr[11:10] control the functionality of this out put. there is no output pin available for this channel on either of the 16-bit timers. 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 352 of 543 nxp semiconductors um10398 chapter 19: lpc1100xl series: 16-bit counter/timer ct16b0/1 5:4 emc0 external match control 0. determines the functional ity of external match 0. 00 0x0 do nothing. 0x1 clear the corresponding external match bi t/output to 0 (ct16bn_matm pin is low if pinned out). 0x2 set the corresponding external match bit/ output to 1 (ct16bn_matm pin is high if pinned out). 0x3 toggle the corresponding external match bit/output. 7:6 emc1 external match control 1. determines the functional ity of external match 1. 00 0x0 do nothing. 0x1 clear the corresponding external match bi t/output to 0 (ct16bn_matm pin is low if pinned out). 0x2 set the corresponding external match bit/ output to 1 (ct16bn_matm pin is high if pinned out). 0x3 toggle the corresponding external match bit/output. 9:8 emc2 external match control 2. determines the functional ity of external match 2. 00 0x0 do nothing. 0x1 clear the corresponding external match bi t/output to 0 (ct16bn_matm pin is low if pinned out). 0x2 set the corresponding external match bit/ output to 1 (ct16bn_matm pin is high if pinned out). 0x3 toggle the corresponding external match bit/output. 11:10 emc3 external match control 3. determines the functional ity of external match 3. 00 0x0 do nothing. 0x1 clear the corresponding external match bi t/output to 0 (ct16bn_matm pin is low if pinned out). 0x2 set the corresponding external match bit/ output to 1 (ct16bn_matm pin is high if pinned out). 0x3 toggle the corresponding external match bit/output. 31:12 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na table 307. external match register (tmr16b0emr - address 0x4000 c03c and tmr16b1emr - address 0x4001 003c) bit description bit symbol value description reset value table 308. external match control emr[11:10], emr[9:8], emr[7:6], or emr[5:4] function 00 do nothing. 01 clear the corresponding external match bit/ou tput to 0 (ct16bn_matm pin is low if pinned out). 10 set the corresponding external match bit/output to 1 (ct16bn_matm pin is high if pinned out). 11 toggle the corresponding external match bit/output.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 353 of 543 nxp semiconductors um10398 chapter 19: lpc1100xl series: 16-bit counter/timer ct16b0/1 19.7.11 count control register (tmr16b0ctcr and tmr16b1ctcr) the count control register (ctcr) is used to select between timer and counter mode, and in counter mode to select the pin and edge(s) for counting. when counter mode is chosen as a mode of operation, the cap input (selected by the ctcr bits 3:2) is sampled on every rising edge of the pclk clock. after comparing two consecutive samples of this cap input, one of the following four events is recognized: rising edge, falling edge, either of edges or no changes in th e level of the selected cap input. only if the identified event occurs, and the event corresponds to the one selected by bits 1:0 in the ctcr register, will the timer counter regist er be incremented. effective processing of the externally supplie d clock to the counter has some limitations. since two successive rising edges of the pclk clock are used to identify only one edge on the cap selected input, the frequency of th e cap input can not exceed one half of the pclk clock. consequently, duration of the high/low levels on the same cap input in this case can not be shorter than 1/(2 ? pclk). bits 7:4 of this register are used to enable and configure the capture-clears-timer feature. this feature allows for a designated edge on a particular cap input to reset the timer to all zeros. using this mechanism to clear the timer on the leading edge of an input pulse and performing a capture on the tr ailing edge permits direct pu lse-width measurement using a single capture input without the need to perform a subtraction operation in software. table 309. count control register (tmr16b0ctcr - address 0x4000 c070 and tmr16b1ctcr - address 0x4001 0070) bit description bit symbol value description reset value 1:0 ctm counter/timer mode. this field selects which rising pclk edges can increment timers prescale counter (pc), or clear pc and increment ti mer counter (tc). 00 0x0 timer mode: every rising pclk edge 0x1 counter mode: tc is incremented on rising edges on the cap input selected by bits 3:2. 0x2 counter mode: tc is incremented on falling edges on the cap input selected by bits 3:2. 0x3 counter mode: tc is incremented on both edges on the cap input selected by bits 3:2. 3:2 cis count input select. in counter mode (when bits 1:0 in this register are not 00), these bits select which cap pin is sampled for clocking. note: if counter mode is selected in the ctcr register, bits 2:0 in the capture control register (ccr) must be programmed as 000. 00 0x0 ct16bn_cap0 0x1 ct16bn_cap1 0x2 reserved. 0x0 reserved. 4 encc setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs. 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 354 of 543 nxp semiconductors um10398 chapter 19: lpc1100xl series: 16-bit counter/timer ct16b0/1 19.7.12 pwm control register (tmr16b0pwmc and tmr16b1pwmc) the pwm control register is used to config ure the match outputs as pwm outputs. each match output can be independently set to pe rform either as pwm output or as match output whose function is controlled by the external match register (emr). for timer 0, three single-edge controlled pwm outputs can be selected on the ct16b0_mat[2:0] outputs. for timer 1, two single-edged pwm outputs can be selected on the ct16b1_mat[1:0] outputs. one additi onal match register determines the pwm cycle length. when a match occurs in any of th e other match registers, the pwm output is set to high. the timer is reset by the match register that is conf igured to set the pwm cycle length. when the timer is reset to zero, all currently high match outputs configured as pwm outputs are cleared. 7:5 selcc when bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. these bits have no effect when bit 4 is zero. 0 0x0 rising edge of cap0 clears the timer (if bit 4 is set). 0x1 falling edge of cap0 clears the timer (if bit 4 is set). 0x2 rising edge of cap1 clears the timer (if bit 4 is set). 0x3 falling edge of cap1 clears the timer (if bit 4 is set). 0x4 reserved. 0x5 reserved. 0x6 reserved. 0x7 reserved. 31:8 - - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - table 309. count control register (tmr16b0ctcr - address 0x4000 c070 and tmr16b1ctcr - address 0x4001 0070) bit description bit symbol value description reset value table 310. pwm control register (tmr16b0pwmc - address 0x4000 c074 and tmr16b1pwmc- address 0x4001 0074) bit description bit symbol value description reset value 0 pwmen0 pwm channel0 enable 0 0 ct16bn_mat0 is controlled by em0. 1 pwm mode is enabled for ct16bn_mat0. 1 pwmen1 pwm channel1 enable 0 0 ct16bn_mat1 is controlled by em1. 1 pwm mode is enabled for ct16bn_mat1. 2 pwmen2 pwm channel2 enable 0 0 match channel 2 or pin ct16b0_mat2 is controlled by em2. match channel 2 is not pinned out on timer 1. 1 pwm mode is enabled for match channel 2 or pin ct16b0_mat2.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 355 of 543 nxp semiconductors um10398 chapter 19: lpc1100xl series: 16-bit counter/timer ct16b0/1 19.7.13 rules for single e dge controlled pwm outputs 1. all single edge controlled pwm outputs go low at the beginning of each pwm cycle (timer is set to zero) unless their match value is equal to zero. 2. each pwm output will go high when its matc h value is reached. if no match occurs (i.e. the match value is greater than the pwm cycle length), the pwm output remains continuously low. 3. if a match value larger than the pwm cycle length is written to the match register, and the pwm signal is high already, then the pwm signal will be cleared on the next start of the next pwm cycle. 4. if a match register contains the same value as the timer reset value (the pwm cycle length), then the pwm output will be reset to low on the next clock tick. therefore, the pwm output will always consist of a one clock tick wide positive pulse with a period determined by the pwm cycle length (i.e. the timer reload value). 5. if a match register is set to zero, then the pwm output will go to high the first time the timer goes back to zero and will stay high continuously. note: when the match outputs are selected to serve as pwm outputs, the timer reset (mrnr) and timer stop (mrns) bits in the match control register mcr must be set to 0 except for the match register setting the pwm cycle length. for th is register, set the mrnr bit to 1 to enable the timer reset w hen the timer value matches the value of the corresponding match register. 3 pwmen3 pwm channel3 enable note: it is recommended to use match channel 3 to set the pwm cycle because it is not pinned out. 0 0 match channel 3 match channel 3 is controlled by em3. 1 pwm mode is enabled for match channel 3match channel 3. 31:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na table 310. pwm control register (tmr16b0pwmc - address 0x4000 c074 and tmr16b1pwmc- address 0x4001 0074) bit description bit symbol value description reset value fig 73. sample pwm waveforms with a pwm cycl e length of 100 (selected by mr2) and mat2:0 enabled as pwm outputs by the pwcm register. 100 (counter is reset) 04165 pwm0/mat0 pwm1/mat1 pwm2/mat2 mr2 = 100 mr1 = 41 mr0 = 65
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 356 of 543 nxp semiconductors um10398 chapter 19: lpc1100xl series: 16-bit counter/timer ct16b0/1 19.8 example timer operation figure 74 shows a timer configured to reset the count and generate an interrupt on match. the prescaler is set to 2 and the match register set to 6. at the end of the timer cycle where the match occurs, the timer count is re set. this gives a full length cycle to the match value. the interrupt indicating that a ma tch occurred is generated in the next clock after the timer reached the match value. figure 75 shows a timer configured to stop and generate an interrupt on match. the prescaler is again set to 2 and the match register set to 6. in the next clock after the timer reaches the match value, the timer enable bit in tcr is cleare d, and the interrupt indicating that a match occurred is generated. 19.9 architecture the block diagram for counter/timer0 and counter/timer1 is shown in figure 76 . fig 74. a timer cycle in which pr =2, mrx=6, and both interrupt and reset on match are enabled pclk prescale counter interrupt timer counter timer counter reset 2 2 2 2000 0 1111 45 6 0 1 fig 75. a timer cycle in which pr=2, mrx=6, and both interrupt and stop on match are enabled pclk prescale counter interrupt timer counter tcr[0] (counter enable) 2 20 0 1 45 6 1 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 357 of 543 nxp semiconductors um10398 chapter 19: lpc1100xl series: 16-bit counter/timer ct16b0/1 fig 76. 16-bit counter/ timer block diagram reset maxval timer control register prescale register prescale counter pclk enable capture register 1 match register 3 match register 2 match register 1 match register 0 capture control register control timer counter csn tci ce = = = = interrupt register external match register match control register matn[2:0] interrupt cap[1:0] stop on match reset on match load[3:0] capture register 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 358 of 543 20.1 how to read this chapter the 32-bit timer blocks are identical for all lpc111x, lpc11d14, and lpc11cxx parts. 20.2 basic configuration the ct32b0/1 are configured using the following registers: 1. pins: the ct32b0/1 pins must be co nfigured in the ioconfig register block ( section 7.4 ). 2. power and peripheral clock: in the sysahbc lkctrl register, se t bit 9 and bit 10 ( ta b l e 2 1 ). the peripheral clock (pclk) is provided by the system clock (see ta b l e 2 0 ). 20.3 features ? two 32-bit counter/timers with a programmable 32-bit prescaler. ? counter or timer operation. ? one 32-bit capture channel that can take a snapshot of the timer value when an input signal transitions. a capture event may also optionally generate an interrupt. ? four 32-bit match registers that allow: ? continuous operation with optional interrupt generation on match. ? stop timer on match with optional interrupt generation. ? reset timer on match with optional interrupt generation. ? four external outputs corres ponding to match registers with the following capabilities: ? set low on match. ? set high on match. ? toggle on match. ? do nothing on match. ? for each timer, up to four match registers can be configured as pwm allowing to use up to three match outputs as single edge controlled pwm outputs. 20.4 applications ? interval timer for counting internal events ? pulse width demodulator via capture input ? free running timer ? pulse width modulator via match outputs um10398 chapter 20: lpc1100/lpc1100c/ lpc1100l series: 32-bit counter/timer ct32b0/1 rev. 12.1 ? 7 august 2013 user manual
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 359 of 543 nxp semiconductors um10398 chapter 20: lpc1100/lpc1100c/lpc1100l series: 32-bit counter/timer 20.5 description each counter/timer is designed to count cycl es of the peripheral clock (pclk) or an externally supplied clock and can optionally gene rate interrupts or perform other actions at specified timer values based on four match registers. the peripheral clock is provided by the system clock (see figure 8 ). each counter/timer also includes one capture input to trap the timer value when an input signal tr ansitions, optionally generating an interrupt. in pwm mode, three match registers can be used to provide a single-edge controlled pwm output on the match output pins. one ma tch register is used to control the pwm cycle length. remark: 32-bit counter/timer0 (ct32b0) and 32-bit counter/timer1 (ct32b1) are functionally identical except for the peripheral base address. 20.6 pin description ta b l e 3 11 gives a brief summary of each of the counter/timer related pins. 20.7 register description 32-bit counter/timer0 contains the registers shown in ta b l e 3 1 2 and 32-bit counter/timer1 contains the registers shown in table 313 . more detailed descriptions follow. table 311. counter/timer pin description pin type description ct32b0_cap0 ct32b1_cap0 input capture signals: a transition on a capture pin can be confi gured to load one of the capture registers with the value in the timer counter and optionally generate an interrupt. the counter/timer block can select a capture signal as a clock source instead of the pclk derived clock. for more details see section 20.7.11 count control register (tmr32b0ctcr and tmr32b1tcr) on page 367 . ct32b0_mat[3:0] ct32b1_mat[3:0] output external match output of ct32b0/1: when a match register tmr32b0/1mr3:0 equals the timer counter (tc), this output can either toggle, go low, go high, or do nothing. the external match register (emr) and the pwm control register (pwm con) control the fu nctionality of this output. table 312. register overview: 32-bit counter/timer 0 ct32b0 (base address 0x4001 4000) name access address offset description reset value [1] tmr32b0ir r/w 0x000 interrupt register (ir). the ir can be written to clear interrupts. the ir can be read to identify which of fi ve possible interrupt sources are pending. 0 tmr32b0tcr r/w 0x004 timer control register (t cr). the tcr is used to control the timer counter functions. the timer counter can be disabled or reset through the tcr. 0 tmr32b0tc r/w 0x008 timer counter (tc). the 32-bit tc is incremented every pr+1 cycles of pclk. the tc is controlled through the tcr. 0 tmr32b0pr r/w 0x00c prescale register (pr). when the prescale counter (below) is equal to this value, the next clock increments the tc and clears the pc. 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 360 of 543 nxp semiconductors um10398 chapter 20: lpc1100/lpc1100c/lpc1100l series: 32-bit counter/timer [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. tmr32b0pc r/w 0x010 prescale counter (pc). the 32 -bit pc is a counter which is incremented to the value stored in pr. when the value in pr is reached, the tc is incremented and the pc is cleared. the pc is observable and controllable through the bus interface. 0 tmr32b0mcr r/w 0x014 match control register (mcr). the mcr is used to control if an interrupt is generated and if the tc is reset when a match occurs. 0 tmr32b0mr0 r/w 0x018 match register 0 (mr0). mr0 can be enabled through the mcr to reset the tc, stop both the tc and pc, and/or generate an interrupt every time mr0 matches the tc. 0 tmr32b0mr1 r/w 0x01c match register 1 (mr1). see mr0 description. 0 tmr32b0mr2 r/w 0x020 match register 2 (mr2). see mr0 description. 0 tmr32b0mr3 r/w 0x024 match register 3 (mr3). see mr0 description. 0 tmr32b0ccr r/w 0x028 capture control register (ccr). the ccr controls which edges of the capture inputs are used to load the capture registers and whether or not an interrupt is generated when a capture takes place. 0 tmr32b0cr0 ro 0x02c capture register 0 (cr0). cr0 is loaded with the value of tc when there is an event on the ct32b0_cap0 input. 0 tmr32b0emr r/w 0x03c external match register (emr). the emr controls the match function and the external match pins ct32b0_mat[3:0]. 0 - - 0x040 - 0x06c reserved - tmr32b0ctcr r/w 0x070 count control register (ctcr). the ctcr selects between timer and counter mode, and in counter mode selects the signal and edge(s) for counting. 0 tmr32b0pwmc r/w 0x074 pwm control register (pwmcon). the pwmcon enables pwm mode for the external match pins ct32b0_mat[3:0]. 0 table 312. register overview: 32-bit counter/timer 0 ct32b0 (base address 0x4001 4000) ?continued name access address offset description reset value [1] table 313. register overview: 32-bit counter/timer 1 ct32b1 (base address 0x4001 8000) name access address offset description reset value [1] tmr32b1ir r/w 0x000 interrupt register (ir). the ir can be written to clear interrupts. the ir can be read to identify which of five possible interrupt sources are pending. 0 tmr32b1tcr r/w 0x004 timer control register (tcr). the tcr is used to control the timer counter functions. the timer counter can be disabled or reset through the tcr. 0 tmr32b1tc r/w 0x008 timer counter (tc). the 32-bit tc is incremented every pr+1 cycles of pclk. the tc is controlled through the tcr. 0 tmr32b1pr r/w 0x00c prescale register (pr). when the prescale counter (below) is equal to this value, the next clock increments the tc and clears the pc. 0 tmr32b1pc r/w 0x010 prescale counter (pc). the 32-bit pc is a counter which is incremented to the value stored in pr. when the value in pr is reached, the tc is incremented and the pc is cleared. the pc is observable and controllable through the bus interface. 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 361 of 543 nxp semiconductors um10398 chapter 20: lpc1100/lpc1100c/lpc1100l series: 32-bit counter/timer [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. 20.7.1 interrupt register (tmr32b0ir and tmr32b1ir) the interrupt register consists of four bits for the match interrupts and one bit for the capture interrupts. if an interrupt is g enerated then the corresponding bit in the ir will be high. otherwise, the bit will be low. writing a logic one to the corresponding ir bit will reset the interrupt. writing a zero has no effect. 20.7.2 timer control register (tmr32b0tcr and tmr32b1tcr) the timer control register (tcr) is used to control the operation of the counter/timer. tmr32b1mcr r/w 0x014 match control register (mcr). the mcr is used to control if an interrupt is generated and if the tc is reset when a match occurs. 0 tmr32b1mr0 r/w 0x018 match register 0 (mr0). mr0 can be enabled through the mcr to reset the tc, stop both the tc and pc, and/or generate an interrupt every time mr0 matches the tc. 0 tmr32b1mr1 r/w 0x01c match register 1 (mr1). see mr0 description. 0 tmr32b1mr2 r/w 0x020 match register 2 (mr2). see mr0 description. 0 tmr32b1mr3 r/w 0x024 match register 3 (mr3). see mr0 description. 0 tmr32b1ccr r/w 0x028 capture control register (ccr). the ccr controls which edges of the capture inputs are used to load th e capture registers and whether or not an interrupt is generated when a capture takes place. 0 tmr32b1cr0 ro 0x02c capture register 0 (cr0). cr0 is loaded with the value of tc when there is an event on the ct32b1_cap0 input. 0 tmr32b1emr r/w 0x03c external match register (e mr). the emr controls the match function and the external match pins ct32b1_mat[3:0]. 0 - - 0x040 - 0x06c reserved - tmr32b1ctcr r/w 0x070 count control register (ctcr). the ctcr selects between timer and counter mode, and in counter mode selects the signal and edge(s) for counting. 0 tmr32b1pwmc r/w 0x074 pwm control register (pwmcon). the pwmcon enables pwm mode for the external match pins ct32b1_mat[3:0]. 0 table 313. register overview: 32-bit counter/timer 1 ct32b1 (base address 0x4001 8000) ?continued name access address offset description reset value [1] table 314: interrupt register (tmr32b0ir - address 0x4001 4000 and tmr32b1ir - address 0x4001 8000) bit description bit symbol description reset value 0 mr0 interrupt interrupt flag for match channel 0. 0 1 mr1 interrupt interrupt flag for match channel 1. 0 2 mr2 interrupt interrupt flag for match channel 2. 0 3 mr3 interrupt interrupt flag for match channel 3. 0 4 cr0 interrupt interrupt flag for capture channel 0 event. 0 31:5 - reserved -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 362 of 543 nxp semiconductors um10398 chapter 20: lpc1100/lpc1100c/lpc1100l series: 32-bit counter/timer 20.7.3 timer counter (tmr32b0 tc - address 0x4001 4008 and tmr32b1tc - address 0x4001 8008) the 32-bit timer counter is incremented when the prescale counter reaches its terminal count. unless it is reset be fore reaching its upper limit, th e tc will count up through the value 0xffff ffff and then wrap back to the value 0x0000 0000. this event does not cause an interrupt, but a match register can be used to detect an overflow if needed. 20.7.4 prescale register (tmr 32b0pr - address 0x4001 400c and tmr32b1pr - address 0x4001 800c) the 32-bit prescale register specifies the maximum value for the prescale counter. 20.7.5 prescale counter register (tmr32b0pc - address 0x4001 4010 and tmr32b1pc - address 0x4001 8010) the 32-bit prescale counter controls division of pclk by some constant value before it is applied to the timer counter. this allows control of the relationship between the resolution of the timer and the maximum time before t he timer overflows. the prescale counter is incremented on every pclk. when it reaches the value stored in the prescale register, the timer counter is incremented, and the prescale counter is reset on the next pclk. this causes the tc to increment on every pclk when pr = 0, every 2 pclks when pr = 1, etc. table 315: timer control register (tmr32b0tcr - address 0x4001 4004 and tmr32b1tcr - address 0x4001 8004) bit description bit symbol description reset value 0 cen when one, the timer counter and prescale counter are enabled for counting. when zero, the counters are disabled. 0 1 crst when one, the timer counter and the prescale counter are synchronously reset on the next positive edge of pclk. the counters remain reset until tcr[1] is returned to zero. 0 31:2 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na table 316: timer counter registers (tmr32b0tc, address 0x4001 4008 and tmr32b1tc 0x4001 8008) bit description bit symbol description reset value 31:0 tc timer counter value. 0 table 317: prescale registers (tmr32b0pr, address 0x4001 400c and tmr32b1pr 0x4001 800c) bit description bit symbol description reset value 31:0 pr prescale value. 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 363 of 543 nxp semiconductors um10398 chapter 20: lpc1100/lpc1100c/lpc1100l series: 32-bit counter/timer 20.7.6 match control register (tmr32b0mcr and tmr32b1mcr) the match control register is used to contro l what operations are performed when one of the match registers matches the timer counter. the function of each of the bits is shown in table 319 . table 318: prescale counter registers (tmr32b0pc, address 0x4001 4010 and tmr32b1pc 0x4001 8010) bit description bit symbol description reset value 31:0 pc prescale counter value. 0 table 319: match control register (tmr32b0mcr - address 0x4001 4014 and tmr32b1mcr - address 0x4001 8014) bit description bit symbol value description reset value 0 mr0i interrupt on mr0: an interrupt is ge nerated when mr0 matches the value in the tc. 0 1 enabled 0 disabled 1 mr0r reset on mr0: the tc will be reset if mr0 matches it. 0 1 enabled 0 disabled 2 mr0s stop on mr0: the tc and pc will be stopped and tcr[0] will be set to 0 if mr0 matches the tc. 0 1 enabled 0 disabled 3 mr1i interrupt on mr1: an interrupt is ge nerated when mr1 matches the value in the tc. 0 1 enabled 0 disabled 4 mr1r reset on mr1: the tc will be reset if mr1 matches it. 0 1 enabled 0 disabled 5 mr1s stop on mr1: the tc and pc will be stopped and tcr[0] will be set to 0 if mr1 matches the tc. 0 1 enabled 0 disabled 6 mr2i interrupt on mr2: an interrupt is ge nerated when mr2 matches the value in the tc. 0 1 enabled 0 disabled 7 mr2r reset on mr2: the tc will be reset if mr2 matches it. 0 1 enabled 0 disabled 8 mr2s stop on mr2: the tc and pc will be stopped and tcr[0] will be set to 0 if mr2 matches the tc. 0 1 enabled 0 disabled
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 364 of 543 nxp semiconductors um10398 chapter 20: lpc1100/lpc1100c/lpc1100l series: 32-bit counter/timer 20.7.7 match registers (tmr 32b0mr0/1/2/3 - addresses 0x4001 4018/1c/20/24 and tmr32b1mr0 /1/2/3 addresses 0x4001 8018/1c/20/24) the match register values are continuously compared to the timer counter value. when the two values are equal, acti ons can be triggere d automatically. the action possibilities are to generate an interrupt, reset the timer counter, or stop the timer. actions are controlled by the settings in the mcr register. 20.7.8 capture control register (tmr32b0ccr and tmr32b1ccr) the capture control register is used to control whether the capture register is loaded with the value in the timer counter when the capture event occurs, and whether an interrupt is gene rated by the captur e event. setting bo th the rising and falling bits at the same time is a valid configuration, resulting in a capture event for both edges. in the description below, n represents the timer number, 0 or 1. 9 mr3i interrupt on mr3: an interrupt is ge nerated when mr3 matches the value in the tc. 0 1 enabled 0 disabled 10 mr3r reset on mr3: the tc will be reset if mr3 matches it. 0 1 enabled 0 disabled 11 mr3s stop on mr3: the tc and pc will be stopped and tcr[0] will be set to 0 if mr3 matches the tc. 0 1 enabled 0 disabled 31:12 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na table 319: match control register (tmr32b0mcr - address 0x4001 4014 and tmr32b1mcr - address 0x4001 8014) bit description bit symbol value description reset value table 320: match registers (tmr32b0mr0 to 3, addresses 0x4001 4018 to 24 and tmr32b1mr0 to 3, addresses 0x4001 8018 to 24) bit description bit symbol description reset value 31:0 match timer counter match value. 0 table 321: capture control register (tmr32b0cc r - address 0x4001 4028 and tmr32b1ccr - address 0x4001 8028) bit description bit symbol value description reset value 0 cap0re capture on ct32bn_cap0 rising edge: a sequence of 0 then 1 on ct32bn_cap0 will cause cr0 to be loaded with the contents of tc. 0 1 enabled 0 disabled
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 365 of 543 nxp semiconductors um10398 chapter 20: lpc1100/lpc1100c/lpc1100l series: 32-bit counter/timer 20.7.9 capture register (tmr32b 0cr0 - address 0x4001 402c and tmr32b1cr0 - address 0x4001 802c) each capture register is associated with a device pin and may be loaded with the timer counter value when a specified event occurs on that pin. the settings in the capture control register register determine whether the capture function is enabled, and whether a capture event happens on the rising edge of the associated pin, the falling edge, or on both edges. 20.7.10 external match register (tmr32b0emr and tmr32b1emr) the external match register provides both co ntrol and status of the external match pins cap32bn_mat[3:0]. if the match outputs are configured as pwm ou tput, the function of the external match registers is determined by the pwm rules ( section 20.7.13 rules for single edge controlled pwm outputs on page 369 ). 1 cap0fe capture on ct32bn_cap0 falling edge: a sequence of 1 then 0 on ct32bn_cap0 will cause cr0 to be loaded with the contents of tc. 0 1 enabled 0 disabled 2 cap0i interrupt on ct32bn_cap0 event: a cr0 load due to a ct32bn_cap0 event will generate an interrupt. 0 1 enabled 0 disabled 31:3 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na table 321: capture control register (tmr32b0cc r - address 0x4001 4028 and tmr32b1ccr - address 0x4001 8028) bit description bit symbol value description reset value table 322: capture registers (tmr32b0cr0, addresses 0x4001 402c and tmr32b1cr0, addresses 0x4001 802c) bit description bit symbol description reset value 31:0 cap timer counter capture value. 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 366 of 543 nxp semiconductors um10398 chapter 20: lpc1100/lpc1100c/lpc1100l series: 32-bit counter/timer table 323: external match register (tmr32b0emr - address 0x4001 403c and tmr32b1emr - address0x4001 803c) bit description bit symbol value description reset value 0 em0 external match 0. this bit reflects the state of output ct 32bn_mat0, whether or not this output is connected to its pin. when a match occurs between the tc and mr0, this bit can either toggle, go low, go high, or do nothing. bits emr[5:4] control the functionality of this output. this bit is driven to t he ct32b0_mat0/ct16b1_mat 0 pins if the match function is selected in the iocon registers (0 = low, 1 = high). 0 1 em1 external match 1. this bit reflects the state of output ct 32bn_mat1, whether or not this output is connected to its pin. when a match occurs between the tc and mr1, this bit can either toggle, go low, go high, or do nothing. bits emr[7:6] control the functionality of this output. this bit is driven to t he ct32b0_mat1/ct16b1_mat 1 pins if the match function is selected in the iocon registers (0 = low, 1 = high). 0 2 em2 external match 2. this bit reflects the state of output ct 32bn_mat2, whether or not this output is connected to its pin. when a match occurs between the tc and mr2, this bit can either toggle, go low, go high, or do nothing. bits emr[9:8] control the functionality of this output. this bit is driven to t he ct32b0_mat2/ct16b1_mat 2 pins if the match function is selected in the iocon registers (0 = low, 1 = high). 0 3 em3 external match 3. this bit reflects the state of output ct 32bn_mat3, whether or not this output is connected to its pin. when a match occurs between the tc and mr3, this bit can either toggle, go low, go high, or do nothing. bits emr[11:10] control the functionality of this ou tput. this bit is driven to the ct32b0_mat3/ct16b1_mat3 pins if the match function is selected in the iocon registers (0 = low, 1 = high). 0 5:4 emc0 external match control 0. determines the functional ity of external match 0. 00 0x0 do nothing. 0x1 clear the corresponding external match bi t/output to 0 (ct32bn_matm pin is low if pinned out). 0x2 set the corresponding external match bit/ output to 1 (ct32bn_matm pin is high if pinned out). 0x3 toggle the corresponding external match bit/output. 7:6 emc1 external match control 1. determines the functional ity of external match 1. 00 0x0 do nothing. 0x1 clear the corresponding external match bi t/output to 0 (ct32bn_matm pin is low if pinned out). 0x2 set the corresponding external match bit/ output to 1 (ct32bn_matm pin is high if pinned out). 0x3 toggle the corresponding external match bit/output. 9:8 emc2 external match control 2. determines the functional ity of external match 2. 00 0x0 do nothing. 0x1 clear the corresponding external match bi t/output to 0 (ct32bn_matm pin is low if pinned out). 0x2 set the corresponding external match bit/ output to 1 (ct32bn_matm pin is high if pinned out). 0x3 toggle the corresponding external match bit/output.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 367 of 543 nxp semiconductors um10398 chapter 20: lpc1100/lpc1100c/lpc1100l series: 32-bit counter/timer 20.7.11 count control register (tmr32b0ctcr and tmr32b1tcr) the count control register (ctcr) is used to select between timer and counter mode, and in counter mode to select the pin and edge(s) for counting. when counter mode is chosen as a mode of operation, the cap input (selected by the ctcr bits 3:2) is sampled on every rising edge of the pclk clock. after comparing two consecutive samples of this cap input, one of the following four events is recognized: rising edge, falling edge, either of edges or no changes in th e level of the selected cap input. only if the identified event occurs, and the event corresponds to the one selected by bits 1:0 in the ctcr register, will the timer counter regist er be incremented. effective processing of the externally supplie d clock to the counter has some limitations. since two successive rising edges of the pclk clock are used to identify only one edge on the cap selected input, the frequency of th e cap input can not exceed one half of the pclk clock. consequently, duration of the high/low levels on the same cap input in this case can not be shorter than 1/(2 ? pclk). 11:10 emc3 external match control 3. determines the functional ity of external match 3. 00 0x0 do nothing. 0x1 clear the corresponding external match bi t/output to 0 (ct32bn_matm pin is low if pinned out). 0x2 set the corresponding external match bit/ output to 1 (ct32bn_matm pin is high if pinned out). 0x3 toggle the corresponding external match bit/output. 31:12 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na table 323: external match register (tmr32b0emr - address 0x4001 403c and tmr32b1emr - address0x4001 803c) bit description bit symbol value description reset value table 324. external match control emr[11:10], emr[9:8], emr[7:6], or emr[5:4] function 00 do nothing. 01 clear the corresponding external match bit/ou tput to 0 (ct32bn_matm pin is low if pinned out). 10 set the corresponding external match bit/output to 1 (ct32bn_matm pin is high if pinned out). 11 toggle the corresponding external match bit/output.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 368 of 543 nxp semiconductors um10398 chapter 20: lpc1100/lpc1100c/lpc1100l series: 32-bit counter/timer 20.7.12 pwm control register (tmr32b0pwmc and tmr32b1pwmc) the pwm control register is used to config ure the match outputs as pwm outputs. each match output can be independently set to pe rform either as pwm output or as match output whose function is controlled by the external match register (emr). for each timer, a maximum of three-single edge controlled pwm outputs can be selected on the matn[2:0] outputs. one additional match register determines the pwm cycle length. when a match occurs in any of the othe r match registers, the pwm output is set to high. the timer is reset by t he match register that is configured to set the pwm cycle length. when the timer is reset to zero, a ll currently high match outputs configured as pwm outputs are cleared. table 325: count control register (tmr32b0ctcr - address 0x4001 4070 and tmr32b1tcr - address 0x4001 8070) bit description bit symbol value description reset value 1:0 ctm counter/timer mode. this field selects which rising pclk edges can increment timers prescale counter (pc), or clear pc and increment timer counter (tc). timer mode: every rising pclk edge 00 0x0 timer mode: every rising pclk edge 0x1 counter mode: tc is incremented on rising edges on the cap input selected by bits 3:2. 0x2 counter mode: tc is incremented on falling edges on the cap input selected by bits 3:2. 0x3 counter mode: tc is incremented on both edges on the cap input selected by bits 3:2. 3:2 cis count input select. when bits 1:0 in this register are not 00, these bits select which cap pin is sampled for clocking: 00 0x0 ct32bn_cap0 0x1 reserved 0x2 reserved 0x3 reserved note: if counter mode is selected in the tnctcr, the 3 bits for that input in the capture control register (tnccr) must be programmed as 000. 31:4 - - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na table 326: pwm control register (tmr32b0pwmc - 0x4001 4074 and tmr32b1pwmc - 0x4001 8074) bit description bit symbol value description reset value 0 pwmen0 pwm channel 0 enable 0 0 ct32bn_mat0 is controlled by em0. 1 pwm mode is enabled for ct32bn_mat0.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 369 of 543 nxp semiconductors um10398 chapter 20: lpc1100/lpc1100c/lpc1100l series: 32-bit counter/timer 20.7.13 rules for single e dge controlled pwm outputs 1. all single edge controlled pwm outputs go low at the beginning of each pwm cycle (timer is set to zero) unless their match value is equal to zero. 2. each pwm output will go high when its matc h value is reached. if no match occurs (i.e. the match value is greater than the pwm cycle length), the pwm output remains continuously low. 3. if a match value larger than the pwm cycle length is written to the match register, and the pwm signal is high already, then the pwm signal will be cleared with the start of the next pwm cycle. 4. if a match register contains the same value as the timer reset value (the pwm cycle length), then the pwm output will be reset to low on the next clock tick after the timer reaches the match valu e. therefore, the pwm out put will always consist of a one clock tick wide positive pulse with a period determined by the pwm cycle length (i.e. the timer reload value). 5. if a match register is set to zero, then the pwm output will go to high the first time the timer goes back to zero and will stay high continuously. note: when the match outputs are selected to function as pwm outputs, the timer reset (mrnr) and timer stop (mrns) bits in the match control register mcr must be set to 0 except for the match register setting the pwm cycle length. for th is register, set the mrnr bit to 1 to enable the timer reset w hen the timer value matches the value of the corresponding match register. 1 pwmen1 pwm channel 1 enable 0 0 ct32bn_mat1 is controlled by em1. 1 pwm mode is enabled for ct32bn_mat1. 2 pwmen2 pwm channel 2 enable 0 0 ct32bn_mat2 is controlled by em2. 1 pwm mode is enabled for ct32bn_mat2. 3 pwmen3 pwm channel 3 enable note: it is recommended to use match channel 3 to set the pwm cycle. 0 0 ct32bn_mat3 is controlled by em3. 1 pwm mode is enabled for ct32bn_mat3. 31:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na table 326: pwm control register (tmr32b0pwmc - 0x4001 4074 and tmr32b1pwmc - 0x4001 8074) bit description bit symbol value description reset value
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 370 of 543 nxp semiconductors um10398 chapter 20: lpc1100/lpc1100c/lpc1100l series: 32-bit counter/timer 20.8 example timer operation figure 78 shows a timer configured to reset the count and generate an interrupt on match. the prescaler is set to 2 and the match register set to 6. at the end of the timer cycle where the match occurs, the timer count is re set. this gives a full length cycle to the match value. the interrupt indicating that a ma tch occurred is generated in the next clock after the timer reached the match value. figure 79 shows a timer configured to stop and generate an interrupt on match. the prescaler is again set to 2 and the match register set to 6. in the next clock after the timer reaches the match value, the timer enable bit in tcr is cleare d, and the interrupt indicating that a match occurred is generated. fig 77. sample pwm waveforms with a pwm cycl e length of 100 (selected by mr2) and mat2:0 enabled as pwm outputs by the pwcm register. 100 (counter is reset) 04165 pwm0/mat0 pwm1/mat1 pwm2/mat2 mr2 = 100 mr1 = 41 mr0 = 65 fig 78. a timer cycle in which pr =2, mrx=6, and both interrupt and reset on match are enabled pclk prescale counter interrupt timer counter timer counter reset 2 2 2 2000 0 1111 45 6 0 1 fig 79. a timer cycle in which pr=2, mrx=6, and both interrupt and stop on match are enabled pclk prescale counter interrupt timer counter tcr[0] (counter enable) 2 20 0 1 45 6 1 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 371 of 543 nxp semiconductors um10398 chapter 20: lpc1100/lpc1100c/lpc1100l series: 32-bit counter/timer 20.9 architecture the block diagram for 32-bit counter/timer0 and 32-bit counter/timer1 is shown in figure 80 . fig 80. 32-bit counter/ timer block diagram reset maxval timer control register prescale register prescale counter pclk enable capture register 0 match register 3 match register 2 match register 1 match register 0 capture control register control timer counter csn tci ce = = = = interrupt register external match register match control register mat[3:0] interrupt cap0 stop on match reset on match load[3:0]
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 372 of 543 21.1 how to read this chapter the 32-bit timer blocks are identical for all lpc1100xl parts. compared to the timer block for the lpc1100/lpc1100l/lpc1100c series, the following features have been added: ? one additional capture input for each timer. ? capture-clear function for easy pulse-width measurement (see section 21.7.11 ). 21.2 basic configuration the ct32b0/1 are configured using the following registers: 1. pins: the ct32b0/1 pins must be co nfigured in the ioconfig register block ( section 7.4 ). 2. power and peripheral clock: in the sysahbc lkctrl register, se t bit 9 and bit 10 ( ta b l e 2 1 ). the peripheral clock (pclk) is provided by the system clock (see ta b l e 2 0 ). 21.3 features ? two 32-bit counter/timers with a programmable 32-bit prescaler. ? counter or timer operation. ? the timer and prescaler may be configured to be cleared on a designated capture event. this feature permits easy pulse-width measurement by clearing the timer on the leading edge of an input pulse and capt uring the timer value on the trailing edge. ? two 32-bit capture channels that can take a snapshot of the timer value when an input signal transitions. a capture event may also optionally generate an interrupt. ? four 32-bit match registers that allow: ? continuous operation with optional interrupt generation on match. ? stop timer on match with optional interrupt generation. ? reset timer on match with optional interrupt generation. ? up to four external outputs corresponding to match registers with the following capabilities: ? set low on match. ? set high on match. ? toggle on match. ? do nothing on match. ? for each timer, up to four match registers can be configured as pwm allowing to use up to three match outputs as single edge controlled pwm outputs. um10398 chapter 21: lpc1100xl series: 32-bit counter/timer ct32b0/1 rev. 12.1 ? 7 august 2013 user manual
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 373 of 543 nxp semiconductors um10398 chapter 21: lpc1100xl series: 32-bit counter/timer ct32b0/1 21.4 applications ? interval timer for counting internal events ? pulse width demodulator via capture input ? free running timer ? pulse width modulator via match outputs 21.5 description each counter/timer is designed to count cycl es of the peripheral clock (pclk) or an externally supplied clock and can optionally gene rate interrupts or perform other actions at specified timer values based on four match registers. the peripheral clock is provided by the system clock (see figure 8 ). each counter/timer also includes one capture input to trap the timer value when an input signal tr ansitions, optionally generating an interrupt. in pwm mode, three match registers can be used to provide a single-edge controlled pwm output on the match output pins. one ma tch register is used to control the pwm cycle length. remark: 32-bit counter/timer0 (ct32b0) and 32-bit counter/timer1 (ct32b1) are functionally identical except for the peripheral base address. 21.6 pin description table 327 gives a brief summary of each of the counter/timer related pins. 21.7 register description 32-bit counter/timer0 contains the registers shown in ta b l e 3 2 8 and 32-bit counter/timer1 contains the registers shown in table 329 . more detailed descriptions follow. table 327. counter/timer pin description pin type description ct32b0_cap[1:0] ct32b1_cap[1:0] input capture signals: a transition on a capture pin can be confi gured to load one of the capture registers with the value in the timer counter and optionally generate an interrupt. the counter/timer block can select a capture signal as a clock source instead of the pclk derived clock. for more details see section 21.7.11 count control register (tmr32b0ctcr and tmr32b1tcr) on page 382 . ct32b0_mat[3:0] ct32b1_mat[3:0] output external match output of ct32b0/1: when a match register tmr32b0/1mr3:0 equals the timer counter (tc), this output can either toggle, go low, go high, or do nothing. the external match register (emr) and the pwm control register (pwm con) control the fu nctionality of this output.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 374 of 543 nxp semiconductors um10398 chapter 21: lpc1100xl series: 32-bit counter/timer ct32b0/1 [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. table 328. register overview: 32-bit counter/timer 0 ct32b0 (base address 0x4001 4000) name access address offset description reset value [1] tmr32b0ir r/w 0x000 interrupt register (ir). the ir can be written to clear interrupts. the ir can be read to identify which of fi ve possible interrupt sources are pending. 0 tmr32b0tcr r/w 0x004 timer control register (t cr). the tcr is used to control the timer counter functions. the timer counter can be disabled or reset through the tcr. 0 tmr32b0tc r/w 0x008 timer counter (tc). the 32-bit tc is incremented every pr+1 cycles of pclk. the tc is controlled through the tcr. 0 tmr32b0pr r/w 0x00c prescale register (pr). when the prescale counter (below) is equal to this value, the next clock increments the tc and clears the pc. 0 tmr32b0pc r/w 0x010 prescale counter (pc). the 32 -bit pc is a counter which is incremented to the value stored in pr. when the value in pr is reached, the tc is incremented and the pc is cleared. the pc is observable and controllable through the bus interface. 0 tmr32b0mcr r/w 0x014 match control register (mcr). the mcr is used to control if an interrupt is generated and if the tc is reset when a match occurs. 0 tmr32b0mr0 r/w 0x018 match register 0 (mr0). mr0 can be enabled through the mcr to reset the tc, stop both the tc and pc, and/or generate an interrupt every time mr0 matches the tc. 0 tmr32b0mr1 r/w 0x01c match register 1 (mr1). see mr0 description. 0 tmr32b0mr2 r/w 0x020 match register 2 (mr2). see mr0 description. 0 tmr32b0mr3 r/w 0x024 match register 3 (mr3). see mr0 description. 0 tmr32b0ccr r/w 0x028 capture control register (ccr). the ccr controls which edges of the capture inputs are used to load the capture registers and whether or not an interrupt is generated when a capture takes place. 0 tmr32b0cr0 ro 0x02c capture register 0 (cr0). cr0 is loaded with the value of tc when there is an event on the ct32b0_cap0 input. 0 tmr32b0cr1 ro 0x030 capture register 1 (cr1). cr1 is loaded with the value of tc when there is an event on the ct32b0_cap1 input. 0 - - 0x034 - 0x038 reserved - tmr32b0emr r/w 0x03c external match register (emr). the emr controls the match function and the external match pins ct32b0_mat[3:0]. 0 - - 0x040 - 0x06c reserved - tmr32b0ctcr r/w 0x070 count control register (ctcr). the ctcr selects between timer and counter mode, and in counter mode selects the signal and edge(s) for counting. 0 tmr32b0pwmc r/w 0x074 pwm control register (pwmcon). the pwmcon enables pwm mode for the external match pins ct32b0_mat[3:0]. 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 375 of 543 nxp semiconductors um10398 chapter 21: lpc1100xl series: 32-bit counter/timer ct32b0/1 [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. table 329. register overview: 32-bit counter/timer 1 ct32b1 (base address 0x4001 8000) name access address offset description reset value [1] tmr32b1ir r/w 0x000 interrupt register (ir). the ir can be written to clear interrupts. the ir can be read to identify which of five possible interrupt sources are pending. 0 tmr32b1tcr r/w 0x004 timer control register (tcr). the tcr is used to control the timer counter functions. the timer counter can be disabled or reset through the tcr. 0 tmr32b1tc r/w 0x008 timer counter (tc). the 32-bit tc is incremented every pr+1 cycles of pclk. the tc is controlled through the tcr. 0 tmr32b1pr r/w 0x00c prescale register (pr). when the prescale counter (below) is equal to this value, the next clock increments the tc and clears the pc. 0 tmr32b1pc r/w 0x010 prescale counter (pc). the 32-bit pc is a counter which is incremented to the value stored in pr. when the value in pr is reached, the tc is incremented and the pc is cleared. the pc is observable and controllable through the bus interface. 0 tmr32b1mcr r/w 0x014 match control register (mcr). the mcr is used to control if an interrupt is generated and if the tc is reset when a match occurs. 0 tmr32b1mr0 r/w 0x018 match register 0 (mr0). mr0 can be enabled through the mcr to reset the tc, stop both the tc and pc, and/or generate an interrupt every time mr0 matches the tc. 0 tmr32b1mr1 r/w 0x01c match register 1 (mr1). see mr0 description. 0 tmr32b1mr2 r/w 0x020 match register 2 (mr2). see mr0 description. 0 tmr32b1mr3 r/w 0x024 match register 3 (mr3). see mr0 description. 0 tmr32b1ccr r/w 0x028 capture control register (ccr). the ccr controls which edges of the capture inputs are used to load th e capture registers and whether or not an interrupt is generated when a capture takes place. 0 tmr32b1cr0 ro 0x02c capture register 0 (cr0). cr0 is loaded with the value of tc when there is an event on the ct32b1_cap0 input. 0 tmr32b1cr1 ro 0x030 capture register 1 (cr1). cr1 is loaded with the value of tc when there is an event on the ct32b1_cap1 input. 0 - - 0x034 - 0x038 reserved - tmr32b1emr r/w 0x03c external match register (e mr). the emr controls the match function and the external match pins ct32b1_mat[3:0]. 0 - - 0x040 - 0x06c reserved - tmr32b1ctcr r/w 0x070 count control register (ctcr). the ctcr selects between timer and counter mode, and in counter mode selects the signal and edge(s) for counting. 0 tmr32b1pwmc r/w 0x074 pwm control register (pwmcon). the pwmcon enables pwm mode for the external match pins ct32b1_mat[3:0]. 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 376 of 543 nxp semiconductors um10398 chapter 21: lpc1100xl series: 32-bit counter/timer ct32b0/1 21.7.1 interrupt register (tmr32b0ir and tmr32b1ir) the interrupt register consists of four bits for the match interrupts and one bit for the capture interrupts. if an interrupt is g enerated then the corresponding bit in the ir will be high. otherwise, the bit will be low. writing a logic one to the corresponding ir bit will reset the interrupt. writing a zero has no effect. 21.7.2 timer control register (tmr32b0tcr and tmr32b1tcr) the timer control register (tcr) is used to control the operation of the counter/timer. 21.7.3 timer counter (tmr32b0 tc - address 0x4001 4008 and tmr32b1tc - address 0x4001 8008) the 32-bit timer counter is incremented when the prescale counter reaches its terminal count. unless it is reset be fore reaching its upper limit, th e tc will count up through the value 0xffff ffff and then wrap back to the value 0x0000 0000. this event does not cause an interrupt, but a match register can be used to detect an overflow if needed. table 330: interrupt register (tmr32b0ir - address 0x4001 4000 and tmr32b1ir - address 0x4001 8000) bit description bit symbol description reset value 0 mr0int interrupt flag for match channel 0. 0 1 mr1int interrupt flag for match channel 1. 0 2 mr2int interrupt flag for match channel 2. 0 3 mr3int interrupt flag for match channel 3. 0 4 cr0int interrupt flag for capture channel 0 event. 0 5 cr1int interrupt flag for capture channel 1 event. 0 31:6 - reserved - table 331: timer control register (tmr32b0tcr - address 0x4001 4004 and tmr32b1tcr - address 0x4001 8004) bit description bit symbol description reset value 0 cen when one, the timer counter and prescale counter are enabled for counting. when zero, the counters are disabled. 0 1 crst when one, the timer counter and the prescale counter are synchronously reset on the next positive edge of pclk. the counters remain reset until tcr[1] is returned to zero. 0 31:2 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na table 332: timer counter registers (tmr32b0tc, address 0x4001 4008 and tmr32b1tc 0x4001 8008) bit description bit symbol description reset value 31:0 tc timer counter value. 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 377 of 543 nxp semiconductors um10398 chapter 21: lpc1100xl series: 32-bit counter/timer ct32b0/1 21.7.4 prescale register (tmr 32b0pr - address 0x4001 400c and tmr32b1pr - address 0x4001 800c) the 32-bit prescale register specifies the maximum value for the prescale counter. 21.7.5 prescale counter register (tmr32b0pc - address 0x4001 4010 and tmr32b1pc - address 0x4001 8010) the 32-bit prescale counter controls division of pclk by some constant value before it is applied to the timer counter. this allows control of the relationship between the resolution of the timer and the maximum time before t he timer overflows. the prescale counter is incremented on every pclk. when it reaches the value stored in the prescale register, the timer counter is incremented, and the prescale counter is reset on the next pclk. this causes the tc to increment on every pclk when pr = 0, every 2 pclks when pr = 1, etc. 21.7.6 match control register (tmr32b0mcr and tmr32b1mcr) the match control register is used to contro l what operations are performed when one of the match registers matches the timer counter. the function of each of the bits is shown in table 335 . table 333: prescale registers (tmr32b0pr, address 0x4001 400c and tmr32b1pr 0x4001 800c) bit description bit symbol description reset value 31:0 pr prescale value. 0 table 334: prescale counter registers (tmr32b0pc, address 0x4001 4010 and tmr32b1pc 0x4001 8010) bit description bit symbol description reset value 31:0 pc prescale counter value. 0 table 335: match control register (tmr32b0mcr - address 0x4001 4014 and tmr32b1mcr - address 0x4001 8014) bit description bit symbol value description reset value 0 mr0i interrupt on mr0: an interrupt is ge nerated when mr0 matches the value in the tc. 0 1 enabled 0 disabled 1 mr0r reset on mr0: the tc will be reset if mr0 matches it. 0 1 enabled 0 disabled 2 mr0s stop on mr0: the tc and pc will be stopped and tcr[0] will be set to 0 if mr0 matches the tc. 0 1 enabled 0 disabled
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 378 of 543 nxp semiconductors um10398 chapter 21: lpc1100xl series: 32-bit counter/timer ct32b0/1 21.7.7 match registers (tmr 32b0mr0/1/2/3 - addresses 0x4001 4018/1c/20/24 and tmr32b1mr0 /1/2/3 addresses 0x4001 8018/1c/20/24) the match register values are continuously compared to the timer counter value. when the two values are equal, acti ons can be triggere d automatically. the action possibilities are to generate an interrupt, reset the timer counter, or stop the timer. actions are controlled by the settings in the mcr register. 3 mr1i interrupt on mr1: an interrupt is ge nerated when mr1 matches the value in the tc. 0 1 enabled 0 disabled 4 mr1r reset on mr1: the tc will be reset if mr1 matches it. 0 1 enabled 0 disabled 5 mr1s stop on mr1: the tc and pc will be stopped and tcr[0] will be set to 0 if mr1 matches the tc. 0 1 enabled 0 disabled 6 mr2i interrupt on mr2: an interrupt is ge nerated when mr2 matches the value in the tc. 0 1 enabled 0 disabled 7 mr2r reset on mr2: the tc will be reset if mr2 matches it. 0 1 enabled 0 disabled 8 mr2s stop on mr2: the tc and pc will be stopped and tcr[0] will be set to 0 if mr2 matches the tc. 0 1 enabled 0 disabled 9 mr3i interrupt on mr3: an interrupt is ge nerated when mr3 matches the value in the tc. 0 1 enabled 0 disabled 10 mr3r reset on mr3: the tc will be reset if mr3 matches it. 0 1 enabled 0 disabled 11 mr3s stop on mr3: the tc and pc will be stopped and tcr[0] will be set to 0 if mr3 matches the tc. 0 1 enabled 0 disabled 31:12 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na table 335: match control register (tmr32b0mcr - address 0x4001 4014 and tmr32b1mcr - address 0x4001 8014) bit description bit symbol value description reset value
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 379 of 543 nxp semiconductors um10398 chapter 21: lpc1100xl series: 32-bit counter/timer ct32b0/1 21.7.8 capture control register (tmr32b0ccr and tmr32b1ccr) the capture control register is used to control whether the capture register is loaded with the value in the timer counter when the capture event occurs, and whether an interrupt is gene rated by the captur e event. setting bo th the rising and falling bits at the same time is a valid configuration, resulting in a capture event for both edges. in the description below, n represents the timer number, 0 or 1. table 336: match registers (tmr32b0mr0 to 3, addresses 0x4001 4018 to 24 and tmr32b1mr0 to 3, addresses 0x4001 8018 to 24) bit description bit symbol description reset value 31:0 match timer counter match value. 0 table 337: capture control register (tmr32b0cc r - address 0x4001 4028 and tmr32b1ccr - address 0x4001 8028) bit description bit symbol value description reset value 0 cap0re capture on ct32bn_cap0 rising edge: a sequence of 0 then 1 on ct32bn_cap0 will cause cr0 to be loaded with the contents of tc. 0 1 enabled 0 disabled 1 cap0fe capture on ct32bn_cap0 falling edge: a sequence of 1 then 0 on ct32bn_cap0 will cause cr0 to be loaded with the contents of tc. 0 1 enabled 0 disabled 2 cap0i interrupt on ct32bn_cap0 event: a cr0 load due to a ct32bn_cap0 event will generate an interrupt. 0 1 enabled 0 disabled 3 cap1re capture on ct32bn_cap1 rising edge: a sequence of 0 then 1 on ct32bn_cap1 will cause cr1 to be loaded with the contents of tc. 0 1 enabled 0 disabled 4 cap1fe capture on ct32bn_cap1 falling edge: a sequence of 1 then 0 on ct32bn_cap1 will cause cr1 to be loaded with the contents of tc. 0 1 enabled 0 disabled 5 cap1i interrupt on ct32bn_cap1 event: a cr1 load due to a ct32bn_cap1 event will generate an interrupt. 0 1 enabled 0 disabled 31:6 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 380 of 543 nxp semiconductors um10398 chapter 21: lpc1100xl series: 32-bit counter/timer ct32b0/1 21.7.9 capture register (tmr32b0c r0/1 - address 0x4001 402c/30 and tmr32b1cr0/1 - address 0x4001 802c/30) each capture register is associated with a device pin and may be loaded with the timer counter value when a specified event occurs on that pin. the settings in the capture control register register determine whether the capture function is enabled and whether a capture event happens on the rising edge of the associated pin, the falling edge, or on both edges. 21.7.10 external match register (tmr32b0emr and tmr32b1emr) the external match register provides both co ntrol and status of the external match pins cap32bn_mat[3:0]. if the match outputs are configured as pwm ou tput, the function of the external match registers is determined by the pwm rules ( section 21.8.2 rules for single edge controlled pwm outputs on page 385 ). table 338: capture registers (tmr32b0cr0/1, addresses 0x4001 402c/30 and tmr32b1cr0/1, addresses 0x4001 802c/30) bit description bit symbol description reset value 31:0 cap timer counter capture value. 0 table 339: external match register (tmr32b0emr - address 0x4001 403c and tmr32b1emr - address0x4001 803c) bit description bit symbol value description reset value 0 em0 external match 0. this bit reflects the state of output ct 32bn_mat0, whether or not this output is connected to its pin. when a match occurs between the tc and mr0, this bit can either toggle, go low, go high, or do nothing. bits emr[5:4] control the functionality of this output. this bit is driven to t he ct32b0_mat0/ct16b1_mat 0 pins if the match function is selected in the iocon registers (0 = low, 1 = high). 0 1 em1 external match 1. this bit reflects the state of output ct 32bn_mat1, whether or not this output is connected to its pin. when a match occurs between the tc and mr1, this bit can either toggle, go low, go high, or do nothing. bits emr[7:6] control the functionality of this output. this bit is driven to t he ct32b0_mat1/ct16b1_mat 1 pins if the match function is selected in the iocon registers (0 = low, 1 = high). 0 2 em2 external match 2. this bit reflects the state of output ct 32bn_mat2, whether or not this output is connected to its pin. when a match occurs between the tc and mr2, this bit can either toggle, go low, go high, or do nothing. bits emr[9:8] control the functionality of this output. this bit is driven to t he ct32b0_mat2/ct16b1_mat 2 pins if the match function is selected in the iocon registers (0 = low, 1 = high). 0 3 em3 external match 3. this bit reflects the state of output ct 32bn_mat3, whether or not this output is connected to its pin. when a match occurs between the tc and mr3, this bit can either toggle, go low, go high, or do nothing. bits emr[11:10] control the functionality of this ou tput. this bit is driven to the ct32b0_mat3/ct16b1_mat3 pins if the match function is selected in the iocon registers (0 = low, 1 = high). 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 381 of 543 nxp semiconductors um10398 chapter 21: lpc1100xl series: 32-bit counter/timer ct32b0/1 5:4 emc0 external match control 0. determines the functional ity of external match 0. 00 0x0 do nothing. 0x1 clear the corresponding external match bi t/output to 0 (ct32bn_matm pin is low if pinned out). 0x2 set the corresponding external match bit/ output to 1 (ct32bn_matm pin is high if pinned out). 0x3 toggle the corresponding external match bit/output. 7:6 emc1 external match control 1. determines the functional ity of external match 1. 00 0x0 do nothing. 0x1 clear the corresponding external match bi t/output to 0 (ct32bn_matm pin is low if pinned out). 0x2 set the corresponding external match bit/ output to 1 (ct32bn_matm pin is high if pinned out). 0x3 toggle the corresponding external match bit/output. 9:8 emc2 external match control 2. determines the functional ity of external match 2. 00 0x0 do nothing. 0x1 clear the corresponding external match bi t/output to 0 (ct32bn_matm pin is low if pinned out). 0x2 set the corresponding external match bit/ output to 1 (ct32bn_matm pin is high if pinned out). 0x3 toggle the corresponding external match bit/output. 11:10 emc3 external match control 3. determines the functional ity of external match 3. 00 0x0 do nothing. 0x1 clear the corresponding external match bi t/output to 0 (ct32bn_matm pin is low if pinned out). 0x2 set the corresponding external match bit/ output to 1 (ct32bn_matm pin is high if pinned out). 0x3 toggle the corresponding external match bit/output. 31:12 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na table 339: external match register (tmr32b0emr - address 0x4001 403c and tmr32b1emr - address0x4001 803c) bit description bit symbol value description reset value table 340. external match control emr[11:10], emr[9:8], emr[7:6], or emr[5:4] function 00 do nothing. 01 clear the corresponding external match bit/ou tput to 0 (ct32bn_matm pin is low if pinned out). 10 set the corresponding external match bit/output to 1 (ct32bn_matm pin is high if pinned out). 11 toggle the corresponding external match bit/output.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 382 of 543 nxp semiconductors um10398 chapter 21: lpc1100xl series: 32-bit counter/timer ct32b0/1 21.7.11 count control register (tmr32b0ctcr and tmr32b1tcr) the count control register (ctcr) is used to select between timer and counter mode, and in counter mode to select the pin and edge(s) for counting. when counter mode is chosen as a mode of operation, the cap input (selected by the ctcr bits 3:2) is sampled on every rising edge of the pclk clock. after comparing two consecutive samples of this cap input, one of the following four events is recognized: rising edge, falling edge, either of edges or no changes in th e level of the selected cap input. only if the identified event occurs, and the event corresponds to the one selected by bits 1:0 in the ctcr register, will the timer counter regist er be incremented. effective processing of the externally supplie d clock to the counter has some limitations. since two successive rising edges of the pclk clock are used to identify only one edge on the cap selected input, the frequency of th e cap input can not exceed one half of the pclk clock. consequently, duration of the high/low levels on the same cap input in this case can not be shorter than 1/(2 ? pclk). bits 7:4 of this register are used to enable and configure the capture-clears-timer feature. this feature allows for a designated edge on a particular cap input to reset the timer to all zeros. using this mechanism to clear the timer on the leading edge of an input pulse and performing a capture on the tr ailing edge permits direct pu lse-width measurement using a single capture input without the need to perform a subtraction operation in software. table 341: count control register (tmr32b0ctcr - address 0x4001 4070 and tmr32b1tcr - address 0x4001 8070) bit description bit symbol value description reset value 1:0 ctm counter/timer mode. this field selects which rising pclk edges can increment timers prescale counter (pc), or clear pc and increment timer counter (tc). timer mode: every rising pclk edge 00 0x0 timer mode: every rising pclk edge 0x1 counter mode: tc is incremented on rising edges on the cap input selected by bits 3:2. 0x2 counter mode: tc is incremented on falling edges on the cap input selected by bits 3:2. 0x3 counter mode: tc is incremented on both edges on the cap input selected by bits 3:2. 3:2 cis count input select. when bits 1:0 in this register are not 00, these bits select which cap pin is sampled for clocking: 00 0x0 ct32bn_cap0 0x1 ct32bn_cap1 0x2 reserved 0x3 reserved note: if counter mode is selected in the tnctcr, the 3 bits for that input in the capture control register (tnccr) must be programmed as 000. 4 encc setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs. 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 383 of 543 nxp semiconductors um10398 chapter 21: lpc1100xl series: 32-bit counter/timer ct32b0/1 21.7.12 pwm control register (tmr32b0pwmc and tmr32b1pwmc) the pwm control register is used to config ure the match outputs as pwm outputs. each match output can be independently set to pe rform either as pwm output or as match output whose function is controlled by the external match register (emr). for each timer, a maximum of three-single edge controlled pwm outputs can be selected on the matn[2:0] outputs. one additional match register determines the pwm cycle length. when a match occurs in any of the othe r match registers, the pwm output is set to high. the timer is reset by t he match register that is configured to set the pwm cycle length. when the timer is reset to zero, a ll currently high match outputs configured as pwm outputs are cleared. 7:5 selcc when bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. these bits have no effect when bit 4 is zero. 0 0x0 rising edge of cap0 clears the timer (if bit 4 is set). 0x1 falling edge of cap0 clears the timer (if bit 4 is set). 0x2 rising edge of cap1 clears the timer (if bit 4 is set). 0x3 falling edge of cap1 clears the timer (if bit 4 is set). 0x4 reserved. 0x5 reserved. 0x6 reserved. 0x7 reserved. 31:8 - - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - table 341: count control register (tmr32b0ctcr - address 0x4001 4070 and tmr32b1tcr - address 0x4001 8070) bit description ?continued bit symbol value description reset value table 342: pwm control register (tmr32b0pwmc - 0x4001 4074 and tmr32b1pwmc - 0x4001 8074) bit description bit symbol value description reset value 0 pwmen0 pwm channel 0 enable 0 0 ct32bn_mat0 is controlled by em0. 1 pwm mode is enabled for ct32bn_mat0. 1 pwmen1 pwm channel 1 enable 0 0 ct32bn_mat1 is controlled by em1. 1 pwm mode is enabled for ct32bn_mat1. 2 pwmen2 pwm channel 2 enable 0 0 ct32bn_mat2 is controlled by em2. 1 pwm mode is enabled for ct32bn_mat2.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 384 of 543 nxp semiconductors um10398 chapter 21: lpc1100xl series: 32-bit counter/timer ct32b0/1 21.8 functional description 21.8.1 example timer operation figure 81 shows a timer configured to reset the count and generate an interrupt on match. the prescaler is set to 2 and the match register set to 6. at the end of the timer cycle where the match occurs, the timer count is re set. this gives a full length cycle to the match value. the interrupt indicating that a ma tch occurred is generated in the next clock after the timer reached the match value. figure 82 shows a timer configured to stop and generate an interrupt on match. the prescaler is again set to 2 and the match register set to 6. in the next clock after the timer reaches the match value, the timer enable bit in tcr is cleare d, and the interrupt indicating that a match occurred is generated. 3 pwmen3 pwm channel 3 enable note: it is recommended to use match channel 3 to set the pwm cycle. 0 0 ct32bn_mat3 is controlled by em3. 1 pwm mode is enabled for ct32bn_mat3. 31:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na table 342: pwm control register (tmr32b0pwmc - 0x4001 4074 and tmr32b1pwmc - 0x4001 8074) bit description bit symbol value description reset value fig 81. a timer cycle in which pr =2, mrx=6, and both interrupt and reset on match are enabled pclk prescale counter interrupt timer counter timer counter reset 2 2 2 2000 0 1111 45 6 0 1
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 385 of 543 nxp semiconductors um10398 chapter 21: lpc1100xl series: 32-bit counter/timer ct32b0/1 21.8.2 rules for single edge controlled pwm outputs 1. all single edge controlled pwm outputs go low at the beginning of each pwm cycle (timer is set to zero) unless their match value is equal to zero. 2. each pwm output will go high when its matc h value is reached. if no match occurs (i.e. the match value is greater than the pwm cycle length), the pwm output remains continuously low. 3. if a match value larger than the pwm cycle length is written to the match register, and the pwm signal is high already, then the pwm signal will be cleared with the start of the next pwm cycle. 4. if a match register contains the same value as the timer reset value (the pwm cycle length), then the pwm output will be reset to low on the next clock tick after the timer reaches the match valu e. therefore, the pwm out put will always consist of a one clock tick wide positive pulse with a period determined by the pwm cycle length (i.e. the timer reload value). 5. if a match register is set to zero, then the pwm output will go to high the first time the timer goes back to zero and will stay high continuously. note: when the match outputs are selected to function as pwm outputs, the timer reset (mrnr) and timer stop (mrns) bits in the match control register mcr must be set to 0 except for the match register setting the pwm cycle length. for th is register, set the mrnr bit to 1 to enable the timer reset w hen the timer value matches the value of the corresponding match register. fig 82. a timer cycle in which pr=2, mrx=6, and both interrupt and stop on match are enabled pclk prescale counter interrupt timer counter tcr[0] (counter enable) 2 20 0 1 45 6 1 0 fig 83. sample pwm waveforms with a pwm cycl e length of 100 (selected by mr2) and mat2:0 enabled as pwm outputs by the pwmc register. 100 (counter is reset) 04165 pwm0/mat0 pwm1/mat1 pwm2/mat2 mr2 = 100 mr1 = 41 mr0 = 65
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 386 of 543 nxp semiconductors um10398 chapter 21: lpc1100xl series: 32-bit counter/timer ct32b0/1 21.9 architecture the block diagram for 32-bit counter/timer0 and 32-bit counter/timer1 is shown in figure 84 . fig 84. 32-bit counter/ timer block diagram reset maxval timer control register prescale register prescale counter pclk enable capture register 1 match register 3 match register 2 match register 1 match register 0 capture control register control timer counter csn tci ce = = = = interrupt register external match register match control register mat[3:0] interrupt cap0 stop on match reset on match load[3:0] capture register 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 387 of 543 22.1 how to read this chapter this chapter describes the windowed wdt available on all parts of the lpc1100l and lpc1100xl series. 22.2 basic configuration the wdt is configured using the following registers: 1. pins: the wdt uses no external pins. 2. power: in the sysahbclkct rl register, set bit 15 ( ta b l e 2 1 ). 3. peripheral clock: select the wdt clock source ( ta b l e 2 5 ) and enable the wdt peripheral clock by writing to the wdtclkdiv register ( ta b l e 2 7 ). remark: the frequency of the wa tchdog oscillator is undef ined after reset. the watchdog oscillator fr equency must be pr ogrammed by writing to the wdtoscctrl register (see ta b l e 1 3 ) before using the watchdog oscillator for the wdt. 4. lock features: once the wa tchdog timer is enabled by setting the wden bit in the wdmod register, the following lo ck features are in effect: a. the wden bit cannot be changed to 0, that is the wdt cannot be disabled. b. the watch dog clock source cannot be changed. if the wdt is needed in deep-sleep mode, sele ct the watch dog oscillator as the clock source before setting the wden bit. 22.3 features ? internally resets chip if not reloaded during the programmable time-out period. ? optional windowed operation requires reload to occur between a minimum and maximum time-out period, both programmable. ? optional warning interrupt can be generated at a programmable time prior to watchdog time-out. ? programmable 24-bit timer with internal fixed pre-scaler. ? selectable time period from 1,024 watchdog clocks (t wdclk ? 256 ? 4) to over 67 million watchdog clocks (t wdclk ? 2 24 ? 4) in increments of 4 watchdog clocks. ? safe watchdog operation. once enabled, requires a hardware reset or a watchdog reset to be disabled. ? a dedicated on-chip watc hdog oscillator provides a relia ble clock source that cannot be turned off when the watchdog timer is running. ? incorrect feed sequence causes immedi ate watchdog reset if the watchdog is enabled. ? the watchdog reload value can optionally be protected such that it can only be changed after the warning interrupt time is reached. um10398 chapter 22: lpc111x/lpc11cxx windowed watchdog timer (wdt) rev. 12.1 ? 7 august 2013 user manual
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 388 of 543 nxp semiconductors um10398 chapter 22: lpc111x/lpc11cxx windowed watchdog timer (wdt) ? flag to indicate watchdog reset. 22.4 applications the purpose of the watchdog timer is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. when enabled, a watchdog event will be generated if the user program fails to feed (or reload) the watchdog within a predetermined amoun t of time. the watchdog event will ca use a chip reset if configured to do so. when a watchdog window is programmed, an early watchdog feed is also treated as a watchdog event. this allows preventing situat ions where a system failure may still feed the watchdog. for example, application code co uld be stuck in an interrupt service that contains a watchdog feed. setting the window su ch that this would result in an early feed will generate a watchdog event, a llowing for system recovery. . 22.5 general description the watchdog consists of a fixed divide-by-4 pre-scaler and a 24-bit counter which decrements when clocked. the minimum value from which the counter decrements is 0xff. setting a value lower than 0xff causes 0xff to be loaded in the counter. hence the minimum watchdog interval is (t wdclk ? 256 ? 4) and the maximum watchdog interval is (t wdclk ? 2 24 ? 4) in multiples of (t wdclk ? 4). the watchdog should be used in the following manner: ? set the watchdog timer constant reload value in wdtc register. ? setup the watchdog timer operating mode in wdmod register. ? set a value for the watchdog window time in wdwindow register if windowed operation is required. ? set a value for the watchdog warning inte rrupt in the wdwarnint register if a warning interrup t is required. ? enable the watchdog by writing 0xaa fo llowed by 0x55 to the wdfeed register. ? the watchdog must be fed again before the watchdog counter reaches zero in order to prevent a watchdog event. if a window value is programmed, the feed must also occur after the watchdog co unter passes that value. when the watchdog timer is configured so that a watchdog event will caus e a reset and the counter reaches zero, t he cpu will be reset, loading th e stack pointer and program counter from the vector table as in the case of external reset. the watchdog time-out flag (wdtof) can be examined to determine if the watchdog has caused the reset condition. the wdtof flag must be cleared by software. when the watchdog timer is co nfigured to genera te a warning interr upt, the interrupt will occur when the counter matches the value defined by the wdwarnint register. the block diagram of the watchdog is shown below in the figure 85 . the synchronization logic (pclk - wdclk) is not shown in the block diagram.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 389 of 543 nxp semiconductors um10398 chapter 22: lpc111x/lpc11cxx windowed watchdog timer (wdt) 22.6 clock control the watchdog timer block uses two clocks: pc lk and wdclk. pclk is used for the apb accesses to the watchdog registers and is derived from the system clock (see figure 8 ). the wdclk is used for the watchdog timer co unting and is derived from the wdt clock divider in figure 8 . several clocks can be used as a clock source for wdt_clk clock: the irc, the watchdog oscillator, and the main clock. the clock source is selected in the syscon block (see table 25 ). the wdclk has its own clock divider ( ta b l e 2 7 ) which can also disable this clock. there is some synchronization logic between these two clock domains. when the wdmod and wdtc registers are updated by apb operatio ns, the new value will take effect in 3 wdclk cycles on the logic in the wdclk clock domain. when the watchdog timer is counting on wdclk, the synchroniz ation logic will first lock the value of the counter on wdclk and then synchronize it with the pclk for reading as the wdtv register by the cpu. the watchdog oscillator can be power ed down in the pdruncfg register ( table 44 ) if it is not used. the clock to the watchdog register block (pclk) can be disabled in the sysahbclkctrl register ( table 21 ) for power savings. remark: the frequency of the watchd og oscillator is undefined after reset. the watchdog oscillator frequency must be programmed by writin g to the wdtoscct rl register (see ta b l e 1 3 ) before using the watchdog oscillator for the wdt. fig 85. windowed watchdog timer (wwdt) block diagram watchdog interrupt wdreset (mod [1]) wdtof (mod [2]) wdint (mod [3]) wden (mod [0]) chip reset 4 feed error feed ok wd_clk enable count mod register compare wdtv compare in range underflow feed sequence detect and protection feed feed ok feed ok compare 0 interrupt compare 24-bit down counter wdintval window tc shadow bit wdprotect (mod [4]) tc write
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 390 of 543 nxp semiconductors um10398 chapter 22: lpc111x/lpc11cxx windowed watchdog timer (wdt) 22.7 register description the watchdog contains the registers shown in table 343 . [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. 22.7.1 watchdog mode register the wdmod register controls the operation of the watchdog as per the combination of wden and reset bits. note that a watchdog feed must be performed before any changes to the wdmod register take effect. table 343. register overview: watchdog timer (base address 0x4000 4000) name access address offset description reset value [1] wdmod r/w 0x000 watchdog mode register. this register contains the basic mode and status of the watchdog timer. 0 wdtc r/w 0x004 watchdog timer constant r egister. this register determines the time-out value. 0xff wdfeed wo 0x008 watchdog feed sequence register. writing 0xaa followed by 0x55 to this register reloads the watchdog timer with the value contained in wdtc. - wdtv ro 0x00c watchdog timer value register . this register reads out the current value of the watchdog timer. 0xff wdwarnint r/w 0x014 watchdog warning interrupt compare value. 0 wdwindow r/w 0x018 watchdog window compare value. 0xff ffff table 344: watchdog mode register (wdmod - 0x4000 4000) bit description bit symbol value description reset value 0 wden watchdog enable bit. this bit is set only. remark: setting this bit to one also locks the watchdog clock source. once the watchdog timer is enabled, the watchdog timer clock source cannot be changed. if the watchdog timer is needed in deep-sleep mode, the watchdog clock source must be changed to the watchdog oscillator before setting this bit to one. 0 0 the watchdog timer is stopped. 1 the watchdog timer is running. 1 wdreset watchdog reset enable bit. this bit is set only. 0 0 a watchdog timeout will not cause a chip reset. 1 a watchdog timeout will cause a chip reset. 2 wdtof watchdog time-out flag. set when the watchdog timer times out, by a feed error, or by events associated with wdprotect, cleared by software. causes a chip reset if wdreset = 1. 0 (only after external reset) 3 wdint watchdog interrupt flag. set when the timer reaches the value in wdwarnint. cleared by software. 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 391 of 543 nxp semiconductors um10398 chapter 22: lpc111x/lpc11cxx windowed watchdog timer (wdt) once the wden , wdprotect , or wdreset bits are set they can not be cleared by software. both flags are cleared by an external reset or a watchdog timer reset. wdtof the watchdog time-out flag is set when the watchdog times out, when a feed error occurs, or when wdprotect =1 and an attempt is made to write to the wdtc register. this flag is cleared by software writing a 0 to this bit. wdint the watchdog interrupt flag is set when the watchdog counter reaches the value specified by wdwarnint. this flag is cleared when any reset occurs, and is cleared by software by writing a 1 to this bit. watchdog reset or interrupt will occur any time the watchdog is running. if a watchdog interrupt occurs in sleep mode , it will wake up the device. 22.7.2 watchdog timer constant register the wdtc register determines the time-out value. every time a feed sequence occurs the wdtc content is reloaded in to the watchdog timer. this is pre-loaded with the value 0x00 00ff upon reset. writing values below 0xff will cause 0x00 00ff to be loaded into the wdtc. thus the minimum time-out interval is t wdclk ? 256 ? 4. if the wdprotect bit in wdmod = 1, an atte mpt to change the value of wdtc before the watchdog counter is below the values of wdwarnint and wdwindow will cause a watchdog reset and set the wdtof flag. 4 wdprotect watchdog update mode. this bit is set only. 0 0 the watchdog reload value (wdtc) can be changed at any time. 1 the watchdog reload value (wdtc) can be changed only after the counter is below the value of wdwarnint and wdwindow. note : this mode is intended for use only when wdreset =1. 31: 5 - reserved. read value is undefined, only zero should be written. - table 345. watchdog operating modes selection wden wdreset mode of operation 0 x (0 or 1) debug/operate without the watchdog running. 1 0 watchdog interrupt mode: the watchdog warning interrupt will be generated but watchdog reset will not. when this mode is selected, the watchdog counter reaching the valu e specified by wdwarnint will set the wdint flag and the watchdog interrupt request will be generated. 1 1 watchdog reset mode: both the watchdog interrupt and watchdog reset are enabled. when this mode is selected, the watchdog counter reaching the value specified by wdwarnint will set the wdint flag and the watchdog interrupt request will be generated, and the watchdog counter reaching zero will reset the microcontroller. a watchdog feed prior to reaching the value of wdwindow will also cause a watchdog reset. table 344: watchdog mode register (wdmod - 0x4000 4000) bit description bit symbol value description reset value
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 392 of 543 nxp semiconductors um10398 chapter 22: lpc111x/lpc11cxx windowed watchdog timer (wdt) 22.7.3 watchdog feed register writing 0xaa followed by 0x55 to this register will reload the watchdog timer with the wdtc value. this operation will also start the watchdog if it is enabled via the wdmod register. setting the wden bit in the wdmod register is not sufficient to enable the watchdog. a valid feed sequence must be completed after setting wden before the watchdog is capable of gener ating a reset. until then, the watchdog will ignore feed errors. after writing 0xaa to wdfeed, access to any watchdog register other than writing 0x55 to wdfeed causes an immediate rese t/interrupt when the watchdog is enabled, and sets the wdtof flag. the reset will be ge nerated during the second pclk following an incorrect access to a watchdog register during a feed sequence. 22.7.4 watchdog timer value register the wdtv register is used to read the current value of watchdog timer counter. when reading the value of the 24-bit counter, the lock and synchronization procedure takes up to 6 wdclk cycles plus 6 pclk cycles, so the value of wdtv is older than the actual value of the timer when it's being read by the cpu. 22.7.5 watchdog timer warning interrupt register the wdwarnint register determines t he watchdog timer counter value that will generate a watchdog interrupt. when the watchdog timer counter matches the value defined by wdwarnint, an interrupt will be generated af ter the subseq uent wdclk. a match of the watchdog timer counter to wdwarnint occurs when the bottom 10 bits of the counter have the same value as the 10 bits of warnint, and the remaining upper bits of the counter are all 0. this gives a maximum time of 1,023 watchdog timer counts (4,096 watchdog clocks) for the interrupt to occur prior to a watchdog event. if warnint is set to 0, the interrup t will occur at the same time as the watchdog event. table 346: watchdog timer constant regist er (wdtc - 0x4000 4004) bit description bit symbol description reset value 23:0 count watchdog time-out interval. 0x00 00ff 31:24 - reserved. read value is undefined, only zero should be written. na table 347: watchdog feed register (wdfeed - 0x4000 4008) bit description bit symbol description reset value 7:0 feed feed value should be 0xaa followed by 0x55. - 31:8 - reserved - table 348: watchdog timer value register (wdtv - 0x4000 400c) bit description bit symbol description reset value 23:0 count counter timer value. 0x00 00ff 31:24 - reserved. read value is undefined, only zero should be written. -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 393 of 543 nxp semiconductors um10398 chapter 22: lpc111x/lpc11cxx windowed watchdog timer (wdt) 22.7.6 watchdog timer window register the wdwindow register determines the high est wdtv value allowed when a watchdog feed is performed. if a feed valid sequence comp letes prior to wdtv reaching the value in wdwindow, a watchdog event will occur. wdwindow resets to the maximum possible wdtv value, so windowing is not in effect. 22.7.7 watchdog timing examples the following figures illustra te several aspects of wa tchdog timer operation. table 349: watchdog timer warning interrupt register (wdwarnint - 0x4000 4014) bit description bit symbol description reset value 9:0 warnint watchdog warning interrupt compare value. 0 31:10 - reserved. read value is undefined, only zero should be written. - table 350: watchdog timer window register (wdwindow - 0x4000 4018) bit description bit symbol description reset value 23:0 window watchdog window value. 0xff ffff 31:24 - reserved. read value is undefined, only zero should be written. - fig 86. early watchdog feed with windowed mode enabled 125a 1258 1259 1257 wdclk / 4 watchdog counter early feed event watchdog reset conditions : window = 0x1200 warnint = 0x3ff tc = 0x2000
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 394 of 543 nxp semiconductors um10398 chapter 22: lpc111x/lpc11cxx windowed watchdog timer (wdt) fig 87. correct watchdog feed with windowed mode enabled correct feed event 1201 11ff 1200 wdclk / 4 watchdog counter watchdog reset 11fc 11fd 2000 1ffe 1fff 11fe 1ffd 1ffc conditions : wdwindow = 0x1200 wdwarnint = 0x3ff wdtc = 0x2000 fig 88. watchdog warning interrupt watchdog interrupt 0403 0401 0402 wdclk / 4 watchdog counter 03fe 03ff 03fd 03fb 03fc 0400 03fa 03f9 conditions : window = 0x1200 warnint = 0x3ff tc = 0x2000
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 395 of 543 23.1 how to read this chapter the wdt block (not windowed) is available for parts lpc111x and lpc11cxx. for parts lpc11cxx only, a clock source lo ck feature is implem ented whenever the wdt is enabled. 23.2 basic configuration the wdt is configured using the following registers: 1. pins: the wdt uses no external pins. 2. power: in the sysahbclkct rl register, set bit 15 ( ta b l e 2 1 ). 3. peripheral clock: select the watchdog clock source ta b l e 2 5 ) and enable the wdt peripheral clock by writing to the wdtclkdiv register ( ta b l e 2 7 ). remark: the frequency of the wa tchdog oscillator is undef ined after reset. the watchdog oscillator fr equency must be pr ogrammed by writing to the wdtoscctrl register (see ta b l e 1 3 ) before using the watchdog oscillator for the wdt. 4. lock features: once the wa tchdog timer is enabled by setting the wden bit in the wdmod register, the following lo ck features are in effect: a. the wden bit cannot be changed to 0, that is the wdt cannot be disabled (lpc111x/101/201/301 and lpc11cxx). b. the watch dog clock source cannot be changed. if the wdt is needed in deep-sleep mode, sele ct the watch dog oscillator as the clock source before setting the wden bit. (lpc11cxx only). 23.3 features ? internally resets chip if not period ically reloaded. ? debug mode. ? enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. ? incorrect/incomplete feed sequence causes reset/interrupt if enabled. ? flag to indicate watchdog reset. ? programmable 24 bit timer with internal pre-scaler. ? selectable time period from (t wdclk ? 256 ? 4) to (t wdclk ? 2 24 ? 4) in multiples of t wdclk ? 4. ? the watchdog clock (wdclk) source is selected in the syscon block from the internal rc oscillator (irc), the main cl ock, or the watchdog oscillator, see ta b l e 2 5 . this gives a wide range of potential timing choices for watchdog operation under different power reduct ion conditions. for increased relia bility, it also provides the ability to run the watchdog timer from an enti rely internal source that is not dependent on an external crystal and its associated components and wiring. um10398 chapter 23: lpc111x/lpc11cxx watchdog timer (wdt) rev. 12.1 ? 7 august 2013 user manual
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 396 of 543 nxp semiconductors um10398 chapter 23: lpc111x/lpc11cxx watchdog timer (wdt) 23.4 applications the purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an errone ous state. when enab led, the watchdog will generate a system reset if the user program fails to feed (or reload) the watchdog within a predetermined amount of time. 23.5 description the watchdog consists of a divide by 4 fixed pre-scaler and a 24-bit counter. the clock is fed to the timer via a pre-scaler. the time r decrements when clocked. the minimum value from which the counter decrements is 0xff. se tting a value lower than 0xff causes 0xff to be loaded in the coun ter. hence the minimum watchdog interval is (t wdclk ? 256 ? 4) and the maximum watchdog interval is (t wdclk ? 2 24 ? 4) in multiples of (t wdclk ? 4). the watchdog should be used in the following manner: 1. set the watchdog timer constant reload value in wdtc register. 2. setup the watchdog timer operating mode in wdmod register. 3. enable the watchdog by writing 0xaa followed by 0x55 to the wdfeed register. 4. the watchdog should be fed again before the watchdog counter underflows to prevent reset/interrupt. when the watchdog is in the reset mode and the counte r underflows, the cpu will be reset, loading the stack pointer and program counter from the vector table as in the case of external reset. the watchdog time-out fl ag (wdtof) can be examined to determine if the watchdog has caused the reset conditi on. the wdtof flag must be cleared by software. 23.6 wdt clocking the watchdog timer block uses two clocks: pc lk and wdclk. pclk is used for the apb accesses to the watchdog registers and is derived from the system clock (see figure 8 ). the wdclk is used for the watchdog timer counting and is derived from the wdt_clk in figure 8 . several clocks can be used as a clock source for wdt_clk clock: the irc, the watchdog oscillator, and the main clock. the cl ock source is selected in the syscon block (see table 25 ). the wdclk has its own clock divider ( section 3.5.20 ), which can also disable this clock. there is some synchronization logic between these two clock domains. when the wdmod and wdtc registers are updated by apb operatio ns, the new value will take effect in 3 wdclk cycles on the logic in the wdclk clock domain. when the watchdog timer is counting on wdclk, the synchroniz ation logic will first lock the value of the counter on wdclk and then synchronize it with the pclk for reading as the wdtv register by the cpu. remark: the frequency of the watchd og oscillator is undefined after reset. the watchdog oscillator frequency must be programmed by writin g to the wdtoscct rl register (see ta b l e 1 3 ) before using the watchdog oscillator for the wdt.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 397 of 543 nxp semiconductors um10398 chapter 23: lpc111x/lpc11cxx watchdog timer (wdt) 23.7 register description the watchdog contains four registers as shown in table 351 below. [1] reset value reflects the data stored in used bits only. it does not include reserved bits content. 23.7.1 watchdog mode regi ster (wdmod - 0x4000 0000) the wdmod register controls the operation of the watchdog through the combination of wden and reset bits. note that a watchdog feed must be performed before any changes to the wdmod register take effect. once the wden and/or wdreset bits are set, they can not be cleared by software. both flags are cleared by a reset or a watchdog timer underflow. wdtof the watchdog time-out flag is set when the watchdog times out. this flag is cleared by software or a por or brown-out-detect reset. table 351. register overview: watchdog timer (base address 0x4000 4000) name access address offset description reset value [1] wdmod r/w 0x000 watchdog mode register. this register contains the basic mode and status of the watchdog timer. 0 wdtc r/w 0x004 watchdog timer consta nt register. this register determines the time-out value. 0xff wdfeed wo 0x008 watchdog feed sequence register. writing 0xaa followed by 0x55 to this register reloads the watchdog timer with the value contained in wdtc. na wdtv ro 0x00c watchdog timer value register. this register reads out the current value of the watchdog timer. 0xff table 352. watchdog mode register (wdmod - address 0x4000 4000) bit description bit symbol description reset value 0 wden wden watchdog enable bit (set only). when 1, the watchdog timer is running. remark: setting this bit to one also locks the watchdog clock source. once the watchdog timer is enabled, the watchdog timer clock source cannot be changed. if the watchdog timer is needed in deep-sleep mode, the watchdog clock source must be changed to the watchdog oscillator before setting this bit to one. the clock source lock feature is not available on all parts, see section 23.1 ). 0 1 wdreset wdreset watchdog reset enable bit (set only). when 1, a watchdog time-out will cause a chip reset. 0 2 wdtof wdtof watchdog time-out flag. set when the watchdog timer times out, cleared by software. 0 (only after por and bod reset) 3 wdint wdint watchdog interrupt flag (read only, not clearable by software). 0 7:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na 31:8 - reserved -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 398 of 543 nxp semiconductors um10398 chapter 23: lpc111x/lpc11cxx watchdog timer (wdt) wdint the watchdog interrupt flag is set wh en the watchdog times out. this flag is cleared when any reset occurs. once the wa tchdog interrupt is serviced, it can be disabled in the nvic or the watchdog interrup t request will be generat ed indefinitely. the intent of the watchdog interrupt is to allow debugging watchdog activity without resetting the device when the watchdog overflows. watchdog reset or interrupt will occur any ti me the watchdog is running and has an operating clock source. any clock source works in sleep mode, and if a watchdog interrupt occurs in sleep mode , it will wake up the device. 23.7.2 watchdog timer constant register (wdtc - 0x4000 4004) the wdtc register determines the time-out value. every time a feed sequence occurs the wdtc content is reloaded in to the watchdog timer. its a 32-bit register with 8 lsb set to 1 on reset. writing values below 0x ff will cause 0x0000 00ff to be loaded to the wdtc. thus the minimum time-out interval is t wdclk ? 256 ? 4. 23.7.3 watchdog feed register (wdfeed - 0x4000 4008) writing 0xaa followed by 0x55 to this register will reload the watchdog timer with the wdtc value. this operation will also start the watchdog if it is enabled via the wdmod register. setting the wden bit in the wdmod register is not sufficient to enable the watchdog. a valid feed sequence must be completed after setting wden before the watchdog is capable of gener ating a reset. until then, the watchdog will ignore feed errors. after writing 0xaa to wdfeed, access to any watchdog register other than writing 0x55 to wdfeed causes an immediate rese t/interrupt when the watchdog is enabled. the reset will be generate d during the second pclk follo wing an incorrec t access to a watchdog register during a feed sequence. table 353. watchdog operating modes selection wden wdreset mode of operation 0 x (0 or 1) debug/operate without the watchdog running. 1 0 watchdog interrupt mode: debug with the watchdog interrupt but no wdreset enabled. when this mode is selected, a watchdog counter underflow will set the wdint flag and the watchdog interrupt request will be generated. remark: in interrupt mode, check the wdin t flag. if this flag is set, the interrupt is true and can be serviced by the interrupt routine. if this flag is not set, the interrupt should be ignored. 1 1 watchdog reset mode: operate with the watchdog interrupt and wdreset enabled. when this mode is selected, a watc hdog counter underflow will reset the microcontroller. although the wa tchdog interrupt is also enabled in this case (wden = 1) it will not be recognized since the watchdog reset will clear the wdint flag. table 354. watchdog constant register (wdtc - address 0x4000 4004) bit description bit symbol description reset value 23:0 count watchdog time-out interval. 0x0000 00ff 31:25 - reserved -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 399 of 543 nxp semiconductors um10398 chapter 23: lpc111x/lpc11cxx watchdog timer (wdt) interrupts should be disabled during the feed sequence. an abo rt condition will occur if an interrupt happens during the feed sequence. 23.7.4 watchdog timer value register (wdtv - 0x4000 400c) the wdtv register is used to read the current value of watchdog timer. when reading the value of the 24-bit timer, the lock and synchronization procedure takes up to 6 wdclk cycles plus 6 pclk cycles, so the value of wdtv is older than the actual value of the timer when it's being read by the cpu. 23.8 block diagram the block diagram of the watchdog is shown below in the figure 89 . the synchronization logic (pclk/wdclk) is not shown in the block diagram. table 355. watchdog feed register (wdfeed - address 0x4000 4008) bit description bit symbol description reset value 7:0 feed feed value should be 0xaa followed by 0x55. na 31:8 - reserved - table 356. watchdog timer value register (wdtv - address 0x4000 000c) bit description bit symbol description reset value 23:0 count counter timer value. 0x0000 00ff 31:24 - reserved - fig 89. watchdog block diagram wdtc 24-bit down counter wdint wdtof wdreset wden shadow bit reset interrupt ??4 wdfeed feed ok feed error wdt_clk underflow enable count wmod register feed sequence
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 400 of 543 24.1 how to read this chapter the system tick timer (systick timer) is part of the arm cortex-m0 core and is identical for all lpc111x, lpc11d14, and lpc11cxx parts. 24.2 basic configuration the system tick timer is config ured using the following registers: 1. pins: the system tick timer uses no external pins. 2. power: the system tick timer is enabl ed through the systick control register syst_csr ( table 358 ). the systick control register also allows changing the clock source to the systick timer 3. enable the clock source for the systick timer in the syst_csr register ( ta b l e 3 5 8 ). 24.3 features ? simple 24-bit timer. ? uses dedicated exception vector. ? clocked internally by the syste m clock or the system clock/2. 24.4 general description the block diagram of the systick timer is shown below in the figure 90 . the systick timer is an integral part of the cortex-m0. the systick timer is intended to generate a fixed 10 millisecon d interrupt for use by an oper ating system or other system management software. um10398 chapter 24: lpc111x/lpc11cxx s ystem tick timer (systick) rev. 12.1 ? 7 august 2013 user manual fig 90. system tick timer block diagram system clock reference clock = system clock/2 syst_calib syst_rvr syst_cvr 24-bit down counter enable syst_csr private peripheral bus system tick interrupt tickint countflag load under - flow count enable clock load data 1 0 syst_csr bit clksource
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 401 of 543 nxp semiconductors um10398 chapter 24: lpc111x/lpc11cxx system tick timer (systick) since the systick timer is a part of the cort ex-m0, it facilitates porting of software by providing a standard timer that is availabl e on cortex-m0 based devices. the systick timer can be used for: ? an rtos tick timer which fires at a programmable rate (for example 100 hz) and invokes a systick routine. ? a high-speed alarm timer using the core clock. ? a simple counter. software can use this to measure time to completion and time used. ? an internal clock source control based on missing/meeting durations. the countflag bit-field in the control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. refer to the cortex-m0 user guide for details. 24.5 register description the systick timer registers are located on the arm cortex-m0 private peripheral bus (see figure 98 ), and are part of the arm cortex-m0 core peripherals. for details, see section 28.6.4 . [1] reset value reflects the data stored in used bits only. it does not include content of reserved bits. 24.5.1 system timer cont rol and status register the syst_csr register contains control information for the systick timer and provides a status flag. this register is part of the ar m cortex-m0 core system timer register block. for a bit description of this register, see section 28.6.4 system timer, systick . this register determines the clock source for the system tick timer. table 357. register overview: systi ck timer (base address 0xe000 e000) name access address offset description reset value [1] syst_csr r/w 0x010 system timer contro l and status register 0x000 0000 syst_rvr r/w 0x014 system timer reload value register 0 syst_cvr r/w 0x018 system timer current value register 0 syst_calib r/w 0x01c system timer calibration value register 0x4
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 402 of 543 nxp semiconductors um10398 chapter 24: lpc111x/lpc11cxx system tick timer (systick) 24.5.2 system timer reload value register the syst_rvr register is set to the value that will be loaded in to the systick timer whenever it counts down to zero. this regist er is loaded by software as part of timer initialization. the syst_calib register may be read an d used as the value for syst_rvr register if the cpu is running at the frequency intend ed for use with the syst_calib value. 24.5.3 system timer current value register the syst_cvr register re turns the current count from the system tick counter when it is read by software. table 358. systick timer control and status register (syst_csr - 0xe000 e010) bit description bit symbol description reset value 0 enable system tick counter enable. when 1, the counter is enabled. when 0, the counter is disabled. 0 1 tickint system tick interrupt enable. when 1, the system tick interrupt is enabled. when 0, the system tick interrupt is disabled. when enabled, the interrupt is generated when the system tick counter counts down to 0. 0 2 clksource system tick clock source se lection. when 1, the system clock (cpu) clock is selected. when 0, the system clock/2 is selected as the reference clock. 0 15:3 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na 16 countflag returns 1 if the systick time r counted to 0 since the last read of this register. 0 31:17 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na table 359. system timer reload value register (syst_rvr - 0x e000 e014) bit description bit symbol description reset value 23:0 reload this is the value that is lo aded into the system tick counter when it counts down to 0. 0 31:24 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na table 360. system timer current value register (syst_cvr - 0x e000 e018) bi t description bit symbol description reset value 23:0 current reading this register return s the current value of the system tick counter. writing any value clears the system tick counter and the countflag bit in stctrl. 0 31:24 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 403 of 543 nxp semiconductors um10398 chapter 24: lpc111x/lpc11cxx system tick timer (systick) 24.5.4 system timer calibration value register (syst_cal ib - 0xe000 e01c) the value of the syst_cal ib register is driv en by the value of the systckcal register in the system configuration block (see ta b l e 3 4 ). 24.6 functional description the systick timer is a 24-bit timer that counts down to zero and generates an interrupt. the intent is to provide a fixed 10 millisecond time interv al between interrupts. the systick timer is clocked from the cpu clock (the system clock, see figure 8 ) or from the reference clock, which is fixed to half the fre quency of the cpu clock. in order to generate recurring interrupts at a specific interval, the syst_rvr register must be initialized with the correct value for the desired interval. a default value is provid ed in the syst_calib register and may be changed by software . the default value gives a 10 millisecond interrupt rate if the cpu clock is set to 50 mhz. 24.7 example timer calculations to use the system tick timer, do the following: 1. program the syst_rvr regist er with the reload value reload to obtain the desired time interval. 2. clear the syst_cvr register by writing to it. this ensures that the timer will count from the syst_rvr value rather than an arbitrary value when the timer is enabled. 3. program the syst_scr register with the value 0x7 which enables the systick timer and the systick timer interrupt. the following example illustrates selecting the systick timer reload value to obtain a 10 ms time interval with the lpc111x/lp c11cxx system clock set to 50 mhz. example (system clock = 50 mhz) the system tick clock = system clock = 50 mhz. bit clksource in the syst_csr register set to 1 (system clock). reload = (system tick clock frequency ? 10 ms) ? 1 = (50 mhz ? 10 ms) ? 1 = 500000 ?? 1 = 499999 = 0x0007a11f. table 361. system timer calibr ation value register (syst_c alib - 0xe000 e01c) bit description bit symbol value description reset value 23:0 tenms see table 462 .0 x 4 29:24 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na 30 skew see table 462 .0 31 noref see table 462 .0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 404 of 543 25.1 how to read this chapter the adc block is identical for all lpc111x, lpc11d14, and lpc11cxx parts. all hvqfn33 and lqfp48 packages support eight adc channels. on the small packages (tssop28/dip28/tssop20/so20), only five or six adc channels are pinned out (see table 3 ). 25.2 basic configuration the adc is configured us ing the following registers: 1. pins: the adc pin functions are configured in the ioconfig register block ( section 7.4 ). 2. power and peripheral clock: in the sysahbclkctrl regist er, set bit 13 ( ta b l e 2 1 ). power to the adc at run-time is co ntrolled through the pdruncfg register ( ta b l e 4 4 ). remark: basic clocking for the a/d converters is determined by the apb clock (pclk). a programmable divider is included in the a/d co nverter to scale this clock to the 4.5 mhz (max) clock needed by the su ccessive approximation process. an accurate conversion requires 11 clock cycles. 25.3 features ? 10-bit successive approximation analog-to-digital converter (adc). ? input multiplexing among 8 pins. ? power-down mode. ? measurement range 0 to 3.6 v. do not exceed the v dd voltage level. ? 10-bit conversion time ? 2.44 ? s. ? burst conversion mode for single or multiple inputs. ? optional conversion on transition on input pin or timer match signal. ? individual result registers for each a/d channel to reduce interrupt overhead. 25.4 pin description table 362 gives a brief summary of the adc related pins. um10398 chapter 25: lpc111x/lpc11cxx adc rev. 12.1 ? 7 august 2013 user manual
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 405 of 543 nxp semiconductors um10398 chapter 25: lpc111x/lpc11cxx adc the adc function must be selected via the iocon registers in order to get accurate voltage readings on the monitored pin. for a pi n hosting an adc input, it is not possible to have a have a digital function selected and yet get valid adc readings. an inside circuit disconnects adc hardware from the associated pin whenever a digital function is selected on that pin. 25.5 register description the adc contains registers organized as shown in table 363 . [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. table 362. adc pin description pin type description ad[7:0] input analog inputs. the a/d converter cell can measure the voltage on any of these input signals. remark: while the pins are 5 v tolerant in digital mode, the maximum input voltage must not exceed v dd when the pins are configured as analog inputs. v dd input v ref ; reference voltage. table 363. register overview : adc (base address 0x4001 c000) name access address offset description reset value [1] ad0cr r/w 0x000 a/d control register. the ad0c r register must be written to select the operating mode before a/d conversion can occur. 0x0000 0000 ad0gdr r/w 0x004 a/d global data register. cont ains the result of the most recent a/d conversion. na - - 0x008 reserved. - ad0inten r/w 0x00c a/d interrupt enable register. th is register contains enable bits that allow the done flag of each a/d channel to be included or excluded from contributing to the generat ion of an a/d interrupt. 0x0000 0100 ad0dr0 r/w 0x010 a/d channel 0 data register. this register contains the result of the most recent conversion completed on channel 0 na ad0dr1 r/w 0x014 a/d channel 1 data register. this register contains the result of the most recent conversion completed on channel 1. na ad0dr2 r/w 0x018 a/d channel 2 data register. this register contains the result of the most recent conversion completed on channel 2. na ad0dr3 r/w 0x01c a/d channel 3 data register. this register contains the result of the most recent conversion completed on channel 3. na ad0dr4 r/w 0x020 a/d channel 4 data register. this register contains the result of the most recent conversion completed on channel 4. na ad0dr5 r/w 0x024 a/d channel 5 data register. this register contains the result of the most recent conversion completed on channel 5. na ad0dr6 r/w 0x028 a/d channel 6 data register. this register contains the result of the most recent conversion completed on channel 6. na ad0dr7 r/w 0x02c a/d channel 7 data register. this register contains the result of the most recent conversion completed on channel 7. na ad0stat ro 0x030 a/d status register. this r egister contains done and overrun flags for all of the a/d channels, as well as the a/d interrupt flag. 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 406 of 543 nxp semiconductors um10398 chapter 25: lpc111x/lpc11cxx adc 25.5.1 a/d control regist er (ad0cr - 0x4001 c000) the a/d control register provides bits to select a/d channels to be converted, a/d timing, a/d modes, and the a/d start trigger. table 364. a/d control register (ad0cr - address 0x4001 c000) bit description bit symbol value description reset value 7:0 sel selects which of the ad7:0 pins is (are) to be sampled and converted. bit 0 selects pin ad0, bit 1 selects pin ad1,..., and bit 7 selects pin ad7. in software-controlled mode (burst = 0), only one channel can be selected, i.e. only one of these bits should be 1. in hardware scan mode (burst = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. if all bits are se t to 0, channel 0 is selected automatically (sel = 0x01). 0x00 15:8 clkdiv the apb clock (pclk) is divided by clkd iv +1 to produce the cl ock for the adc, which should be less than or equal to 4.5 mhz. typica lly, software should program the smallest value in this field that yields a clock of 4.5 m hz or slightly less, bu t in certain cases (such as a high-impedance analog source) a slower clock may be desirable. 0 16 burst burst mode remark: if burst is set to 1, the adginten bit in the ad0inten register ( table 366 ) must be set to 0. 0 0 software-controlled mode: conversions are software-controlled and require 11 clocks. 1 hardware scan mode: the ad converter does repeated conversions at the rate selected by the clks field, scanning (if necessary) through the pins selected by 1s in the sel field. the first conversion after the start corr esponds to the least-significant bit set to 1 in the sel field, then the next higher bits (p ins) set to 1 are scanned if applicable. repeated conversions can be terminated by clearing th is bit, but the conversion in progress when this bit is cleared will be completed. important: start bits must be 000 when burst = 1 or conversions will not start. 19:17 clks this field selects the number of clocks used for each conversion in burst mode, and the number of bits of accuracy of the result in the ls bits of addr, between 11 clocks (10 bits) and 4 clocks (3 bits). 000 0x0 11 clocks / 10 bits 0x1 10 clocks / 9 bits 0x2 9 clocks / 8 bits 0x3 8 clocks / 7 bits 0x4 7 clocks / 6 bits 0x5 6 clocks / 5 bits 0x6 5 clocks / 4 bits 0x7 4 clocks / 3 bits 23:20 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 407 of 543 nxp semiconductors um10398 chapter 25: lpc111x/lpc11cxx adc [1] note that this does not require that the timer match function appear on a device pin. 25.5.2 a/d global data regi ster (ad0gdr - 0x4001 c004) the a/d global data register contains the resu lt of the most recent a/d conversion. this includes the data, done, and overrun flags, and the number of the a/d channel to which the data relates. 26:24 start when the burst bit is 0, these bits control whether and when an a/d conversion is started: 0 0x0 no start (this value should be used when clearing pdn to 0). 0x1 start conversion now. 0x2 start conversion when the edg e selected by bit 27 occurs on pio0_2/ssel/ct16b0_cap0. 0x3 start conversion when the edg e selected by bit 27 occurs on pio1_5/dir/ct32b0_cap0. 0x4 start conversion when the edge sele cted by bit 27 occurs on ct32b0_mat0 [1] . 0x5 start conversion when the edge sele cted by bit 27 occurs on ct32b0_mat1 [1] . 0x6 start conversion when the edge sele cted by bit 27 occurs on ct16b0_mat0 [1] . 0x7 start conversion when the edge sele cted by bit 27 occurs on ct16b0_mat1 [1] . 27 edge this bit is significant only when the start field contains 010-111. in these cases: 0 0 start conversion on a rising edge on the selected cap/mat signal. 1 start conversion on a falling edge on the selected cap/mat signal. 31:28 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na table 364. a/d control register (ad0cr - address 0x4001 c000) bit description bit symbol value description reset value table 365. a/d global data register (ad0 gdr - address 0x4001 c004) bit description bit symbol description reset value 5:0 - reserved. these bits always read as zeroes. 0 15:6 v_vref when done is 1, this field co ntains a binary fraction representing the voltage on the adn pin selected by the sel field, divided by the voltage on the v dd pin. zero in the field indicates that the voltage on the adn pin was less than, equal to, or close to that on v ss , while 0x3ff indicates that the voltage on adn was close to, equal to, or greater than that on v ref . x 23:16 - reserved. these bits always read as zeroes. 0 26:24 chn these bits contain the channel from which the result bits v_vref were converted. x 29:27 - reserved. these bits always read as zeroes. 0 30 overrun this bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the v_vref bits. 0 31 done this bit is set to 1 when an a/d conversion completes. it is cleared when this register is read and when the adcr is written. if the adcr is written while a conversion is still in progress, this bit is set and a new conversion is started. 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 408 of 543 nxp semiconductors um10398 chapter 25: lpc111x/lpc11cxx adc 25.5.3 a/d interrupt enable re gister (ad0inten - 0x4001 c00c) this register allows control over which a/d channels generate an interrupt when a conversion is complete. for example, it may be desirable to use some a/d channels to monitor sensors by continuously performi ng conversions on them. the most recent results are read by the application program whenever they are needed. in this case, an interrupt is not desirable at the end of each conversion for some a/d channels. 25.5.4 a/d data registers (ad0 dr0 to ad0dr7 - 0x4001 c010 to 0x4001 c02c) the a/d data register hold the result when an a/d conversion is complete, and also include the flags that indicate when a conversion has been completed and when a conversion overrun has occurred. table 366. a/d interrupt enable register (ad0inten - address 0x4001 c00c) bit description bit symbol description reset value 7:0 adinten these bits allow control over which a/d channels generate interrupts for conversion completion. when bit 0 is one, completion of a conversion on a/d channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on a/d channel 1 will generate an interrupt, etc. 0x00 8 adginten when 1, enables the global done flag in ad0drx to generate an interrupt. when 0, only the individual a/d channels enabled by adinten 7:0 will generate interrupts. remark: this bit must be set to 0 in burst mode (burst = 1 in the ad0cr register). 1 31:9 - reserved. unused, always 0. 0 table 367. a/d data registers (ad0dr0 to ad0dr7 - addresses 0x4001 c010 to 0x4001 c02c) bit description bit symbol description reset value 5:0 - reserved. 0 15:6 v_vref when done is 1, this field cont ains a binary fraction representing the voltage on the adn pin, divided by the voltage on the v ref pin. zero in the field indicates that the voltage on the adn pin was less than, equal to, or close to that on v ref , while 0x3ff indicates that the voltage on ad input was close to, equal to, or greater than that on v ref . na 29:16 - reserved. 0 30 overrun this bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the v_vref bits.this bit is cleared by reading this register. 0 31 done this bit is set to 1 when an a/d conversion completes. it is cleared when this register is read. 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 409 of 543 nxp semiconductors um10398 chapter 25: lpc111x/lpc11cxx adc 25.5.5 a/d status regist er (ad0stat - 0x4001 c030) the a/d status register allows checking the status of all a/d channels simultaneously. the done and overrun flags appearing in the addrn register for each a/d channel are mirrored in adstat. the interrupt flag (the logical or of all done flags) is also found in adstat. 25.6 operation 25.6.1 hardware-triggered conversion if the burst bit in the adcr0 is 0 and t he start field contains 010-111, the a/d converter will start a conv ersion when a transition occurs on a selected pin or timer match signal. 25.6.2 interrupts an interrupt is requested to the interrupt controller when the adint bit in the adstat register is 1. the adint bit is one when any of the done bits of a/d channels that are enabled for interrupts (via the adinten register) are one. software can use the interrupt enable bit in the interrupt controller that co rresponds to the adc to control whether this results in an interrupt. the result register for an a/d channel that is generating an interrupt must be read in order to clear the corresponding done flag. 25.6.3 accuracy vs. digital receiver while the a/d converter can be used to measure the voltage on any adc input pin, regardless of the pins setting in the ioco n block, selecting the adc in the iocon registers function improves the conversion accuracy by disabling the pins digital receiver (see also section 7.3.4 ). table 368. a/d status register (ad0stat - address 0x4001 c030) bit description bit symbol description reset value 7:0 done these bits mirror the done stat us flags that appear in the result register for each a/d channel n. 0 15:8 overrun these bits mirror the over rrun status flags that appear in the result register for each a/d channel n. reading adstat allows checking the status of all a/d channels simultaneously. 0 16 adint this bit is the a/d interrupt flag. it is one when any of the individual a/d channel done flags is asserted and enabled to contribute to the a/d interr upt via the adinten register. 0 31:17 - reserved. unused, always 0. 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 410 of 543 26.1 how to read this chapter see ta b l e 3 6 9 for different flash configurations. um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware rev. 12.1 ? 7 august 2013 user manual table 369. lpc111x/lpc11cx flash configurations type number flash configuration page erase iap command supported isp via uart isp via c_can lpc1110fd20 4 kb table 370 no yes no LPC1111fdh20/002 8 kb table 370 no yes no LPC1111fhn33/101 8 kb table 370 no yes no LPC1111fhn33/102 8 kb table 370 no yes no LPC1111fhn33/103 8 kb table 371 yes yes no LPC1111fhn33/201 8 kb table 370 no yes no LPC1111fhn33/202 8 kb table 370 no yes no LPC1111fhn33/203 8 kb table 371 yes yes no lpc1112fd20/102 16 kb table 370 no yes no lpc1112fdh20/102 16 kb table 370 no yes no lpc1112fdh28/102 16 kb table 370 no yes no lpc1112fhn33/101 16 kb table 370 no yes no lpc1112fhn33/102 16 kb table 370 no yes no lpc1112fhn33/103 16 kb table 371 yes yes no lpc1112fhn33/201 16 kb table 370 no yes no lpc1112fhn24/202 16 kb table 370 no yes no lpc1112fhn33/202 16 kb table 370 no yes no lpc1112fhn33/203 16 kb table 371 yes yes no lpc1112fhi33/202 16 kb table 370 no yes no lpc1112fhi33/203 16 kb table 371 yes yes no lpc1113fhn33/201 24 kb table 370 no yes no lpc1113fhn33/202 24 kb table 370 no yes no lpc1113fhn33/203 24 kb table 371 yes yes no lpc1113fhn33/301 24 kb table 370 no yes no lpc1113fhn33/302 24 kb table 370 no yes no lpc1113fhn33/303 24 kb table 371 yes yes no lpc1113fbd48/301 24 kb table 370 no yes no lpc1113fbd48/302 24 kb table 370 no yes no lpc1113fbd48/303 24 kb table 371 yes yes no lpc1114fdh28/102 32 kb table 370 no yes no lpc1114fn28/102 32 kb table 370 no yes no lpc1114fhn33/201 32 kb table 370 no yes no lpc1114fhn33/202 32 kb table 370 no yes no lpc1114fhn33/203 32 kb table 371 yes yes no
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 411 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware remark: in addition to the isp and iap commands, a register in the flash controller block can be accessed to configure flash memory access times, see section 26.9 . 26.2 features ? in-system programming: in-system programming (isp) is programming or reprogramming the on-chip flash memory, using the bootloader software and uart serial port or the c_can interface. this can be done when the part resides in the end-user board. ? in-application programming: in-application (iap) programming is performing erase and write operation on the on-chip flash memory, as directed by the end-user application code. ? flash access times can be configured through a register in the flash controller block. ? erase time for one sector is 100 ms 5%. programming time for one block of 256 bytes is 1 ms 5%. 26.3 general description 26.3.1 bootloader the bootloader controls initial operation after reset and also provides the means to accomplish programming of the flash memory vi a uart or c_can. this could be initial programming of a blank device, erasure and re-programming of a previously programmed device, or programming of the flash memory by the application program in a running system. lpc1114fhn33/301 32 kb table 370 no yes no lpc1114fhn33/302 32 kb table 370 no yes no lpc1114fhn33/303 32 kb table 371 yes yes no lpc1114fhn33/333 56 kb table 371 yes yes no lpc1114fhi33/302 32 kb table 370 no yes no lpc1114fhi33/303 32 kb table 371 yes yes no lpc1114fbd48/301 32 kb table 370 no yes no lpc1114fbd48/302 32 kb table 370 no yes no lpc1114fbd48/303 32 kb table 371 yes yes no lpc1114fbd48/323 48 kb table 371 yes yes no lpc1114fbd48/333 56 kb table 371 yes yes no lpc1115fbd48/303 64 kb table 371 yes yes no lpc11d14 32 kb table 370 no yes no lpc11c12/c22 16 kb table 370 no yes yes lpc11c14/c24 32 kb table 370 no yes yes table 369. lpc111x/lpc11cx flash configurations type number flash configuration page erase iap command supported isp via uart isp via c_can
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 412 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware the bootloader code is executed every time th e part is powered on or reset. the loader can execute the isp command handler or the user application code. a low level after reset at the pio0_1 pin is considered as an external hardware request to start the isp command handler either via uart or c_can, if present. remark: sram location 0x1000 0000 to 0x1000 0050 is not used by the bootloader and the memory content in this ar ea is retained during reset. sram memory is not retained when the part powers down or enters deep power-down mode. if the c_can interface is present (lpc11cx parts), the state of pin pio0_3 at reset together with a low level on pin pio0_1 determines whether uart isp or c_can isp routines are called: ? if pio0_3 is low, the bootloader configures the c_can interface and calls the c_can isp command handler. ? pio0_3 is high, the bootloader configures the uart serial port and calls the uart isp command handler (this is the default). remark: on parts without c_can interface, the state of pin pio0_3 does not matter. assuming that power supply pins are on th eir nominal levels when the rising edge on reset pin is generated, it may take up to 3 ms before pio0_1 is sampled and the decision whether to continue with user code or isp handler is made. if pio0_1 is sampled low and the watchdog overflow flag is set, the external hardware request to start the isp command handler is ignored. if there is no request for the isp command handler execution (pio0_1 is sampled high after reset), a search is made for a valid user program. if a valid user program is found then the execution control is transferred to it. if a valid user program is not found, the auto-baud routine is invoked. remark: the sampling of pin pio0_1 can be disabled through programming flash location 0x0000 02fc (see section 26.3.8.1 ). 26.3.2 memory map after any reset the boot block is 16 kb in size. the boot block is located in the memory region starting from the address 0x1fff 0000. the bootloader is designed to run from this memory area, but both the isp and iap software use part s of the on-chip ram. the ram usage is described later in this chapte r. the interrupt vectors residing in the boot block of the on-chip flash memory also become active af ter reset, i.e., the bo ttom 512 bytes of the boot block are also visible in the memory region starting from the address 0x0000 0000. 26.3.3 criterion for valid user code criterion for valid user code: the reserved cortex-m0 exception vector location 7 (offset 0x 0000 001c in the vector table) should co ntain the 2s complement of the check-sum of table entries 0 through 6. this causes the checksum of the first 8 table entries to be 0. the bootloader code checksums the first 8 locations in sector 0 of the flash. if the result is 0, then execution control is transferred to the user code. if the signature is not valid, the auto-baud routin e synchronizes with the host via serial port 0. the host should send a ? (0x3f) as a synchronization character and wait for a response. the host side serial port settings should be 8 data bits, 1 stop bit and no parity. the auto-baud routine measures the bit time of the received synchronization character in terms of its own frequency and programs the baud rate generator of the serial port. it also
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 413 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware sends an ascii string ("synchronized") to the host. in response to this host should send the same string ("synchronized< cr>"). the auto-baud routine looks at the received characters to ve rify synchronization. if synchr onization is verified then "ok" string is sent to the host. the host should re spond by sending the crystal frequency (in khz) at which the part is running. for example, if the part is running at 10 mhz, the response from the host should be "10000". "ok" string is sent to the host after receivin g the crystal frequency. if synchronization is not verified then the auto-baud routine waits again for a synchronization character. for auto-baud to work correctly in case of user invoked isp, the cclk frequency should be greater than or equal to 10 mhz. once the crystal frequency is received the part is initialized and the isp command handler is invoked. for safety reasons an "unlock" command is required before executing the commands resulting in flash erase/write operations and the "go" command. the rest of the commands can be executed without the unlock command. the unlock command is required to be executed once per isp session. the unlock command is explained in section 26.5 uart isp commands on page 420 .
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 414 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware 26.3.4 boot process flowchart (1) for details on handling the crystal frequency, see section 26.7.8 reinvoke isp (iap) on page 440 fig 91. boot process flowchart reset initialize receive crystal frequency run uart isp command handler run c_can isp command handler run auto-baud crp1/2/3 enabled? watchdog flag set? crp3/no_isp enabled? enter isp mode? (pio0_1 = low) c_can boot? (pio0_3 = low) user code valid? user code valid? auto-baud successful? execute internal user code initialize c_can enable debug yes yes yes yes yes yes yes yes no no no no no no no no a a boot from uart boot from c_can
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 415 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware 26.3.5 flash configuration for lp c1100, lpc1100c, lpc1100l series some iap and isp commands operate on se ctors and specify se ctor numbers. the following table shows the correspondence between sector numbers and memory addresses for lpc111x/lpc11cxx devices. 26.3.6 flash configuratio n for lpc1100xl series some iap and isp commands operate on se ctors and specify se ctor numbers. in addition, parts in the lpc1100xl series support a page erase command. the following table shows the correspondence between page numbers, sector numbers, and memory addresses for lpc1 100xl devices. the size of a sector is 4 kb, the size of a page is 256 byte. one sector contains 16 pages. table 370. lpc111x flash configuratio n (lpc1100, lpc1100l, lpc1100c series) sector number sector size [kb] address range lpc1110 (4 kb flash) LPC1111 (8 kb flash) lpc1112/ lpc11c12/l pc11c22 (16 kb flash) lpc1113 (24 kb flash) lpc1114/ lpc11c14/l pc11c24 (32 kb flash) 0 4 0x0000 0000 - 0x0000 0fff yes yes yes yes yes 1 4 0x0000 1000 - 0x0000 1fff - yes yes yes yes 2 4 0x0000 2000 - 0x0000 2fff - - yes yes yes 3 4 0x0000 3000 - 0x0000 3fff - - yes yes yes 4 4 0x0000 4000 - 0x0000 4fff - - - yes yes 5 4 0x0000 5000 - 0x0000 5fff - - - yes yes 6 4 0x0000 6000 - 0x0000 6fff - - - - yes 7 4 0x0000 7000 - 0x0000 7fff - - yes table 371. lpc1100xl flash configuration sector number sector size [kb] page number address range LPC1111 (8 kb flash) lpc1112 (16 kb flash) lpc1113 (24 kb flash) lpc1114/203/303 (32 kb flash) lpc1114/323 (48 kb flash) lpc1114/333 (56 kb flash) lpc1115 (64 kb flash) 0 4 0 -15 0x0000 0000 - 0x0000 0fff yes yes yes yes yes yes yes 1 4 16 - 31 0x0000 1000 - 0x0000 1fff yes yes yes yes yes yes yes 2 4 32 - 47 0x0000 2000 - 0x0000 2fff - yes yes yes yes yes yes 3 4 48 - 63 0x0000 3000 - 0x0000 3fff - yes yes yes yes yes yes 4 4 64 - 79 0x0000 4000 - 0x0000 4fff - - yes yes yes yes yes 5 4 80 - 95 0x0000 5000 - 0x0000 5fff - - yes yes yes yes yes 6 4 96 - 111 0x0000 6000 - 0x0000 6fff - - - yes yes yes yes 7 4 112 - 127 0x0000 7000 - 0x0000 7fff - - - yes yes yes yes 8 4 128 - 143 0x0000 8000 - 0x0000 8fff - - - - yes yes yes 9 4 144 - 159 0x0000 9000 - 0x0000 9fff - - - - yes yes yes 10 4 160 - 175 0x0000 a000 - 0x0000 afff - - - - yes yes yes 11 4 176 - 191 0x0000 b000 - 0x0000 bfff - - - - yes yes yes 12 4 192 - 207 0x0000 c000 - 0x0000 cfff - - - - - yes yes
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 416 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware 26.3.7 flash content protection mechanism the lpc111x/lpc11c1x is equipped with the error correction code (ecc) capable flash memory. the purpose of an error correction modu le is twofold. firstly, it decodes data words read from the memory into output data words. secondly, it encodes data words to be written to the memory. the error correction capability consists of single bit error correction with hamming code. the operation of ecc is transparent to the ru nning application. the e cc content itself is stored in a flash memory not accessible by users code to either read from it or write into it on its own. a byte of ecc corresponds to every consecutive 128 bits of the user accessible flash. consequently, flash byte s from 0x0000 0000 to 0x0000 000f are protected by the first ecc byte, flash bytes from 0x0000 0010 to 0x0000 001f are protected by the second ecc byte, etc. whenever the cpu requests a read from us ers flash, both 128 bits of raw data containing the specified memory location and the matching ecc byte are evaluated. if the ecc mechanism detects a single error in t he fetched data, a correction will be applied before data are provided to the cpu. when a write request into the users flash is made, write of user specified content is accompan ied by a matching ecc value calculated and stored in the ecc memory. when a sector of flash memory is erased, the corresponding ecc bytes are also erased. once an ecc byte is written, it can not be updated unless it is erased first. therefore, for the implemented ecc mechanism to perform properly, data must be written into the flash memory in groups of 16 bytes (or multiples of 16), aligned as described above. 26.3.8 code read protection (crp) code read protection is a mechanism that allo ws the user to enable different levels of security in the system so that access to the on-chip flash and use of the isp can be restricted. when needed, crp is invoked by programming a specific pattern in flash location at 0x0000 02fc. iap commands are not affected by the code read protection. important: any crp change becomes effective only after the device has gone through a power cycle. 13 4 208 - 223 0x0000 d000 - 0x0000 dfff - - - - - yes yes 144224 - 2390x0000 e000 - 0x0000 efff- - ----yes 15 4 240 - 255 0x0000 f000 - 0x0000 ffff - - - ---yes table 371. lpc1100xl flash configuration sector number sector size [kb] page number address range LPC1111 (8 kb flash) lpc1112 (16 kb flash) lpc1113 (24 kb flash) lpc1114/203/303 (32 kb flash) lpc1114/323 (48 kb flash) lpc1114/333 (56 kb flash) lpc1115 (64 kb flash)
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 417 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware table 372. code read protection options name pattern programmed in 0x0000 02fc description no_isp 0x4e69 7370 prevents sampling of pin pio0_1 for entering isp mode. pio0_1 is available for other uses. crp1 0x12345678 access to chip via the swd pins is disabled. this mode allows partial flash update using the following i sp commands and restrictions: ? write to ram command should not access ram below 0x1000 0300. access to addresses below 0x1000 0200 is disabled. ? copy ram to flash command can not write to sector 0. ? erase command can erase sector 0 only when all sectors are selected for erase. ? compare command is disabled. ? read memory command is disabled. this mode is useful when crp is re quired and flash field updates are needed but all sectors can not be erased. since compare command is disabled in case of partial up dates the secondary loader should implement checksum mechanism to verify the integrity of the flash. crp2 0x87654321 access to chip via the swd pins is disabled. the following isp commands are disabled: ? read memory ? write to ram ? go ? copy ram to flash ? compare when crp2 is enabled the isp erase command only allows erasure of all user sectors. crp3 0x43218765 access to chip via the swd pins is disabled. isp entry by pulling pio0_1 low is disabled if a valid us er code is present in flash sector 0. this mode effectively disables isp override using pio0_1 pin. it is up to the users application to prov ide a flash update mechanism using iap calls or call reinvoke isp command to enable flash update via uart. caution: if crp3 is selected, no future factory testing can be performed on the device. table 373. code read protection hardware/software interaction crp option user code valid pio0_1 pin at reset swd enabled lpc111x/ lpc11cxx enters isp mode partial flash update in isp mode none no x yes yes yes none yes high yes no na none yes low yes yes yes crp1 yes high no no na crp1 yes low no yes yes crp2 yes high no no na
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 418 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware in case a crp mode is enabled and access to the chip is allowed via the isp, an unsupported or restrict ed isp command will be te rminated with return code code_read_protection_enabled. 26.3.8.1 isp entry protection in addition to the three crp modes, the user can prevent the sampling of pin pio0_1 for entering isp mode and thereby release pin pio0_1 for other uses. this is called the no_isp mode. the no_isp mode can be entered by programming the pattern 0x4e69 7370 at location 0x0000 02fc. crp2 yes low no yes no c r p 3y e sx n on on a crp1 no x no yes yes crp2 no x no yes no crp3 no x no yes no table 374. isp commands allowed for different crp levels isp command crp1 crp2 crp3 (no entry in isp mode allowed) unlock yes yes n/a set baud rate yes yes n/a echo yes yes n/a write to ram yes; above 0x1000 0300 only no n/a read memory no no n/a prepare sector(s) for write operation yes yes n/a copy ram to flash yes; not to sector 0 no n/a go no no n/a erase sector(s) yes; sector 0 can only be erased when all sectors are erased. yes; all sectors only n/a blank check sector(s) no no n/a read part id yes yes n/a read boot code version yes yes n/a compare no no n/a readuid yes yes n/a table 373. code read protection hardware/software interaction crp option user code valid pio0_1 pin at reset swd enabled lpc111x/ lpc11cxx enters isp mode partial flash update in isp mode
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 419 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware 26.4 uart communication protocol all uart isp commands should be sent as single ascii strings. strings should be terminated with carriage return (cr) and/or line feed (lf) control characters. extra and characters are ignored. all isp responses are sent as terminated ascii strings. data is sent and received in uu-encoded format. 26.4.1 uart isp command format "command parameter_0 parameter_1 ... parameter_n" "data" (data only for write commands). 26.4.2 uart isp response format "return_coderesponse_0response_1 ... response_n" "data" (data only for read commands). 26.4.3 uart isp data format the data stream is in uu-encoded format. the uu-encode algorithm converts 3 bytes of binary data in to 4 bytes of printable ascii ch aracter set. it is more efficient than hex format which converts 1 byte of binary data in to 2 bytes of ascii hex. the sender should send the check-sum after transmitting 20 uu-encoded lines. the length of any uu-encoded line should not exceed 61 characters (bytes) i.e. it can hold 45 data bytes. the receiver should compare it with the check-sum of the received bytes. if the check-sum matches then the receiver should respond with "ok" to continue further transmission. if the check-sum does not match the receiver should respond with "resend". in response the se nder should retransmit the bytes. 26.4.4 uart isp flow control a software xon/xo ff flow control scheme is used to prevent data loss due to buffer overrun. when the data arrives rapidly, the ascii control character dc3 (stop) is sent to stop the flow of data. data flow is resume d by sending the ascii control character dc1 (start). the host should also support the same flow control scheme. 26.4.5 uart isp command abort commands can be aborted by sending the ascii co ntrol character "esc". this feature is not documented as a command under "isp comm ands" section. once the escape code is received the isp command handler waits for a new command. 26.4.6 interrupts during uart isp the boot block interrupt vectors located in the boot block of the flash are active after any reset.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 420 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware 26.4.7 interrupts during iap the on-chip flash memory is not accessible du ring erase/write operations. when the user application code starts executing the interrupt vectors from the user flash area are active. before making any iap call, either disable the interrupts or ensure that the user interrupt vectors are active in ram and that the inte rrupt handlers reside in ram. the iap code does not use or disable interrupts. 26.4.8 ram used by isp comman d handler (for lpc11cxx parts) isp commands use on-chip ram from 0x1000 017c to 0x1000 025b. the user could use this area, but the contents may be lost up on reset. flash programming commands use the top 32 bytes of on-chip ram. the stack is located at (ram top ? 32). the maximum stack usage is 256 bytes and it grows downwards. 26.4.9 ram used by isp comman d handler (for lpc111x parts) isp commands use on-chip ram from 0x1000 0050 to 0x1000 017f. the user could use this area, but the contents may be lost up on reset. flash programming commands use the top 32 bytes of on-chip ram. the stack is located at (ram top ? 32). the maximum stack usage is 256 bytes and it grows downwards. 26.4.10 ram used by iap command handler flash programming commands use the top 32 bytes of on-chip ram. the maximum stack usage in the user allocated stack space is 128 bytes and it grows downwards. 26.5 uart isp commands the following commands are accepted by the isp command handler. detailed status codes are supported for each command. the command handler sends the return code invalid_command when an undefined command is received. commands and return codes are in ascii format. cmd_success is sent by isp command handl er only when receiv ed isp command has been completely executed and the new isp command can be given by the host. exceptions from this rule are "set baud rate ", "write to ram", "read memory", and "go" commands. table 375. uart isp command summary isp command usage described in unlock u table 376 set baud rate b table 377 echo a table 378 write to ram w table 379 read memory r

table 380 prepare sector(s) for write operation p table 381 copy ram to flash c table 382 go g

table 383 erase sector(s) e table 384
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 421 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware 26.5.1 unlock (uart isp) 26.5.2 set baud rate (uart isp) 26.5.3 echo (uart isp) blank check sector(s) i table 385 read part id j table 386 read boot code version k table 388 compare m table 389 readuid n table 390 table 375. uart isp command summary isp command usage described in table 376. uart isp unlock command command u input unlock code: 23130 10 return code cmd_success | invalid_code | param_error description this command is used to unlock flash write, erase, and go commands. example "u 23130" unlocks the flash write/erase & go commands. table 377. uart isp set baud rate command command b input baud rate: 9600 | 19200 | 38400 | 57600 | 115200 stop bit: 1 | 2 return code cmd_success | invalid_baud_rate | invalid_stop_bit | param_error description this command is used to change the baud rate. the new baud rate is effective after the command handler send s the cmd_success return code. example "b 57600 1" sets the serial port to baud rate 57600 bps and 1 stop bit. table 378. uart isp echo command command a input setting: on = 1 | off = 0 return code cmd_success | param_error description the default setting for echo comma nd is on. when on the isp command handler sends the received serial data back to the host. example "a 0" turns echo off.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 422 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware 26.5.4 write to ram (uart isp) the host should send t he data only after receiving th e cmd_success return code. the host should send the check-sum after transmitting 20 uu-encoded lines. the checksum is generated by adding raw data (before uu-encoding) bytes and is reset after transmitting 20 uu-encoded lines. the length of any uu-encoded line should not exceed 61 characters (bytes) i.e. it can hold 45 data bytes. when the data fits in less then 20 uu-encoded lines then the check-sum should be of the actual number of bytes sent. the isp command handler compares it with th e check-sum of the received bytes. if the check-sum matches, the isp command handler responds with "ok" to continue further transmission. if the check-sum does not match, the isp command handler responds with "resend< cr>". in response th e host should retransmit the bytes. 26.5.5 read memory

(uart isp) the data stream is followed by the command success return co de. the check-sum is sent after transmitting 20 uu-encoded lines. the checksum is generated by adding raw data (before uu-encoding) bytes and is reset after transmitting 20 uu-encoded lines. the length of any uu-encoded line should not exce ed 61 characters (bytes) i.e. it can hold 45 data bytes. when the data fits in less then 20 uu-encoded lines then the check-sum is of actual number of bytes sent. the host should compare it with the checksum of the received bytes. if the check-sum matches then the host should respond with "ok" to continue further transmissi on. if the check-sum does not match then the host should respond with "resend< cr>". in respon se the isp command handler sends the data again. table 379. uart isp write to ram command command w input start address: ram address where data bytes are to be written. this address should be a word boundary. number of bytes: number of bytes to be written. count should be a multiple of 4 return code cmd_success | addr_error (address not on word boundary) | addr_not_mapped | count_error (byte count is not multiple of 4) | param_error | code_read_protection_enabled description this command is used to download data to ram. data should be in uu-encoded format. this command is blocked when code read protection is enabled. example "w 268436224 4" writes 4 bytes of data to address 0x1000 0300.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 423 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware 26.5.6 prepare sector(s) for write ope ration (uart isp) this command makes flash write/erase operation a two step process. 26.5.7 copy ram to flash (uart isp) when writing to the flash, the following limitations apply: 1. the smallest amount of data that can be written to flash by the copy ram to flash command is 256 byte (equal to one page). 2. one page consists of 16 flash words (lines), and the smallest amount that can be modified per flash write is one flash word (one line). this limitation follows from the application of ecc to the flash write operation, see section 26.3.7 . 3. to avoid write disturbance (a mechanism intr insic to flash memories), an erase should be performed after following 16 consecutive writes inside the same page. note that the erase operation then erases the entire sector. table 380. uart isp read memory command command r input start address: address from where data bytes are to be read. this address should be a word boundary. number of bytes: number of bytes to be read. count should be a multiple of 4. return code cmd_success followed by | addr_error (address not on word boundary) | addr_not_mapped | count_error (byte count is not a multiple of 4) | param_error | code_read_protection_enabled description this command is used to read data from ram or flash memory. this command is blocked when code read protection is enabled. example "r 268435456 4" reads 4 bytes of data from address 0x1000 0000. table 381. uart isp prepare sector( s) for write operation command command p input start sector number end sector number: should be greater than or equal to start sector number. return code cmd_success | busy | invalid_sector | param_error description this command must be executed before executing "copy ram to flash" or "erase sector(s)" command. successful execution of the "copy ram to flash" or "erase sector(s)" command causes relevant sectors to be protected again. the boot block can not be prepared by this command. to prepare a single sector use the same "start" and "end" sector numbers. example "p 0 0" prepares the flash sector 0.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 424 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware remark: once a page has been written to 16 times, it is still possible to write to other pages within the same sector without performing a sector erase (assuming that those pages have been erased previously). 26.5.8 go

(uart isp) the go command is usually used after the flash image has been updated. after the update a reset is re quired. therefore, the go comma nd should point to the reset handler. since the device is still in isp mo de, the reset handler should do the following: ? re-initialize the sp pointer to the application default. ? set the sysmemremap to ei ther 0x01 or 0x02. while in isp mode, the sysmemremap is set to 0x00. alternatively, the following snippet can be loaded into the ram for execution: scb->aircr = 0x05fa0004; //issue system reset while(1); //should never come here this snippet will issue a system reset request to the core. table 382. uart isp copy ram to flash command command c input flash address (dst): destination flash address where data bytes are to be written. the destination address should be a 256 byte boundary. ram address (src): source ram address from where data bytes are to be read. number of bytes: number of bytes to be written. should be 256 | 512 | 1024 | 4096. remark: in parts with less than 4 kb sram, the number of bytes is limited to 1024 (see ta b l e 3 ). return code cmd_success | src_addr_error (address not on word boundary) | dst_addr_error (address not on correct boundary) | src_addr_not_mapped | dst_addr_not_mapped | count_error (byte count is not 256 | 512 | 1024 | 4096) | sector_not_prepared_for write_operation | busy | cmd_locked | param_error | code_read_protection_enabled description this command is used to program the flash memory. the "p repare sector(s) for write operation" command should preced e this command. the affected sectors are automatically protected again once the copy command is successfully executed. the boot block cannot be written by this command. this command is blocked when code read protection is enabled. example "c 0 268437504 512" copies 512 bytes from the ram address 0x1000 0800 to the flash address 0.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 425 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware the following isp commands will send the system reset code loaded into 0x1000 000. u 23130 w 268435456 16 0`4@"20%@_n<,[0#@!`#z!0`` 1462 g 268435456 t 26.5.9 erase sector(s) (uart isp) table 383. uart isp go command command g input address: flash or ram address from which the code execution is to be started. this address should be on a word boundary. mode: t (execute progra m in thumb mode). return code cmd_success | addr_error | addr_not_mapped | cmd_locked | param_error | code_read_protection_enabled description this command is used to execute a program residing in ram or flash memory. it may not be possible to return to the isp command handler once this command is successfully executed. this command is blocked when code read protection is enabled. the command must be used wit h an address of 0x0000 0200 or greater. example "g 512 t" branches to address 0x0000 0200 in thumb mode. table 384. uart isp erase sector command command e input start sector number end sector number: should be greater than or equal to start sector number. return code cmd_success | busy | invalid_sector | sector_not_prepared_for_write_operation | cmd_locked | param_error | code_read_protection_enabled description this command is used to erase one or more sector(s) of on-chip flash memory. the boot block can not be erased using this command. this command only allows erasure of all user sectors when t he code read protection is enabled. example "e 2 3" erases the flash sectors 2 and 3.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 426 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware 26.5.10 blank check sector(s) (uart isp) 26.5.11 read part identi fication number (uart isp) table 385. uart isp blank check sector command command i input start sector number: end sector number: should be greater than or equal to start sector number. return code cmd_success | sector_not_blank (followed by ) | invalid_sector | param_error description this command is used to blank check one or more sectors of on-chip flash memory. blank check on sector 0 always fails as first 64 bytes are re-mapped to flash boot block. when crp is enabled, the blank check command returns 0 for the offset and value of sectors which are not blank. blank sector s are correctly reported irrespective of the crp setting. example "i 2 3" blank c hecks the flash sectors 2 and 3. table 386. uart isp read pa rt identification command command j input none. return code cmd_succ ess followed by part identification number in ascii (see table 387 ). description this command is used to read the part identification number. table 387. lpc111x and lpc11cxx part identification numbers device hex coding lpc111x lpc1110fd20 0x0a07 102b; 0x1a07 102b LPC1111fdh20/002 0x0a16 d02b; 0x1a16 d02b LPC1111fhn33/101 0x041e 502b; 0x2516 d02b LPC1111fhn33/102 0x2516 d02b LPC1111fhn33/201 0x0416 502b; 0x2 516 902b LPC1111fhn33/202 0x2516 902b LPC1111fhn33/103 0x0001 0013 LPC1111fhn33/203 0x0001 0012 lpc1112fd20/102 0x0a24 902b; 0x1a24 902b lpc1112fdh20/102 0x0a24 902b; 0x1a24 902b lpc1112fdh28/102 0x0a24 902b; 0x1a24 902b lpc1112fhn33/101 0x042d 502b; 0x2524 d02b lpc1112fhn33/102 0x2524 d02b lpc1112fhn33/201 0x0425 502b; 0x2524 902b lpc1112fhn33/202 0x2524 902b
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 427 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware lpc1112fhn24/202 0x2524 902b lpc1112fhi33/202 0x2524 902b lpc1112fhn33/103 0x0002 0023 lpc1112fhn33/203 0x0002 0022 lpc1112fhi33/203 0x0002 0022 lpc1113fhn33/201 0x0434 502b; 0x2532 902b lpc1113fhn33/202 0x2532 902b lpc1113fhn33/301 0x0434 102b; 0x2532 102b lpc1113fhn33/302 0x2532 102b lpc1113fbd48/301 0x0434 102b; 0x2532 102b lpc1113fbd48/302 0x2532 102b lpc1113fbd48/303 0x0003 0030 lpc1113fhn33/203 0x0003 0032 lpc1113fhn33/303 0x0003 0030 lpc1114fdh28/102 0x0a40 902b; 0x1a40 902b lpc1114fn28/102 0x0a40 902b; 0x1a40 902b lpc1114fhn33/201 0x0444 502b; 0x2540 902b lpc1114fhn33/202 0x2540 902b lpc1114fhn33/301 0x0444 102b; 0x2540 102b lpc1114fhn33/302 0x2540 102b lpc1114fhi33/302 0x2540 102b lpc1114fbd48/301 0x0444 102b; 0x2540 102b lpc1114fbd48/302 0x2540 102b lpc1114fbd48/303 0x0004 0040 lpc1114fhn33/203 0x0004 0042 lpc1114fhn33/303 0x0004 0040 lpc1114fbd48/323 0x0004 0060 lpc1114fbd48/333 0x0004 0070 lpc1114fhn33/333 0x0004 0070 lpc1114fhi33/303 0x0004 0040 lpc11d14fbd100/302 0x2540 102b lpc1115fbd48/303 0x0005 0080 lpc11cxx lpc11c12fbd48/301 0x1421 102b lpc11c14fbd48/301 0x1440 102b lpc11c22fbd48/301 0x1431 102b lpc11c24fbd48/301 0x1430 102b table 387. lpc111x and lpc11cxx part identification numbers device hex coding
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 428 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware 26.5.12 read boot code version number (uart isp) 26.5.13 compare (uart isp) 26.5.14 readuid (uart isp) table 388. uart isp read boot code version number command command k input none return code cmd_success fo llowed by 2 bytes of boot code version number in ascii format. it is to be interpreted as .. description this command is used to read the boot code version number. table 389. uart isp compare command command m input address1 (dst): starting flash or ram address of data bytes to be compared. this address should be a word boundary. address2 (src): starting flash or ram address of data bytes to be compared. this address should be a word boundary. number of bytes: number of bytes to be compared; should be a multiple of 4. return code cmd_success | (source and destination data are equal) compare_error | (followed by the offset of first mismatch) count_error (byte count is not a multiple of 4) | addr_error | addr_not_mapped | param_error description this command is used to compare the memory contents at two locations. compare result may not be correct when source or destination address contains any of the first 512 bytes starting from address zero. first 512 bytes are re-mapped to boot rom example "m 8192 268468224 4" comp ares 4 bytes from the ram address 0x1000 8000 to the 4 bytes from the flash address 0x2000. table 390. uart isp readuid command command n input none return code cmd_success fo llowed by four 32-bit words of e-sort test information in ascii format. the word sent at the lowest address is sent first. description this command is used to read the unique id.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 429 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware 26.5.15 uart isp return codes 26.6 c_can communication protocol remark: the c_can interface is available on lpc11cxx parts only. the c_can bootloader is activated by the ro m reset handler automatically if pio0_3 is low on reset and the isp entry enabled (pio0_1 low). the c_can bootloader initializes the on-chip oscillator and the can co ntroller for a can bit rate of 100 kbit/s and sets its own canopen node id to a fixed va lue. the bootloader then waits for canopen sdo commands and responds to them. these commands allow to read and write table 391. uart isp return codes summary return code mnemonic description 0 cmd_success command is executed successfully. sent by isp handler only when command given by the host has been completely and successfully executed. 1 invalid_command invalid command. 2 src_addr_error source address is not on word boundary. 3 dst_addr_error destination addres s is not on a correct boundary. 4 src_addr_not_mapped source address is not mapped in the memory map. count value is taken in to consideration where applicable. 5 dst_addr_not_mapped destination addres s is not mapped in the memory map. count value is tak en in to consideration where applicable. 6 count_error byte count is not multiple of 4 or is not a permitted value. 7 invalid_sector sector number is invalid or end sector number is greater than start sector number. 8 sector_not_blank sector is not blank. 9 sector_not_prepared_for_ write_operation command to prepare sector for write operation was not executed. 10 compare_error source and destination data not equal. 11 busy flash programming hardware interface is busy. 12 param_error insufficient number of parameters or invalid parameter. 13 addr_error address is not on word boundary. 14 addr_not_mapped address is not mapped in the memory map. count value is taken in to consideration where applicable. 15 cmd_locked command is locked. 16 invalid_code unlock code is invalid. 17 invalid_baud_rate invalid baud rate setting. 18 invalid_stop_bit invalid stop bit setting. 19 code_read_protection_ enabled code read protection enabled.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 430 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware anything in a so-called object dictionary (od). the od contains entries that are addressed via a 16-bit index and 8-bit subindex. the command interface is part of this od. the c_can isp command handler allows to perform all functions that are otherwise available via the uart isp commands, see table 392 . the sdo commands are received, processed and responded to forever until the command to jump to a certain execution address (go) has been received or the chip is reset. the c_can isp handler occupies the fixed canopen node id 125 (0x7d). 26.6.1 c_can isp sdo communication the can isp node listens for can 2.0a (11- bit) messages with the identifier of 0x600 plus the node id 0x7d equaling to 0x67d. the node sends sdo responses with the identifier 0x580 plus node id equaling to 0x5fd. the sdo communication protocols expedited and segmented are supported. th is means that communication is always confirmed: each request can message will be followed by a response message from the isp node. the sdo block transfer mode is not supported. for details regarding the sdo protocol, see the cia 301 specification . table 392. c_can isp and uart isp command summary isp command c_can usage uart usage unlock section 26.6.3 table 376 set baud rate n/a table 377 echo n/a table 378 write to ram section 26.6.4 table 379 read memory section 26.6.5 table 380 prepare sector(s) for write operation section 26.6.6 table 381 copy ram to flash section 26.6.7 table 382 go section 26.6.8 table 383 erase sector(s) section 26.6.9 table 384 blank check sector(s) section 26.6.10 table 385 read part id section 26.6.11 table 386 read boot code version section 26.6.12 table 388 readuid section 26.6.13 table 390 compare section 26.6.14 table 389
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 431 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware 26.6.2 c_can isp object directory table 393. c_can isp object directory index subindex data type access description 0x1000 00 unsigned32 ro device type (ascii lpc1) 0x1001 00 - ro error register (not used, 0x00) 0x1018 00 - identity object 01 unsigned32 ro vendor id (not used, 0x0000 0000) 02 unsigned32 ro part identification number 03 unsigned32 ro boot code version number 0x1f50 00 - program data 01 domain rw program area 0x1f51 00 - program control 01 unsigned8 rw program control 0x5000 00 unsigned16 wo unlock code 0x5010 00 unsigned32 rw memory read address 0x5011 00 unsigned32 rw memory read length 0x5015 00 unsigned32 rw ram write address 0x5020 00 unsigned16 wo prepare sectors for write 0x5030 00 unsigned16 wo erase sectors 0x5040 00 - blank check sectors 01 unsigned16 wo check sectors 02 unsigned32 ro offset of the first non-blank location 0x5050 00 - copy ram to flash 01 unsigned32 rw flash address (dst) 02 unsigned32 rw ram address (src) 03 unsigned16 rw number of bytes 0x5060 00 - compare memory 01 unsigned32 rw address 1 02 unsigned32 rw address 2 03 unsigned16 rw number of bytes 04 unsigned32 ro offset of the first mismatch 0x5070 00 - execution address 01 unsigned32 rw execution address 02 unsigned8 ro mode (t or a), only t supported 0x5100 00 - serial number 01 unsigned32 ro serial number 1 02 unsigned32 ro serial number 2 03 unsigned32 ro serial number 3 04 unsigned32 ro serial number 4
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 432 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware 26.6.3 unlock (c_can isp) write to [0x5000, 0]. writing an invalid unlock code will return a dedicated abort code. 26.6.4 write to ram (c_can isp) set ram write address by writing to [0x5015, 0]. then write the binary data to [0x1f50, 1]. since this is a domain entry, the data can be continuously written. the host terminates the write. the write address in [0x5015, 0] au to-increments, so a write of a larger area may be done in multiple successive write cycles to [0x1f50, 1]. 26.6.5 read memory (c_can isp) set ram read address by writing to [0x5010, 0] and the read length by writing to [0x5011,0]. then read the binary data from [0x1f50,1]. since this is a domain entry, the data is continuously read. the device terminat es the read when the number of bytes in the read length entry has been read. the read address in [0x5010, 0] auto-increments, so a read of a larger area may be done in multiple successive read cycles from [0x1f50,1]. 26.6.6 prepare sectors for write operation (c_can isp) write a 16-bit value to [0x5020, 0] with the start sector number in the lower eight bits and the end sector number in the upper eight bits. 26.6.7 copy ram to flash (c_can isp) write the parameters in to entry [0x5050, 1 to 3]. the writ e of the number of bytes into [0x5050,3] starts the programming. see section 26.5.4 for limitations on the write-to-flash process. 26.6.8 go (c_can isp) write the start address into [0x5070, 0]. then trigger the start application command by writing the value 0x1 to [0x1f51, 1]. 26.6.9 erase sectors (c_can isp) write a 16-bit value to [0x5030, 0] with the start sector number in the lower eight bits and the end sector number in the upper eight bits. 26.6.10 blank check sectors (c_can isp) write a 16-bit value to [0x5040, 1] with the start sector number in the lower eight bits and the end sector number in the upper eight bits. if the sector_not_blank abort code is retu rned, the entry [0x5040, 2] contains the offset of the first non-blank location. 26.6.11 read partid (c_can isp) read [0x1018, 2]. see table 387 .
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 433 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware 26.6.12 read boot code version (c_can isp) read [0x1018, 3] 26.6.13 read serial number (c_can isp) read [0x5100, 1 to 4] 26.6.14 compare (c_can isp) write the parameters into entry [0x5060, 1 to 3]. the write of the number of bytes into[0x5060, 3] starts the comparison. if the compare_error abort code is returned, the entry [0x5060, 4] can be read to get the offset of the first mismatch. 26.6.15 c_can isp sdo abort codes the od entries that trigger an action return an appropriate sdo abort code when the action returned an error. the abort code is 0x0f00 0000 plus the value of the corresponding isp return code in the lowest byte. table 394 shoes the list of abort codes. in addition, the regular canopen sdo abort co des for invalid access to od entries are also supported. table 394. c_can isp sdo abort codes uart isp error code sdo abort code value addr_error sdoabort_ad dr_error 0x0f00 000d addr_not_mapped sdoabort_ad dr_ not_mapped 0x0f00 000e cmd_locked sdoabort_cmd_locked 0x0f00 000f code_read_protection_ enabled sdoabort_code_read _protection_enabled 0x0f00 0013 compare_error sdoabort_c ompare_error 0x0f00 000a count_error sdoabort_co unt_error 0x0f00 0006 dst_addr_error sdoabort_dst_addr_error 0x0f00 0003 dst_addr_not_mapped sdoabort_dst_addr_ not_mapped 0x0f00 0005 invalid_code sdoabort_invalid_code 0x0f00 0010 invalid_command sdoabort_invalid_command 0x0f00 0001 invalid_sector sdoabort_invalid_sector 0x0f00 0007 param_error sdoabort_param_error 0x0f00 000c sector_not_blank sdoabort_sec tor_ not_blank 0x0f00 0008 sector_not_prepared_ for_write_operation sdoabort_sector_not_ prepared_for_write_ operation 0x0f00 0009 src_addr_error sdoabort_src_addr_error 0x0f00 0002 src_addr_not_mapped sdoabort_src_addr_ not_mapped 0x0f00 0004
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 434 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware 26.6.16 differences to fully-compliant canopen while the bootloader uses the sdo communica tion protocol and the object dictionary data organization method, it is not a fully cia 301 standard compliant canopen node.the following features are not available or different to the standard: ? network management (nmt) message processing not available. ? heartbeat message and entry 0x1017 not available. ? uses proprietary sdo abort codes to indicate device errors. ? to speed up communication, empty sdo responses during sdo segmented download/write to the node are shortened to one data byte, rather than full eight data bytes as the standard describes. ? entry [0x1018, 1] vendor id reads 0x0000 0000 rather than an official cia-assigned unique vendor id. ? the host must use a different met hod to identify the can isp devices. 26.7 iap commands for in application programming the iap routine should be called with a word pointer in register r0 pointing to memory (ram) containing command code and parameters. result of the iap command is returned in the result table pointed to by register r1. the user can reuse the command table for result by passing the same pointer in registers r0 and r1. the parameter table should be big enough to hold all the results in case the number of results are more than number of parameters. parameter passing is illustrated in the figure 92 . the number of parameters and results vary according to the iap command. the maximum number of parameters is 5, passed to the "copy ram to flash" command. the maximum number of results is 4, returned by the "readuid" command. the command handler sends the status code invalid_command when an undefined command is received. the iap routine reside s at 0x1fff 1ff0 location and it is thumb code. call the iap function in the following way: define the iap location entry point. since the 0t h bit of the iap location is set there will be a change to thumb instruction set when the program counter branches to this address. #define iap_location 0x1fff1ff1 define data structure or pointers to pass i ap command table and result table to the iap function: unsigned int command_param[5]; unsigned int status_result[4]; or unsigned int * command_param; unsigned int * status_result; command_param = (unsigned int *) 0x... status_result =(unsigned int *) 0x...
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 435 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware define pointer to function type, which takes tw o parameters and return s void. note the iap returns the result with the base address of the table residing in r1. typedef void (*iap)(unsigned int [],unsigned int[]); iap iap_entry; setting the function pointer: iap_entry=(iap) iap_location; to call the iap, use the following statement. iap_entry (command_param,status_result); up to 4 parameters can be pass ed in the r0, r1, r2 and r3 re gisters respectively (see the arm thumb procedure call standard sws espc 0002 a-05). additional parameters are passed on the stack. up to 4 parameters can be returned in the r0, r1, r2 and r3 registers respectively. additional parame ters are returned indirectly via memory. some of the iap calls require more than 4 parameters. if the arm suggested scheme is used for the parameter passing/returning then it might create problems due to difference in the c compiler implementation from different vendors. the suggested parameter passing scheme reduces such risk. the flash memory is not accessible during a write or erase operation. iap commands, which results in a flash write/erase operation, use 32 bytes of space in the top portion of the on-chip ram for execution. the user program should not be use this space if iap flash programming is permitted in the application. table 395. iap command summary iap command command code described in prepare sector(s) for write operation 50 (decimal) table 396 copy ram to flash 51 (decimal) table 397 erase sector(s) 52 (decimal) table 398 blank check sector(s) 53 (decimal) table 399 read part id 54 (decimal) table 400 read boot code version 55 (decimal) table 401 compare 56 (decimal) table 402 reinvoke isp 57 (decimal) table 403 read uid 58 (decimal) table 404 erase page 59 (decimal) table 405
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 436 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware 26.7.1 prepare sector(s) for write operation (iap) this command makes flash write/erase operation a two step process. 26.7.2 copy ram to flash (iap) see section 26.5.4 for limitations on the write-to-flash process. fig 92. iap parameter passing command code param 0 param 1 param n status_result[0] status_result[1] status code result 0 result 1 result n command parameter array status result array arm register r0 arm register r1 command_param[0] command_param[1] command_param[2] command_param[n] status_result[2] status_result[n] table 396. iap prepare sector(s) for write operation command command prepare sector(s) for write operation input command code: 50 (decimal) param0: start sector number param1: end sector number (should be greater than or equal to start sector number). status code cmd_success | busy | invalid_sector result none description this command must be executed before executing "copy ram to flash" or "erase sector(s)" command. successful execution of the "copy ram to flash" or "erase sector(s)" command causes relevant sectors to be protected again. the boot sector can not be prepared by this command. to prepare a single sector use the same "start" and "end" sector numbers.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 437 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware 26.7.3 erase sector(s) (iap) table 397. iap copy ram to flash command command copy ram to flash input command code: 51 (decimal) param0(dst): destination flash address where da ta bytes are to be written. this address should be a 256 byte boundary. param1(src): source ram address from which data bytes are to be read. this address should be a word boundary. param2: number of bytes to be written. should be 256 | 512 | 1024 | 4096. param3: system clock frequency (cclk) in khz. remark: in parts with less than 4 kb sram, param2 is limited to 1024 (see ta b l e 3 ). status code cmd_success | src_addr_error (address not a word boundary) | dst_addr_error (address not on correct boundary) | src_addr_not_mapped | dst_addr_not_mapped | count_error (byte count is not 256 | 512 | 1024 | 4096) | sector_not_prepared_for_write_operation | busy result none description this command is used to program the flash memory. the affected sectors should be prepared first by calling "prepare sect or for write operation" command. the affected sectors are automatically prot ected again once the copy command is successfully executed. the boot sector can not be written by this command. table 398. iap erase sector(s) command command erase sector(s) input command code: 52 (decimal) param0: start sector number param1: end sector number (should be greater than or equal to start sector number). param2: system clock frequency (cclk) in khz. status code cmd_success | busy | sector_not_prepared_for_write_operation | invalid_sector result none description this command is used to erase a se ctor or multiple sectors of on-chip flash memory. the boot sector can not be erased by this command. to erase a single sector use the same "start" and "end" sector numbers.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 438 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware 26.7.4 blank check sector(s) (iap) 26.7.5 read part identification number (iap) 26.7.6 read boot code version number (iap) table 399. iap blank check sector(s) command command blank check sector(s) input command code: 53 (decimal) param0: start sector number param1: end sector number (should be greater than or equal to start sector number). status code cmd_success | busy | sector_not_blank | invalid_sector result result0: offset of the first non blank word location if the status code is sector_not_blank. result1: contents of non blank word location. description this command is used to blank check a sector or multiple sectors of on-chip flash memory. to blank check a single sector use the same "start" and "end" sector numbers. table 400. iap read part identification command command read part identification number input command code: 54 (decimal) parameters: none status code cmd_success | result result0: part identification number. description this command is used to read the part identification number. table 401. iap read boot code version number command command read boot code version number input command code: 55 (decimal) parameters: none status code cmd_success | result result0: 2 bytes of boot code version number. read as .< byte0(minor)> description this command is used to read the boot code version number.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 439 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware 26.7.7 compare (iap) table 402. iap compare command command compare input command code: 56 (decimal) param0(dst): starting flash or ram address of data bytes to be compared. this address should be a word boundary. param1(src): starting flash or ram address of data bytes to be compared. this address should be a word boundary. param2: number of bytes to be compar ed; should be a multiple of 4. status code cmd_success | compare_error | count_error (byte count is not a multiple of 4) | addr_error | addr_not_mapped result result0: offset of the first mismatch if the status code is compare_error. description this command is used to compare the memory contents at two locations. the result may not be correct when the source or destination includes any of the first 512 bytes starting from address zero. the first 512 bytes can be re-mapped to ram.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 440 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware 26.7.8 reinvoke isp (iap) 26.7.9 readuid (iap) 26.7.10 erase page remark: see table 369 for list of parts that implement this command. table 403. iap reinvoke isp command compare input command code: 57 (decimal) status code none result none. description this command is used to invoke the bootloader in isp mode. it maps boot vectors, sets pclk = cclk, configures uart pins rxd and txd, resets counter/timer ct32b1 and resets the u0fdr (see table 200 ). this command may be used when a valid user program is present in the internal flash memory and the pio0_1 pin is not accessible to force the isp mode. if there is more than one boot source available (see section 26.1 ), pin pio0_3 must be configured correctly to sele ct the appropriate boot source: ? configure pin pio0_3 as output. ? drive the output to low or high depending on the boot source (see section 26.3.1 ). table 404. iap readuid command command compare input command code: 58 (decimal) status code cmd_success result result0: the first 32-bit word (at the lowest address). result1: the second 32-bit word. result2: the third 32-bit word. result3: the fourth 32-bit word. description this command is used to read the unique id. table 405. iap erase page command command erase page input command code: 59 (decimal) param0: start page number. param1: end page number (should be greater than or equal to start page) param2: system clock frequency (cclk) in khz. status code cmd_success | busy | sector_not_prepared_for_write_operation | invalid_sector result none description this command is used to erase a page or multiple pages of on-chip flash memory. to erase a single page use the same "start" and "end" page numbers. see ta b l e 3 6 9 for list of parts that implement this command.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 441 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware 26.7.11 iap status codes 26.8 debug notes 26.8.1 comparing flash images depending on the debugger used and the ide d ebug settings, the memory that is visible when the debugger connects might be the boot rom, the internal sram , or the flash. to help determine which memory is present in the current debug environment, check the value contained at flash address 0x0000 0004. this address contains the entry point to the code in the arm cortex-m0 vector table, which is the bottom of the boot rom, the internal sram, or the flash memory respectively. 26.8.2 serial wire debug (swd ) flash programming interface debug tools can write parts of the flash im age to ram and then execute the iap call "copy ram to flash" repeatedly with proper offset. table 406. iap status codes summary status code mnemonic description 0 cmd_success command is executed successfully. 1 invalid_command invalid command. 2 src_addr_error source address is not on a word boundary. 3 dst_addr_error destination address is not on a correct boundary. 4 src_addr_not_mapped source address is not mapped in the memory map. count value is taken in to consideration where applicable. 5 dst_addr_not_mapped destination address is not mapped in the memory map. count value is taken in to consideration where applicable. 6 count_error byte count is not multiple of 4 or is not a permitted value. 7 invalid_sector sector number is invalid. 8 sector_not_blank sector is not blank. 9 sector_not_prepared_ for_write_operation command to prepare sector for write operation was not executed. 10 compare_error source and destination data is not same. 11 busy flash programming hardware interface is busy. table 407. memory mapping in debug mode memory mapping mode memory start address visible at 0x0000 0004 bootloader mode 0x1fff 0000 user flash mode 0x0000 0000 user sram mode 0x1000 0000
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 442 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware 26.9 flash memory access depending on the system clock frequency, access to the flash memory can be configured with various access times by writing to the flashcfg register at address 0x4003 c010. remark: improper setting of this register may result in incorrect operation of the lpc111x/lpc11cxx flash memory. do not ma nipulate the flashcfg register when using power profiles (set_power() and/or set_pll() apis). table 408. flash configuration register (fla shcfg, address 0x4003 c010) bit description bit symbol value description reset value 1:0 flashtim flash memory access ti me. flashtim +1 is equal to the number of system clocks used for flash access. 10 0x0 1 system clock flash access time (for system clock frequencies of up to 20 mhz). 0x1 2 system clocks flash ac cess time (for system clock frequencies of up to 40 mhz). 0x2 3 system clocks flash ac cess time (for system clock frequencies of up to 50 mhz). 0x3 reserved. 31:2 - - reserved. user software must not change the value of these bits. bits 31:2 must be written back exactly as read . -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 443 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware 26.10 flash signature generation the flash module contains a built-in signatu re generator. this generator can produce a 128-bit signature from a range of flash memory . a typical usage is to verify the flashed contents against a calculated signature (e.g. during programming). the address range for generating a signature must be aligned on flash-word boundaries, i.e. 128-bit boundaries. once started, si gnature generation completes independently. while signature generation is in progress, t he flash memory cannot be accessed for other purposes, and an attempted re ad will cause a wait state to be asserted until signature generation is complete. code outside of the flash (e.g. internal ram) can be executed during signature generation. this can include interrupt services, if the interrupt vector table is re-mapped to memory other than the flash memory. the code that initiates signature generation should also be placed outside of the flash memory. 26.10.1 register descriptio n for signature generation 26.10.1.1 signature generation address and control registers these registers control automatic signature ge neration. a signature can be generated for any part of the flash memory contents. the address range to be used for generation is defined by writing the start address to the signature start address register (fmsstart) and the stop address to the si gnature stop address register (fmsstop. the start and stop addresses must be aligned to 128-bit boun daries and can be derived by dividing the byte address by 16. signature generation is started by setting the sig_start bit in the fmsstop register. setting the sig_start bit is typically comb ined with the signature stop address in a single write. table 410 and ta b l e 4 11 show the bit assignments in the fmsstart and fmsstop registers respectively. table 409. register overview: fmc (base address 0x4003 c000) name access address offset description reset value reference fmsstart r/w 0x020 signature start address register 0 table 410 fmsstop r/w 0x024 signature stop-address register 0 table 411 fmsw0 r 0x02c word 0 [31:0] - table 412 fmsw1 r 0x030 word 1 [63:32] - table 413 fmsw2 r 0x034 word 2 [95:64] - table 414 fmsw3 r 0x038 word 3 [127:96] - table 415 fmstat r 0xfe0 signature generation status register 0 section 26. 10.1.3 fmstatclr w 0xfe8 signature generation status clear register - section 26. 10.1.4
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 444 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware 26.10.1.2 signature generation result registers the signature generation result registers re turn the flash signature produced by the embedded signature generator. the 128-bit signature is reflected by the four registers fmsw0, fmsw1, fmsw2 and fmsw3. the generated flash signature can be used to verify the flash memory contents. the generated signature can be compared with an expected signature and thus makes saves time and code space. the method for generating the signature is described in section 26.10.2 . table 415 show bit assignment of the fmsw0 and fmsw1, fmsw2, fmsw3 registers respectively. table 410. flash module signature start regist er (fmsstart - 0x4003 c020) bit description bit symbol description reset value 16:0 start signature generation start address (corresponds to ahb byte address bits[20:4]). 0 31:17 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na table 411. flash module signature stop regist er (fmsstop - 0x4003 c024) bit description bit symbol value description reset value 16:0 stop bist stop address divided by 16 (corresponds to ahb byte address [20:4]). 0 17 sig_start start control bit for signature generation. 0 0 signature generation is stopped 1 initiate signature generation 31:18 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na table 412. fmsw0 register bit descri ption (fmsw0, address: 0x4003 c02c) bit symbol description reset value 31:0 sw0[31:0] word 0 of 128-bit signature (bits 31 to 0). - table 413. fmsw1 register bit descri ption (fmsw1, address: 0x4003 c030) bit symbol description reset value 31:0 sw1[63:32] word 1 of 128-bit signature (bits 63 to 32). - table 414. fmsw2 register bit descri ption (fmsw2, address: 0x4003 c034) bit symbol description reset value 31:0 sw2[95:64] word 2 of 128-bit signature (bits 95 to 64). - table 415. fmsw3 register bit description (fmsw3, address: 0x4003 40c8) bit symbol description reset value 31:0 sw3[127:96] word 3 of 128-bit signature (bits 127 to 96). -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 445 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware 26.10.1.3 flash module status register the read-only fmstat register provides a means of determining when signature generation has comple ted. completion of si gnature gene ration can be checked by polling the sig_done bit in fmstat. sig_done should be cleared via the fmstatclr register before starting a signature genera tion operation, otherwise the status might indicate completion of a previous operation. 26.10.1.4 flash module status clear register the fmstatclr register is used to clear the signature generation completion flag. 26.10.2 algorithm and procedure for signature generation signature generation a signature can be generated for any part of the flash contents. the address range to be used for signature generation is defined by writing the start address to the fmsstart register, and the stop address to the fmsstop register. the signature generation is started by writing a 1 to the sig_start bit in the fmsstop register. starting the signature generation is typically combined with defining the stop address, which is done in the stop bits of the same register. the time that the signature generation takes is proportional to the address range for which the signature is generated. reading of the flash memory for signature generation uses a self-timed read mechanism and does not de pend on any configurable timing settings for the flash. a safe estimation for the duration of the sign ature generation is: duration = int((60 / tcy) + 3) x (fmsstop - fmsstart + 1) table 416. flash module status register (fmstat - 0x4003 cfe0) bit description bit symbol description reset value 1:0 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na 2 sig_done when 1, a previously started signature generation has completed. see fmstatclr register description for clearing this flag. 0 31:3 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na table 417. flash module status clear register (fmstatclr - 0x0x4003 cfe8) bit description bit symbol description reset value 1:0 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na 2 sig_done_clr writing a 1 to this bits clears the signature generation completion flag (sig_done) in the fmstat register. 0 31:3 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 446 of 543 nxp semiconductors um10398 chapter 26: lpc111x/lpc11cxx flash programming firmware when signature generation is triggered via software, the duration is in ahb clock cycles, and tcy is the time in ns for one ahb clock. the sig_done bit in fmstat can be polled by software to determine when signature generation is complete. after signature generation, a 128-bit signature can be read from the fmsw0 to fmsw3 registers. the 128-bit signature reflects the co rrected data read from the flash. the 128-bit signature reflects flash parity bits and check bit values. content verification the signature as it is read from the fmsw0 to fmsw3 registers must be equal to the reference signature. the algorithms to de rive the reference signature is given in figure 93 . fig 93. algorithm for generating a 128-bit signature int128 signature = 0 int128 nextsignature for address = flashpage 0 to address = flashpage max { for i = 0 to 126 { nextsignature[i] = flashword[i] xor signature[i+1]} nextsignature[127] = flashword[127] xor signature[0] xor signature[2] xor signature[27] xor signature[29] signature = nextsignature } return signature
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 447 of 543 27.1 how to read this chapter the debug functionality is identical for all lpc111x, lpc11d14, and lpc11cxx parts. 27.2 features ? supports arm serial wire debug mode. ? direct debug access to all memories, registers, and peripherals. ? no target resources are required for the debugging session. ? four breakpoints. ? two data watchpoints that can also be used as triggers. 27.3 introduction debug functions are integrated into the arm co rtex-m0. serial wire debug functions are supported. the arm cortex-m0 is configured to support up to four breakpoints and two watchpoints. 27.4 description debugging with the lpc111x/lpc11cxx uses the serial wire debug mode. 27.5 pin description the tables below indicate the various pin functions related to debug. some of these functions share pins with other functions wh ich therefore may not be used at the same time. um10398 chapter 27: lpc111x/lpc11cxx serial wire debug (swd) rev. 12.1 ? 7 august 2013 user manual table 418. serial wire debug pin description pin name type description swclk input serial wire clock. this pin is the clock for debug logic when in the serial wire debug mode (swclk). this pin is pulled up internally. swdio input / output serial wire debug data input/output. the swdio pin is used by an external debug tool to communicate with and control the lpc111x/lpc11cxx. this pin is pulled up internally.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 448 of 543 nxp semiconductors um10398 chapter 27: lpc111x/lpc11cxx serial wire debug (swd) 27.6 debug notes 27.6.1 debug limitations important: the user should be aware of certain limitations during debugging. the most important is that, due to limitations of the arm cortex-m0 integration, the lpc111x/lpc11cxx cannot wake up in the usual manner from deep-sleep mode. it is recommended not to use this mode during debug. another issue is that debug mode changes the way in which reduced power modes work internal to the arm cortex-m0 cpu, and th is ripples through th e entire system. these differences mean that power measurements should not be made while debugging, the results will be higher than during normal operation in an application. during a debugging session, the system tick timer is automatically stopped whenever the cpu is stopped. other peripherals are not affected. 27.6.2 debug connections for debugging purposes, it is useful to prov ide access to the isp entry pin pio0_1. this pin can be used to recover the part from conf igurations which would disable the swd port such as improper pll configuration, reconfiguration of swd pins as adc inputs, entry into deep power-down mode out of reset, etc. this pin can be used for other functions such as gpio, but it should not be held low on power-up or reset. the vtref pin on the swd connector enables the debug connector to match the target voltage. fig 94. connecting the swd pins to a standard swd connector reset signals from swd connector swdio swclk vdd gnd vtref swdio swclk nsrst gnd lpc111x isp entry pio0_1
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 449 of 543 28.1 how to read this chapter the nmi is implemented on the lpc1100xl series (see section 3.5.29 ). parts on the lpc1100, lpc1100l, and lpc1100c series do not support the nmi. 28.2 introduction the following material is using the arm cortex-m0 user guide . minor changes have been made regarding the specific implemen tation of the cortex-m0 for the lpc111x, lpc11d14, and lpc11cxx parts. the arm cortex-m0 documentation is also available in ref. 1 and ref. 2 . 28.3 about the cortex-m0 processor and core peripherals the cortex-m0 processor is an entry-level 32-bit arm cortex processor designed for a broad range of embedded applications. it of fers significant benefits to developers, including: ? a simple architecture that is easy to learn and program ? ultra-low power, energy efficient operation ? excellent code density ? deterministic, high-performance interrupt handling ? upward compatibility with cortex-m processor family. um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference rev. 12.1 ? 7 august 2013 user manual fig 95. cortex-m0 implementation &ruwh[0surfhvvru &ruwh[0 surfhvvru fruh %xvpdwul[ 1hvwhg 9hfwruhg ,qwhuuxsw &rqwuroohu 19,& ,qwhuuxswv 'hexj $ffhvv3ruw '$3 $+%/lwhlqwhuidfhwrv\vwhp 6huldo:luhghexjsruw 'hexj 'hexjjhu lqwhuidfh %uhdnsrlqw dqg zdwfksrlqw xqlw &ruwh[0frpsrqhqwv
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 450 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference the cortex-m0 processor is built on a highly area and power optimized 32-bit processor core, with a 3-stage pipeline von neumann architecture. the processor delivers exceptional energy efficiency through a small but powerful instruction set and extensively optimized design, providing high-end processing hardware including a single-cycle multiplier. the cortex-m0 processor implements the armv 6-m architecture, which is based on the 16-bit thumb instruction set and includes thumb-2 technology. this provides the exceptional performance expected of a modern 32-bit architecture, with a higher code density than other 8-bit an d 16-bit microcontrollers. the cortex-m0 processor closely integrates a configurable nested vectored interrupt controlle r (nvic), to deliver industry-leading interrupt performance. the nvic: ? includes a non-maskable interrupt (nmi). see section 28.1 for implementation of the nmi for specific parts. ? provides zero jitter interrupt option ? provides four interr upt priority levels. the tight integration of the processor core and nvic provides fast execution of interrupt service routines (isrs), dramatically reducing the interrupt latency. this is achieved through the hardware stacki ng of registers, and the ability to abandon and restart load-multiple and stor e-multiple operations. interrupt handlers do not require any assembler wrapper code, removing any code overhead from the isrs. tail-chaining optimization also significantly reduces the overhead when switching from one isr to another. to optimize low-power designs, the nvic integr ates with the sleep modes, that include a deep-sleep function that enables the entire device to be rapidly powered down. 28.3.1 system-level interface the cortex-m0 processor provides a single system-level interface using amba technology to provide high speed, low latency memory accesses. 28.3.2 integrated configurable debug the cortex-m0 processor implements a complete hardware debug solution, with extensive hardware breakpoint and watchpoint options. this provides high system visibility of the processor, memory and peripherals through a 2-pin serial wire debug (swd) port that is ideal for microcontr ollers and other small package devices. 28.3.3 cortex-m0 processor features summary ? high code density with 32-bit performance ? tools and binary upwards compatible with cortex-m processor family ? integrated ultra low-power sleep modes ? efficient code execution permits slower pr ocessor clock or increases sleep mode time ? single-cycle 32-bit hardware multiplier ? zero jitter inte rrupt handling
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 451 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference ? extensive debug capabilities. 28.3.4 cortex-m0 core peripherals these are: nvic ? the nvic is an embedded interrupt controller that supports low latency interrupt processing. system control block ? the system control block (scb) is the programmers model interface to the processor. it provides syst em implementation information and system control, including configuration, contro l, and reporting of system exceptions. system timer ? the system timer, systick, is a 24-bit count-down timer. use this as a real time operating system (rtos) tick timer or as a simple counter. 28.4 processor 28.4.1 programmers model this section describes the cortex-m0 programme rs model. in addition to the individual core register descriptions, it contains info rmation about the proces sor modes and stacks. 28.4.1.1 processor modes the processor modes are: thread mode ? used to execute application software. the processor enters thread mode when it co mes out of reset. handler mode ? used to handle exceptions. the processor returns to thread mode when it has finished all exception processing. 28.4.1.2 stacks the processor uses a full descending stack. this means the stack pointer indicates the last stacked item on the stack memory. when the processor pushes a new item onto the stack, it decrements the stack pointer and then writes the item to the new memory location. the processor implements two stacks, the main stack and the process stack, with independent copies of the stack pointer, see section 28.4.1.3.2 . in thread mode, the control register cont rols whether the processor uses the main stack or the process stack, see section 28C28.4.1.3.7 . in handler mode , the processor always uses the main stack. the op tions for processor operations are: 28.4.1.3 core registers the processor core registers are: table 419. summary of processor mode and stack use options processor mode used to execute stack used thread applications main stack or process stack see section 28C28.4.1.3.7 handler exception handlers main stack
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 452 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference [1] describes access type during program executi on in thread mode and handler mode. debug access can differ. [2] bit[24] is the t-bit and is loaded from bit[0] of the reset vector. 28.4.1.3.1 general-purpose registers r0-r12 are 32-bit general-purpose registers for data operations. 28.4.1.3.2 stack pointer the stack pointer (sp) is register r13. in thread mode, bit[1] of the control register indicates the stack pointer to use: ? 0 = main stack pointer (msp). this is the reset value. ? 1 = process stack pointer (psp). fig 96. processor core register set table 420. core register set summary name type [1] reset value description r0-r12 rw unknown section 28C28.4.1.3.1 msp rw see description section 28C28.4.1.3.2 psp rw unknown section 28C28.4.1.3.2 lr rw unknown section 28C28.4.1.3.3 pc rw see description section 28C28.4.1.3.4 psr rw unknown [2] table 28C421 apsr rw unknown table 28C422 ipsr ro 0x00000000 table 423 epsr ro unknown [2] table 28C424 primask rw 0x00000000 table 28C425 control rw 0x00000000 table 28C426 3urjudp&rxqwhu 635 /55 3&5 5 5 5 5 5 5 5 5 5 5 5 5 5 /rzuhjlvwhuv +ljkuhjlvwhuv 063 363 &21752/ 365 /lqn5hjlvwhu 6wdfn3rlqwhu *hqhudosxusrvhuhjlvwhuv 3urjudp6wdwxv5hjlvwhu &rqwuro5hjlvwhu 6shfldouhjlvwhuv 35,0$6. ,qwhuuxswpdvnuhjlvwhu
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 453 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference on reset, the processor loads the msp with the value from address 0x00000000 . 28.4.1.3.3 link register the link register (lr) is register r14. it stores the return information for subroutines, function calls, and exceptions. on reset, the lr value is unknown. 28.4.1.3.4 program counter the program counter (pc) is register r15. it contains the current program address. on reset, the processor loads the pc with the value of the reset vector, which is at address 0x00000004 . bit[0] of the value is loaded into th e epsr t-bit at reset and must be 1. 28.4.1.3.5 program status register the program status register (psr) combines: ? application program status register (apsr) ? interrupt program status register (ipsr) ? execution program status register (epsr). these registers are mutually exclusive bitfields in the 32-bit psr. the psr bit assignments are: access these registers individually or as a co mbination of any two or all three registers, using the register name as an argument to the msr or mrs instructions. for example: ? read all of the registers using psr with the mrs instruction ? write to the apsr using apsr with the msr instruction. the psr combinations and attributes are: [1] the processor ignores writes to the ipsr bits. [2] reads of the epsr bits return zero, and the processor ignores writes to the these bits fig 97. apsr, ipsr, epsr register bit assignments table 421. psr register combinations register type combination psr rw [1] [2] apsr, epsr, and ipsr iepsr ro epsr and ipsr iapsr rw [1] apsr and ipsr eapsr rw [2] apsr and epsr 5hvhuyhg ([fhswlrqqxpehu 1=&9 5hvhuyhg $365 ,365 (365 5hvhuyhg 5hvhuyhg 7
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 454 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference see the instruction descriptions section 28C28.5.7.6 and section 28C28.5.7.7 for more information about how to access the program status registers. application program status register: the apsr contains the current state of the condition flags, from previous instructi on executions. see the register summary in table 28C420 for its attributes. the bit assignments are: see section 28.5.4.1.4 for more information about the apsr negative, zero, carry or borrow, and overflow flags. interrupt program status register: the ipsr contains the exception number of the current interrupt service routine (isr). see the register summary in table 28C420 for its attributes. the bit assignments are: execution program status register: the epsr contains the thumb state bit. see the register summary in table 28C420 for the epsr attributes . the bit assignments are: table 422. apsr bit assignments bits name function [31] n negative flag [30] z zero flag [29] c carry or borrow flag [28] v overflow flag [27:0] - reserved table 423. ipsr bit assignments bits name function [31:6] - reserved [5:0] exception number this is the number of the current exception: 0 = thread mode 1 = reserved 2 = nmi 3 = hardfault 4-10 = reserved 11 = svcall 12, 13 = reserved 14 = pendsv 15 = systick 16 = irq0 . . . 47 = irq31 48-63 = reserved. see section 28C28.4.3.2 for more information.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 455 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference attempts by application software to read the epsr directly using the mrs instruction always return zero. attempts to write the epsr using the msr instruction are ignored. fault handlers can examine the epsr value in the stacked psr to determine the cause of the fault. see section 28C28.4.3.6 . the following can clear the t bit to 0: ? instructions blx , bx and pop{pc} ? restoration from the stacked xpsr value on an exception return ? bit[0] of the vector value on an exception entry. attempting to execute instructions when the t bit is 0 results in a hardfault or lockup. see section 28C28.4.4.1 for more information. interruptible-restart able instructions: the interruptible-restartable instructions are ldm and stm . when an interrupt occurs during the execution of one of these instructions, the processor abandons execution of the instruction. after servicing the interrupt, the processor restarts execution of the instruction from the beginning. 28.4.1.3.6 exception mask register the exception mask register disables the handling of exceptions by the processor. disable exceptions where they might impact on timing critical tasks or code sequences requiring atomicity. to disable or re-enable exceptions, use the msr and mrs instructions, or the cps instruction, to change the value of primask. see section 28C28.5.7.6 , section 28C28.5.7.7 , and section 28C28.5.7.2 for more information. priority mask register: the primask register prevents activation of all exceptions with configurable priority. see the register summary in table 28C420 for its attributes. the bit assignments are: 28.4.1.3.7 control register the control register controls the stack used when the processor is in thread mode. see the register summary in table 28C420 for its attributes. the bit assignments are: table 424. epsr bi t assignments bits name function [31:25] - reserved [24] t thumb state bit [23:0] - reserved table 425. primask regi ster bit assignments bits name function [31:1] - reserved [0] primask 0 = no effect 1 = prevents the activation of all exceptions with configurable priority.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 456 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference handler mode always uses the msp, so the proc essor ignores explicit writes to the active stack pointer bit of the control register when in handler mode. the exception entry and return mechanisms update the control register. in an os environment, it is recommended that threads running in thread mode use the process stack and the kernel and exception handlers use the main stack. by default, thread mode uses the msp. to switch the stack pointer used in thread mode to the psp, use the msr instruction to set the active stack pointer bit to 1, see section 28C28.5.7.6 . remark: when changing the stack pointer, software must use an isb instruction immediately after the msr instruction. this ensures that instructions after the isb execute using the new stack pointer. see section 28C28.5.7.5 . 28.4.1.4 exceptions and interrupts the cortex-m0 processor supports interrupts and system exceptions. the processor and the nested vectored interrupt controller (nvic) prioritize and handle all exceptions. an interrupt or exception changes the normal flow of software control. the processor uses handler mode to handle all exceptions except for reset. see section 28C28.4.3.6.1 and section 28C28.4.3.6.2 for more information. the nvic registers control interrupt handling. see section 28C28.6.2 for more information. 28.4.1.5 data types the processor: ? supports the following data types: ? 32-bit words ? 16-bit halfwords ? 8-bit bytes ? manages all data memory accesses as little-endian. instruction memory and private peripheral bus (ppb) accesses are always little-endian. see section 28C28.4.2.1 for more information. 28.4.1.6 the cortex microcontroller software interface standard arm provides the cortex microcontroller software interface standard (cmsis) for programming cortex-m0 microcontrollers. the cmsi s is an integrated part of the device driver library. table 426. control register bit assignments bits name function [31:2] - reserved [1] active stack pointer defines the current stack: 0 = msp is the current stack pointer 1 = psp is the current stack pointer. in handler mode this bit reads as zero and ignores writes. [0] - reserved.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 457 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference for a cortex-m0 microcontroller system, cmsis defines: ? a common way to: ? access peripheral registers ? define exception vectors ? the names of: ? the registers of the core peripherals ? the core exception vectors ? a device-independent interface for rtos kernels. the cmsis includes address definitions and data structures for the core peripherals in the cortex-m0 processor. it also includes optional interfaces for middleware components comprising a tcp/ip stack and a flash file system. the cmsis simplifies software development by enabling the reuse of template code, and the combination of cmsis-compliant software components from various middleware vendors. software vendors can expand the cmsis to include their peripheral definitions and access functions for those peripherals. this document includes the register names defined by the cmsis, and gives short descriptions of the cmsis functions that address the processor core and the core peripherals. remark: this document uses the register short names defined by the cmsis. in a few cases these differ from the architectural short names that might be used in other documents. the following sections give more information about the cmsis: ? section 28.4.5.3 power management programming hints ? section 28.5.2 intrinsic functions ? section 28.6.2.1 accessing the cortex-m0 nvic registers using cmsis ? section 28.6.2.8.1 nvic programming hints . 28.4.2 memory model this section describes the processor memory map and the behavior of memory accesses. the processor has a fixed memory map that pr ovides up to 4gb of addressable memory. the memory map is:
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 458 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference the processor reserves regions of the private peripheral bus (ppb) address range for core peripheral registers, see section 28C28.3 . 28.4.2.1 memory regions, types and attributes the memory map is split into regions. each region has a defined memory type, and some regions have additional memory attributes. th e memory type and attributes determine the behavior of accesses to the region. the memory types are: normal ? the processor can re-order transactions for efficiency, or perform speculative reads. device ? the processor preserves transaction orde r relative to other transactions to device or strongly-ordered memory. see figure 6 for the lpc111x/lpc11cxx specific impl ementation of the memory map. sram and code locations are different on the lpc111x/lpc11cxx. fig 98. generic arm cortex-m0 memory map ([whuqdoghylfh ([whuqdo5$0 3hulskhudo 65$0 &rgh [)))))))) 3ulydwhshulskhudoexv [( [())))) [))))))) [$ [))))))) [ [))))))) [ [))))))) [ [ *% *% *% *% *% ['))))))) [( 0% 0% 'hylfh
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 459 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference strongly-ordered ? the processor preserves transaction order relative to all other transactions. the different ordering requirements for device and strongly-ordered memory mean that the memory system can buffer a write to device memory, but must no t buffer a write to strongly-ordered memory. the additional memory attributes include. execute never (xn) ? means the processor prevents inst ruction accesses. a hardfault exception is generated on executing an instruction fetched from an xn region of memory. 28.4.2.2 memory system ordering of memory accesses for most memory accesses caused by explic it memory access instructions, the memory system does not guarantee that the order in which the accesses complete matches the program order of the instructions, providing an y re-ordering does not affect the behavior of the instruction sequence. norm ally, if correct program execution depends on two memory accesses completing in program order, software must insert a memory barrier instruction between the memory access instructions, see section 28C28.4.2.4 . however, the memory system does guarantee some ordering of acce sses to device and strongly-ordered memory. for two memory access instructions a1 and a2, if a1 occurs before a2 in program order, the ordering of the memory accesses caused by two instructions is: where: - ? means that the memory system does not g uarantee the ordering of the accesses. < ? means that accesses are observed in program order, that is, a1 is always observed before a2. 28.4.2.3 behavior of memory accesses the behavior of accesses to each region in the memory map is: fig 99. memory ordering restrictions 1rupdodffhvv 'hylfhdffhvvqrqvkduhdeoh 'hylfhdffhvvvkduhdeoh 6wurqjo\rughuhgdffhvv 1rupdo dffhvv 1rqvkduhdeoh 6kduhdeoh 6wurqjo\ rughuhg dffhvv 'hylfhdffhvv $ $
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 460 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference [1] see section 28C28.4.2.1 for more information. the code, sram, and external ram regions can hold programs. 28.4.2.4 software ordering of memory accesses the order of instructions in the program flow does not always guarantee the order of the corresponding memory transactions. this is because: ? the processor can reorder some memory accesses to improve efficiency, providing this does not affect the behavior of the instruction sequence ? memory or devices in the memory map might have different wait states ? some memory accesses are buffered or speculative. section 28C28.4.2.2 describes the cases where the memory system guarantees the order of memory accesses. otherwise, if the orde r of memory accesses is critical, software must include memory barrier instructions to force that ordering. the processor provides the following memory ba rrier instructions: dmb ? the data memory barrier (dmb) instruction ensures that outstanding memory transactions complete before subs equent memory transactions. see section 28C28.5.7.3 . dsb ? the data synchronization barrier (dsb) instruction ensures that outstanding memory transactions complete before su bsequent instructions execute. see section 28C28.5.7.4 . isb ? the instruction synchronization barrier (isb) ensures that the effect of all completed memory transactions is reco gnizable by subsequent instructions. see section 28C28.5.7.5 . the following are examples of usin g memory barrier instructions: table 427. memory access behavior address range memory region memory type [1] xn [1] description 0x00000000 - 0x1fffffff code normal - executable region for program code. you can also put data here. 0x20000000 - 0x3fffffff sram normal - executable region for data. you can also put code here. 0x40000000 - 0x5fffffff peripheral device xn external device memory. 0x60000000 - 0x9fffffff external ram normal - executable region for data. 0xa0000000 - 0xdfffffff external device device xn external device memory. 0xe0000000 - 0xe00fffff private peripheral bus strongly-ordered xn this region includes the nvic, system timer, and system control block. only word accesses can be used in this region. 0xe0100000 - 0xffffffff device device xn vendor specific.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 461 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference vector table ? if the program changes an entry in the vector table, and then enables the corresponding exception, use a dmb instruction between the operations. this ensures that if the exception is taken immediately afte r being enabled the processor uses the new exception vector. self-modifying code ? if a program contains self-modifying code, use an isb instruction immediately after the code modification in the program. this ensures subsequent instruction execution uses the updated program. memory map switching ? if the system contains a memory map switching mechanism, use a dsb instruction after switching the memo ry map. this ensures subsequent instruction execution uses the updated memory map. memory accesses to strongly-ordered memory, such as the system control block, do not require the use of dmb instructions. the processor preserves transaction order relative to all other transactions. 28.4.2.5 memory endianness the processor views memory as a linear collection of bytes numbered in ascending order from zero. for example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word. section 28C28.4.2.5.1 describes how words of data are stored in memory. 28.4.2.5.1 little-endian format in little-endian format, the processor stores the least significant byte (lsbyte) of a word at the lowest-numbered byte, and the most significant byte (msbyte) at the highest-numbered byte. for example: 28.4.3 exception model this section describes the exception model. 28.4.3.1 exception states each exception is in one of the following states: inactive ? the exception is not active and not pending. pending ? the exception is waiting to be serviced by the processor. fig 100. little-endian format 5hjlvwhu $ ove\wh pve\wh $ $ % % % % % % % % 0hpru\ $ $gguhvv
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 462 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference an interrupt request from a peripheral or from software can change the state of the corresponding interrupt to pending. active ? an exception that is being serviced by the processor but has not completed. an exception handler can interrupt the execut ion of another exception handler. in this case both exceptions are in the active state. active and pending ? the exception is being serviced by the processor and there is a pending exception from the same source. 28.4.3.2 exception types the exception types are: remark: see section 28.1 for implementation of the nmi for specific parts. reset ? reset is invoked on power up or a warm reset. the exception model treats reset as a special form of exception. when reset is asserted, the operation of the processor stops, potentially at any point in an instru ction. when reset is deasserted, execution restarts from the address provided by the reset entry in the vector table. execution restarts in thread mode. nmi ? a nonmaskable interrupt (nmi) can be signalled by a peripheral or triggered by software. this is the highest priority exceptio n other than reset. it is permanently enabled and has a fixed priority of ? 2. nmis cannot be: ? masked or prevented from acti vation by any other exception ? preempted by any exception other than reset. hardfault ? a hardfault is an exception that occurs because of an error during normal or exception processing. hardfaults have a fixed priority of -1, meaning they have higher priority than any exception with configurable priority. svcall ? a supervisor call (svc) is an exception that is triggered by the svc instruction. in an os environment, applications can use svc instructions to access os kernel functions and device drivers. pendsv ? pendsv is an interrupt-driven request for system-level service. in an os environment, use pendsv for context switch ing when no other exception is active. systick ? a systick exception is an exception the system timer generates when it reaches zero. software can also generate a systick exception. in an os environment, the processor can use this ex ception as system tick. interrupt (irq) ? an interrupt, or irq, is an exception signalled by a peripheral, or generated by a software request. all interrupts are asynchronous to instruction execution. in the system, peripherals use interrup ts to communicate with the processor. table 428. properties of different exception types exception number [1] irq number [1] exception type priority vector address [2] 1 - reset -3, the highest 0x00000004 2- 1 4n m i- 2 0x00000008 3 -13 hardfault -1 0x0000000c 4-10 - reserved - - 11 -5 svcall configurable [3] 0x0000002c
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 463 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference [1] to simplify the software layer, the cmsis only us es irq numbers and therefore uses negative values for exceptions other than interrupts. the ipsr returns the exception number, see table 28C423 . [2] see section 28.4.3.4 for more information. [3] see section 28C28.6.2.6 . [4] increasing in steps of 4. for an asynchronous exception, other than re set, the processor can execute additional instructions between when the exception is triggered and when the processor enters the exception handler. privileged software can disable the exceptions that table 28C428 shows as having configurable priority, see section 28C28.6.2.3 . for more information about hardfaults, see section 28C28.4.4 . 28.4.3.3 exception handlers the processor handles exceptions using: interrupt service routines (isrs) ? interrupts irq0 to irq31 are the exceptions handled by isrs. fault handler ? hardfault is the only exception handled by the fault handler. system handlers ? nmi, pendsv, svcall systick, and hardfault are all system exceptions handled by system handlers. 28.4.3.4 vector table the vector table contains the reset value of the stack pointer, and the start addresses, also called exception vectors, for all exception handlers. figure 28C101 shows the order of the exception vectors in the vector table. th e least-significant bit of each vector must be 1, indicating that the exception han dler is written in thumb code. 12-13 - reserved - - 14 -2 pendsv configurable [3] 0x00000038 15 -1 systick configurable [3] 0x0000003c 16 and above 0 and above interrupt (irq) configurable [3] 0x00000040 and above [4] table 428. properties of different exception types exception number [1] irq number [1] exception type priority vector address [2]
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 464 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference the vector table is fixed at address 0x00000000 . 28.4.3.5 exception priorities as table 28C428 shows, all exceptions have an associated priority, with: ? a lower priority value indicating a higher priority ? configurable priorities for all exceptio ns except reset, hardfault, and nmi. if software does not configure any priorities, then all exceptions with a configurable priority have a priority of 0. for information ab out configuring exception priorities see ? section 28C28.6.3.7 ? section 28C28.6.2.6 . remark: configurable priority values are in the range 0-3. the reset, hardfault, and nmi exceptions, with fixed negative priority values, always have higher priority than any other exception. fig 101. vector table ,qlwldo63ydoxh 5hvhw +dug)dxow 10, [ [ [ [& [ 5hvhuyhg 69&doo 3hqg69 6\v7lfn ,54 5hvhuyhg [& [ [& [ 2iivhw ([fhswlrqqxpehu 9hfwru ,54 ,54 [ ,54 [ [%& ,54qxpehu
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 465 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference assigning a higher priority value to irq[0] an d a lower priority value to irq[1] means that irq[1] has higher priority than irq[0]. if bo th irq[1] and irq[0] ar e asserted, irq[1] is processed before irq[0]. if multiple pending exceptions have the sa me priority, the pending exception with the lowest exception number takes precedence. for example, if both irq[0] and irq[1] are pending and have the same priority, then irq[0] is processed before irq[1]. when the processor is executing an exc eption handler, the exception handler is preempted if a higher priority exception oc curs. if an exception oc curs with the same priority as the exception being handled, the handl er is not preempted, irrespective of the exception number. however, the status of the new interrupt changes to pending. 28.4.3.6 exception entry and return descriptions of exception handling use the following terms: preemption ? when the processor is executing an exception handler, an exception can preempt the exception handler if its priority is higher than the priority of the exception being handled. when one exception preempts another, the exceptions are called nested exceptions. see section 28C28.4.3.6.1 for more information. return ? this occurs when the exception handler is completed, and: ? there is no pending exception with sufficient priority to be serviced ? the completed exception handler was not handling a late-arriving exception. the processor pops the stack and restores the processor state to the state it had before the interrupt occurred. see section 28C28.4.3.6.2 for more information. tail-chaining ? this mechanism speeds up exception servicing. on completion of an exception handler, if there is a pending exception that meets the requirements for exception entry, the stack pop is skipped and control transfers to the new exception handler. late-arriving ? this mechanism speeds up preemption. if a higher priority exception occurs during state saving for a previous exc eption, the processor switches to handle the higher priority exception and initiates the vect or fetch for that exception. state saving is not affected by late arrival because the state saved would be the same for both exceptions. on return from the exception handler of the late-arriving exception, the normal tail-chaining rules apply. 28.4.3.6.1 exception entry exception entry occurs when there is a pendi ng exception with sufficient priority and either: ? the processor is in thread mode ? the new exception is of higher priority than the exception being handled, in which case the new exception preempts the exception being handled. when one exception preempts another, the exceptions are nested.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 466 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference sufficient priority means the exception has greater priority than any limit set by the mask register, see section 28C28.4.1.3.6 . an exception with less priority than this is pending but is not handled by the processor. when the processor takes an exception, un less the exception is a tail-chained or a late-arriving exception, the processor pushes information onto the current stack. this operation is referred to as stacking and the structure of eight data words is referred as a stack frame . the stack frame contains the following information: immediately after stacking, the stack pointer indicates the lowest address in the stack frame. the stack frame is aligned to a double-word address. the stack frame includes the return address. this is the address of the next instruction in the interrupted program. this value is restored to the pc at exception return so that the interrupted program resumes. the processor performs a vector fetch that reads the exception handler start address from the vector table. when stacking is complete, the processor starts ex ecuting the exception handler. at the same time, the processor wr ites an exc_return value to the lr. this indicates which stack pointer corresponds to the stack frame and what operation mode the processor was in before the entry occurred. if no higher priority exception occurs during exception entry, the processor starts executing the exception handler and autom atically changes the status of the corresponding pending interrupt to active. if another higher priority exception occurs during exception entry, the processor starts executing the exception handler for this exception and does not change the pending status of the earlier exception. this is the late arrival case. 28.4.3.6.2 exception return exception return occurs when the processor is in handler mode and execution of one of the following instructions attempts to set the pc to an exc_return value: ? a pop instruction that loads the pc ? a bx instruction using any register. the processor saves an exc_return value to the lr on exce ption entry. the exception mechanism relies on this value to detect when the processor has completed an exception handler. bits[31:4] of an exc_return value are 0xfffffff . when the processor loads a value matching this pattern to the pc it detects that the operation is a fig 102. exception entry stack contents 63srlqwvkhuhehiruhlqwhuuxsw [365 3& /5 5 5 5 5 5 suhylrxv! 63srlqwvkhuhdiwhulqwhuuxsw 63[& 63[ 63[ 63[ 63[& 63[ 63[ 63[ 'hfuhdvlqj phpru\ dgguhvv
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 467 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference not a normal branch operation and, instead, th at the exception is co mplete. therefore, it starts the exception return sequence. bits[3:0] of the exc_return value indicate the required return stack and processor mode, as table 28C429 shows. 28.4.4 fault handling faults are a subset of exceptions, see section 28C28.4.3 . all faults result in the hardfault exception being taken or cause lockup if they occur in the nmi or hardfault handler. the faults are: ? execution of an svc instruction at a priority equal or higher than svcall ? execution of a bkpt instruction without a debugger attached ? a system-generated bus error on a load or store ? execution of an instruction from an xn memory address ? execution of an instruction from a location for which the system generates a bus fault ? a system-generated bus error on a vector fetch ? execution of an undefined instruction ? execution of an instruction when not in t humb-state as a result of the t-bit being previously cleared to 0 ? an attempted load or store to an unaligned address. remark: only reset and nmi can preempt the fixed priority hardfault handler. a hardfault can preempt any exception other than reset, nmi, or another hard fault. 28.4.4.1 lockup the processor enters a lockup state if a fault occurs when executing the nmi or hardfault handlers, or if the system generates a bus error when unstacking the psr on an exception return using the msp. when the proces sor is in lockup state it does not execute any instructions. the processor remains in lo ckup state until one of the following occurs: ? it is reset ? a debugger halts it ? an nmi occurs and the current lockup is in the hardfault handler. table 429. exception return behavior exc_return description 0xfffffff1 return to handler mode. exception return gets state from the main stack. execution uses msp after return. 0xfffffff9 return to thread mode. exception return gets state from msp. execution uses msp after return. 0xfffffffd return to thread mode. exception return gets state from psp. execution uses psp after return. all other values reserved.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 468 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference remark: if lockup state occurs in the nmi handler a subsequent nmi does not cause the processor to leave lockup state. 28.4.5 power management the cortex-m0 processor sleep modes reduce power consumption: ? a sleep mode, that stops the processor clock ? a deep-sleep mode. the sleepdeep bit of the scr selects which sleep mode is used, see section 28C28.6.3.5 . this section describes the mechanisms for entering sleep mode and the conditions for waking up from sleep mode. 28.4.5.1 entering sleep mode this section describes the mechanisms softwa re can use to put the processor into sleep mode. the system can generate spurious wake-up ev ents, for example a d ebug operation wakes up the processor. therefore software must be able to put the processor back into sleep mode after such an event. a program might ha ve an idle loop to put the processor back in to sleep mode. 28.4.5.1.1 wait for interrupt the wait for interrupt instruction, wfi , causes immediate entry to sleep mode. when the processor executes a wfi instruction it stops executing instructions and enters sleep mode. see section 28C28.5.7.12 for more information. 28.4.5.1.2 wait for event remark: the wfe instruction is not implemented on the lpc111x/lpc11cxx. the wait for even t instruction, wfe , causes entry to sleep mode conditional on the value of a one-bit event register. when the processor executes a wfe instruction, it checks the value of the event register: 0 ? the processor stops executing inst ructions and enters sleep mode 1 ? the processor sets the register to zero an d continues executing instructions without entering sleep mode. see section 28C28.5.7.11 for more information. if the event register is 1, this indicates that the processor must not enter sleep mode on execution of a wfe instruction. typically, this is because of the assertion of an external event, or because another processor in the system has executed a sev instruction, see section 28C28.5.7.9 . software cannot access this register directly.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 469 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference 28.4.5.1.3 sleep-on-exit if the sleeponexit bit of the scr is set to 1, when the processor completes the execution of an exception handler and returns to thread mode it immediately enters sleep mode. use this mechanism in ap plications that only require the processor to run when an interrupt occurs. 28.4.5.2 wake-up from sleep mode the conditions for the processor to wake-up d epend on the mechanism that caused it to enter sleep mode. 28.4.5.2.1 wake-up from wfi or sleep-on-exit normally, the processor wa kes up only when it detects an exception with sufficient priority to cause exception entry. some embedded systems might have to execute system restore tasks after the processor wakes up, and before it executes an interrupt handler. to achieve this set the primask bit to 1. if an interrupt arrives that is enabled and has a higher priority than current exception priority, the processor wakes up but does not execute the interrupt handler until the processor sets primask to zero. for more in formation abou t primask, see section 28C28.4.1.3.6 . 28.4.5.2.2 wake-up from wfe the processor wakes up if: ? it detects an exception with sufficie nt priority to cause exception entry ? in a multiprocessor system, another processor in the system executes a sev instruction. in addition, if the sevonpend bit in the s cr is set to 1, any new pending interrupt triggers an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to cause exception ent ry. for more information about the scr see section 28C28.6.3.5 . 28.4.5.3 power management programming hints iso/iec c cannot directly generate the wfi , wfe , and sev instructions. the cmsis provides the following intrinsic fu nctions for these instructions: void __wfe(void) // wait for event void __wfi(void) // wait for interrupt void __sev(void) // send event 28.5 instruction set 28.5.1 instruction set summary the processor implements a version of the thumb instruction set. ta b l e 4 3 0 lists the supported instructions. remark: in table 430
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 470 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference ? angle brackets, <>, enclose alternative forms of the operand ? braces, {}, enclose optional operands and mnemonic parts ? the operands column is not exhaustive. for more information on the instructions an d operands, see the instruction descriptions. table 430. cortex-m0 instructions mnemonic operands brief description flags reference adcs {rd,} rn, rm add with carry n,z,c,v section 28C28.5.5.1 add{s} {rd,} rn, add n,z,c,v section 28C28.5.5.1 adr rd, label pc-relative address to register - section 28C28.5.4.1 ands {rd,} rn, rm bitwise and n,z section 28C28.5.5.1 asrs {rd,} rm, arithmetic shift right n,z,c section 28C28.5.5.3 b{cc} label branch {conditionally} - section 28C28.5.6.1 bics {rd,} rn, rm bit clear n,z section 28C28.5.5.2 bkpt #imm breakpoint - section 28C28.5.7.1 bl label branch with link - section 28C28.5.6.1 blx rm branch indirect with link - section 28C28.5.6.1 bx rm branch indirect - section 28C28.5.6.1 cmn rn, rm compare negative n,z,c,v section 28C28.5.5.4 cmp rn, compare n,z,c,v section 28C28.5.5.4 cpsid i change processor state, disable interrupts - section 28C28.5.7.2 cpsie i change processor state, enable interrupts - section 28C28.5.7.2 dmb - data memory barrier - section 28C28.5.7.3 dsb - data synchronization barrier - section 28C28.5.7.4 eors {rd,} rn, rm exclusive or n,z section 28C28.5.5.2 isb - instruction synchronization barrier - section 28C28.5.7.5 ldm rn{!}, reglist load multiple registers, increment after - section 28C28.5.4.5 ldr rt, label load register from pc-relative address - section 28C28.5.4 ldr rt, [rn, ] load register with word - section 28C28.5.4 ldrb rt, [rn, ] load register with byte - section 28C28.5.4 ldrh rt, [rn, ] load register with halfword - section 28C28.5.4 ldrsb rt, [rn, ] load register with signed byte - section 28C28.5.4 ldrsh rt, [rn, ] load register with signed halfword - section 28C28.5.4 lsls {rd,} rn, logical shift left n,z,c section 28C28.5.5.3 u {rd,} rn, logical shift right n,z,c section 28C28.5.5.3 mov{s} rd, rm move n,z section 28C28.5.5.5 mrs rd, spec_reg move to general register from special register - section 28C28.5.7.6 msr spec_reg, rm move to special register from general register n,z,c,v section 28C28.5.7.7 muls rd, rn, rm multiply, 32-bit result n,z section 28C28.5.5.6 mvns rd, rm bitwise not n,z section 28C28.5.5.5
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 471 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference 28.5.2 intrinsic functions iso/iec c code cannot directly access so me cortex-m0 instruct ions. this section describes intrinsic functions that can generate these instructions, provided by the cmsis and that might be provided by a c comp iler. if a c compiler does not support an appropriate intrinsic function, you might have to use inline assembler to access the relevant instruction. the cmsis provides the following intrinsic functions to generate instructions that iso/iec c code cannot directly access: nop - no operation - section 28C28.5.7.8 orrs {rd,} rn, rm logical or n,z section 28C28.5.5.2 pop reglist pop registers from stack - section 28C28.5.4.6 push reglist push registers onto stack - section 28C28.5.4.6 rev rd, rm byte-reverse word - section 28C28.5.5.7 rev16 rd, rm byte-reverse packed halfwords - section 28C28.5.5.7 revsh rd, rm byte-reverse signed halfword - section 28C28.5.5.7 rors {rd,} rn, rs rotate right n,z,c section 28C28.5.5.3 rsbs {rd,} rn, #0 reverse subtract n,z,c,v section 28C28.5.5.1 sbcs {rd,} rn, rm subtract with carry n,z,c,v section 28C28.5.5.1 sev - send event - section 28C28.5.7.9 stm rn!, reglist store multiple regist ers, increment after - section 28C28.5.4.5 str rt, [rn, ] store register as word - section 28C28.5.4 strb rt, [rn, ] store register as byte - section 28C28.5.4 strh rt, [rn, ] store register as halfword - section 28C28.5.4 sub{s} {rd,} rn, subtract n,z,c,v section 28C28.5.5.1 svc #imm supervisor call - section 28C28.5.7.10 sxtb rd, rm sign extend byte - section 28C28.5.5.8 sxth rd, rm sign extend halfword - section 28C28.5.5.8 tst rn, rm logical and based test n,z section 28C28.5.5.9 uxtb rd, rm zero extend a byte - section 28C28.5.5.8 uxth rd, rm zero extend a halfword - section 28C28.5.5.8 wfe - wait for event - section 28C28.5.7.11 wfi - wait for interrupt - section 28C28.5.7.12 table 430. cortex-m0 instructions mnemonic operands brief description flags reference table 431. cmsis intrinsic functions to generate some cortex-m0 instructions instruction cmsis intrinsic function cpsie i void __enable_irq(void) cpsid i void __disable_irq(void) isb void __isb(void) dsb void __dsb(void) dmb void __dmb(void) nop void __nop(void)
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 472 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference the cmsis also provides a number of functi ons for accessing the special registers using mrs and msr instructions: 28.5.3 about the instruction descriptions the following sections give more info rmation about using the instructions: ? section 28.5.3.1 operands ? section 28.5.3.2 restrictions when using pc or sp ? section 28.5.3.3 shift operations ? section 28.5.3.4 address alignment ? section 28.5.3.5 pc-relative expressions ? section 28.5.3.6 conditional execution . 28.5.3.1 operands an instruction operand can be an arm register, a constant, or another instruction-specific parameter. instructions act on the operands and often store the result in a destination register. when there is a destination register in the instruction, it is usually specified before the other operands. 28.5.3.2 restrictions when using pc or sp many instructions are unable to use, or have restrictions on whether you can use, the program counter (pc) or stack pointer (sp) for the operands or destination register. see instruction descriptions for more information. rev uint32_t __rev(uint32_t int value) rev16 uint32_t __rev16(uint32_t int value) revsh uint32_t __revsh (uint32_t int value) sev void __sev(void) wfe void __wfe(void) wfi void __wfi(void) table 432. cmsis intrinsic function s to access the special registers special register access cmsis function primask read uint32_t __get_primask (void) write void __set_prim ask (uint32_t value) control read uint32_t __get_control (void) write void __set_control (uint32_t value) msp read uint32_t __get_msp (void) write void __set_msp (uint32_t topofmainstack) psp read uint32_t __get_psp (void) write void __set_psp (uint32_t topofprocstack) table 431. cmsis intrinsic functions to generate some cortex-m0 instructions instruction cmsis intrinsic function
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 473 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference remark: when you update the pc with a bx, blx, or pop instruction, bit[0] of any address must be 1 for correct execution. this is because this bit indicates the destination instruction set, and the cortex-m0 processor only supports thumb instructions. when a bl or blx instruction writes the value of bit[0] into the lr it is automatically assigned the value 1. 28.5.3.3 shift operations register shift operations move the bits in a re gister left or right by a specified number of bits, the shift length . register shift can be performed directly by the instructions asr, lsr, lsl, and ror and the resu lt is written to a destination register.the permitted shift lengths depend on the shift type and the in struction, see the individual instruction description. if the shif t length is 0, no shift occurs. register shift operations update the carry flag except when the specified shift leng th is 0. the following sub-sections describe the various shift operations and how they af fect the carry flag. in these descriptions, rm is the register containing the value to be shifted, and n is the shift length. 28.5.3.3.1 asr arithmetic shift right by n bits moves the left-hand 32 - n bits of the register rm , to the right by n places, into the right-hand 32 - n bits of the result, and it copies the original bit[31] of the register into the left-hand n bits of the result. see figure 28C103 . you can use the asr operation to divi de the signed value in the register rm by 2 n , with the result being rounded towards negative-infinity. when the instruction is asrs the carry flag is updated to the last bit shifted out, bit[ n -1], of the register rm . remark: ? if n is 32 or more, then all the bits in the re sult are set to the value of bit[31] of rm . ? if n is 32 or more and the carry flag is updated, it is updated to the value of bit[31] of rm . 28.5.3.3.2 lsr logical shift right by n bits moves the left-hand 32- n bits of the register rm , to the right by n places, into the right-hand 32 - n bits of the result, and it sets the left-hand n bits of the result to 0. see figure 104 . fig 103. asr #3 &duu\ )odj
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 474 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference you can use the lsr operation to divide the value in the register rm by 2 n , if the value is regarded as an unsigned integer. when the instruction is lsrs, the carry flag is updated to the last bit shifted out, bit[ n -1], of the register rm . remark: ? if n is 32 or more, then all the bits in the result are cleared to 0. ? if n is 33 or more and the carry flag is updated, it is updated to 0. 28.5.3.3.3 lsl logical shift left by n bits moves the right-hand 32- n bits of the register rm , to the left by n places, into the left-hand 32- n bits of the result, and it sets the right-hand n bits of the result to 0. see figure 105 . you can use the lsl operation to multiply the value in the register rm by 2 n , if the value is regarded as an unsigned integer or a twos complement signed integer. overflow can occur without warning. when the instruction is lsls the carry flag is updated to the last bit shifted out, bit[32- n ], of the register rm . these instructions do not affect the carry flag when used with lsl #0. remark: ? if n is 32 or more, then all the bits in the result are cleared to 0. ? if n is 33 or more and the carry flag is updated, it is updated to 0. fig 104. lsr #3 &duu\ )odj fig 105. lsl #3 &duu\ )odj
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 475 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference 28.5.3.3.4 ror rotate right by n bits moves the left-hand 32- n bits of the register rm , to the right by n places, into the right-hand 32- n bits of the result, and it moves the right-hand n bits of the register into the left-hand n bits of the result. see figure 28C106 . when the instruction is rors the carry flag is updated to the last bit rotation, bit[ n -1], of the register rm . remark: ? if n is 32, then the value of the re sult is same as the value in rm , and if the carry flag is updated, it is upd ated to bit[31] of rm . ? ror with shift length, n , greater than 32 is the same as ror with shift length n -32. 28.5.3.4 address alignment an aligned access is an operation where a word-aligned address is used for a word, or multiple word access, or where a halfword-aligned address is used for a halfword access. byte accesses are always aligned. there is no support for unaligned accesses on the cortex-m0 processor. any attempt to perform an unaligned memory access operation results in a hardfault exception. 28.5.3.5 pc-relative expressions a pc-relative expression or label is a symbol that represents the address of an instruction or literal data. it is represented in the instruction as the pc value plus or minus a numeric offset. the assembler calculates the required offset from the label and the address of the current instruction. if the offset is to o big, the assembler produces an error. remark: ? for most instructions, the value of the pc is the address of the current instruction plus 4 bytes. ? your assembler might permit other syntaxes for pc-relative expressions, such as a label plus or minus a number, or an expression of the form [pc, # imm ]. fig 106. ror #3 &duu\ )odj
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 476 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference 28.5.3.6 conditional execution most data processing instructions update the condition flags in the application program status register (apsr) according to the resu lt of the operation, see section . some instructions update all flags, and some only update a subset. if a flag is not updated, the original value is preserved. see the instruct ion descriptions for the flags they affect. you can execute a conditional branch instruct ion, based on the condition flags set in another instruction, either: ? immediately after the instruction that updated the flags ? after any number of intervening instructions that have not updated the flags. on the cortex-m0 processor, conditional ex ecution is available by using conditional branches. this section describes: ? section 28.5.3.6.1 the condition flags ? section 28.5.3.6.2 condition code suffixes . 28.5.3.6.1 the condition flags the apsr contains the following condition flags: n ? set to 1 when the result of the operat ion was negative, cleared to 0 otherwise. z ? set to 1 when the result of the operation was zero, cleared to 0 otherwise. c ? set to 1 when the operation resulted in a carry, cleared to 0 otherwise. v ? set to 1 when the operation caused overflow, cleared to 0 otherwise. for more information about the apsr see section 28C28.4.1.3.5 . a carry occurs: ? if the result of an addition is greater than or equal to 2 32 ? if the result of a subtraction is positive or zero ? as the result of a shift or rotate instruction. overflow occurs when the sign of the result , in bit[31], does not match the sign of the result had the operation been performed at infinite precision, for example: ? if adding two negative values results in a positive value ? if adding two positive values results in a negative value ? if subtracting a positive value from a neg ative value generates a positive value ? if subtracting a negative value from a pos itive value generates a negative value. the compare operations are identical to subtracting, for cmp, or adding, for cmn, except that the result is discarded. see the inst ruction descriptions for more information. 28.5.3.6.2 condition code suffixes conditional branch is shown in syntax descriptions as b{ cond }. a branch instruction with a condition code is only taken if the condition code flags in the apsr meet the specified condition, otherwise the branch instruction is ignored. shows the condition codes to use.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 477 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference table 433 also shows the relationship between condition code suffixes and the n, z, c, and v flags. 28.5.4 memory access instructions table 434 shows the memory access instructions: 28.5.4.1 adr generates a pc-relative address. 28.5.4.1.1 syntax adr rd , label table 433. condition code suffixes suffix flags meaning eq z = 1 equal, last flag setting result was zero ne z = 0 not equal, last flag setting result was non-zero cs or hs c = 1 higher or same, unsigned cc or lo c = 0 lower, unsigned mi n = 1 negative pl n = 0 positive or zero vs v = 1 overflow vc v = 0 no overflow hi c = 1 and z = 0 higher, unsigned ls c = 0 or z = 1 lower or same, unsigned ge n = v greater than or equal, signed lt n ? = v less than, signed gt z = 0 and n = v greater than, signed le z = 1 and n ? = v less than or equal, signed al can have any value always. this is the default when no suffix is specified. table 434. access instructions mnemonic brief description see ldr{type} load register using register offset section 28C28.5.4. 3 ldr load register from pc-relative address section 28C28.5.4. 4 pop pop registers from stack section 28C28.5.4. 6 push push registers onto stack section 28C28.5.4. 6 stm store multiple registers section 28C28.5.4. 5 str{type} store register using immediate offset section 28C28.5.4. 2 str{type} store register using register offset section 28C28.5.4. 3
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 478 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference where: rd is the destination register. label is a pc-relative expression. see section 28C28.5.3.5 . 28.5.4.1.2 operation adr generates an address by adding an immediat e value to the pc, and writes the result to the destination register. adr facilitates the generation of position-independent co de, because t he address is pc-relative. if you use adr to generate a target address for a bx or blx instruction, you must ensure that bit[0] of the address you generate is set to 1 for correct execution. 28.5.4.1.3 restrictions in this instruction rd must specify r0-r7. the data-value addressed must be word aligned and within 1020 bytes of the current pc. 28.5.4.1.4 condition flags this instruction does not change the flags. 28.5.4.1.5 examples adr r1, textmessage ; write address value of a location labelled as ; textmessage to r1 adr r3, [pc,#996] ; set r3 to value of pc + 996. 28.5.4.2 ldr and str, immediate offset load and store with immediate offset. 28.5.4.2.1 syntax ldr rt , [< rn | sp> {, # imm }] ldr rt , [ rn {, # imm }] str rt , [< rn | sp>, {,# imm }] str rt , [ rn {,# imm }] where: rt is the register to load or store. rn is the register on which the memory address is based. imm is an offset from rn . if imm is omitted, it is assumed to be zero. 28.5.4.2.2 operation ldr, ldrb and ldrh instructions load the register specified by rt with either a word, byte or halfword data value from memory. sizes less than word are zero extended to 32-bits before being written to the register specified by rt .
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 479 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference str, strb and strh instructions store the word, least-signif icant byte or lower halfword contained in the single register specified by rt in to memory. the memory address to load from or store to is the sum of the value in the register specified by either rn or sp and the immediate value imm . 28.5.4.2.3 restrictions in these instructions: ? rt and rn must only specify r0-r7. ? imm must be between: ? 0 and 1020 and an integer multiple of four for ldr and str using sp as the base register ? 0 and 124 and an integer multiple of four for ldr and str using r0-r7 as the base register ? 0 and 62 and an integer multiple of two for ldrh and strh ? 0 and 31 for ldrb and strb. ? the computed address must be divisible by the number of bytes in the transaction, see section 28C28.5.3.4 . 28.5.4.2.4 condition flags these instructions do not change the flags. 28.5.4.2.5 examples ldr r4, [r7 ; loads r4 from the address in r7. str r2, [r0,#const-struc] ; const-struc is an expression evaluating ; to a constant in the range 0-1020. 28.5.4.3 ldr and str, register offset load and store with register offset. 28.5.4.3.1 syntax ldr rt , [ rn , rm ] ldr rt , [ rn , rm ] ldr rt , [ rn , rm ] str rt , [ rn , rm ] str rt , [ rn , rm ] where: rt is the register to load or store. rn is the register on which the memory address is based. rm is a register containing a value to be used as the offset.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 480 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference 28.5.4.3.2 operation ldr, ldrb, u, ldrsb and ldrsh load the register specified by rt with either a word, zero extended byte, zero extended halfword , sign extended byte or sign extended halfword value from memory. str, strb and strh store the word, least-significant byte or lower halfword contained in the single register specified by rt into memory. the memory address to load from or store to is the sum of the values in the registers specified by rn and rm . 28.5.4.3.3 restrictions in these instructions: ? rt , rn , and rm must only specify r0-r7. ? the computed memory address must be divisible by the number of bytes in the load or store, see section 28C28.5.3.4 . 28.5.4.3.4 condition flags these instructions do not change the flags. 28.5.4.3.5 examples str r0, [r5, r1] ; store value of r0 into an address equal to ; sum of r5 and r1 ldrsh r1, [r2, r3] ; load a halfword from the memory address ; specified by (r2 + r3), sign extend to 32-bits ; and write to r1. 28.5.4.4 ldr, pc-relative load register (literal) from memory. 28.5.4.4.1 syntax ldr rt , label where: rt is the register to load. label is a pc-relative expression. see section 28C28.5.3.5 . 28.5.4.4.2 operation loads the register specified by rt from the word in memory specified by label . 28.5.4.4.3 restrictions in these instructions, label must be within 1020 bytes of the current pc and word aligned. 28.5.4.4.4 condition flags these instructions do not change the flags.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 481 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference 28.5.4.4.5 examples ldr r0, lookuptable ; load r0 with a word of data from an address ; labelled as lookuptable. ldr r3, [pc, #100] ; load r3 with memory word at (pc + 100). 28.5.4.5 ldm and stm load and store multiple registers. 28.5.4.5.1 syntax ldm rn {!}, reglist stm rn !, reglist where: rn is the register on which the memory addresses are based. ! writeback suffix. reglist is a list of one or more registers to be loaded or stored, enclosed in braces. it can contain register ranges. it must be comma separated if it contains more than one register or register range, see section 28C28.5.4.5.5 . ldmia and ldmfd are synonyms for ldm. ld mia refers to the base register being incremented after each access. ldmfd refers to its use for popping data from full descending stacks. stmia and stmea are synonyms for stm. stmia refers to the base register being incremented after each access . stmea refers to its use fo r pushing data onto empty ascending stacks. 28.5.4.5.2 operation ldm instructions load the registers in reglist with word values from memory addresses based on rn . stm instructions store the word values in the registers in reglist to memory addresses based on rn . the memory addresses used for the accesses are at 4-byte intervals ranging from the value in the register specified by rn to the value in the register specified by rn + 4 * ( n -1), where n is the number of registers in reglist . the accesses happens in order of increasing register numbers, with the lowest numbered register using the lowest memory address and the highest number register using the high est memory address. if the writeback suffix is specified, the value in the register specified by rn + 4 * n is written back to the register specified by rn . 28.5.4.5.3 restrictions in these instructions: ? reglist and rn are limited to r0-r7. ? the writeback suffix must always be used unless the instruction is an ldm where reglist also contains rn , in which case the writeback suffix must not be used.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 482 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference ? the value in the register specified by rn must be word aligned. see section 28C28.5.3.4 for more information. ? for stm, if rn appears in reglist , then it must be the first register in the list. 28.5.4.5.4 condition flags these instructions do not change the flags. 28.5.4.5.5 examples ldm r0,{r0,r3,r4} ; ldmia is a synonym for ldm stmia r1!,{r2-r4,r6} 28.5.4.5.6 incorrect examples stm r5!,{r4,r5,r6} ; value stored for r5 is unpredictable ldm r2,{} ; there must be at least one register in the list 28.5.4.6 push and pop push registers onto, and pop registers off a full-descending stack. 28.5.4.6.1 syntax push reglist pop reglist where: reglist is a non-empty list of registers, enclosed in braces. it can contain register ranges. it must be comma separated if it contains more than one register or register range. 28.5.4.6.2 operation push stores registers on the stack, with th e lowest numbered register using the lowest memory address and the highest numbered re gister using the highest memory address. pop loads registers from the stack, with the lowest number ed register using the lowest memory address and the highest numbered re gister using the highest memory address. push uses the value in the sp register mi nus four as the highest memory address, pop uses the value in the sp register as th e lowest memory address, implementing a full-descending stack. on completion, push updates the sp register to point to the location of the lowest store value, pop updates the sp register to point to the location above the highest location loaded. if a pop instruction includes pc in its reglist , a branch to this location is performed when the pop instruction has completed. bit[0] of the value read fo r the pc is used to update the apsr t-bit. this bit must be 1 to ensure correct operation. 28.5.4.6.3 restrictions in these instructions: ? reglist must use only r0-r7.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 483 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference ? the exception is lr for a push and pc for a pop. 28.5.4.6.4 condition flags these instructions do not change the flags. 28.5.4.6.5 examples push {r0,r4-r7} ; push r0,r4,r5,r6,r7 onto the stack push {r2,lr} ; push r2 and the link-register onto the stack pop {r0,r6,pc} ; pop r0,r6 and pc from the stack, then branch to ; the new pc. 28.5.5 general data processing instructions table 435 shows the data processing instructions: table 435. data processing instructions mnemonic brief description see adcs add with carry section 28C28.5.5.1 add{s} add section 28C28.5.5.1 ands logical and section 28C28.5.5.2 asrs arithmetic shift right section 28C28.5.5.3 bics bit clear section 28C28.5.5.2 cmn compare negative section 28C28.5.5.4 cmp compare section 28C28.5.5.4 eors exclusive or section 28C28.5.5.2 lsls logical shift left section 28C28.5.5.3 lsrs logical shift right section 28C28.5.5.3 mov{s} move section 28C28.5.5.5 muls multiply section 28C28.5.5.6 mvns move not section 28C28.5.5.5 orrs logical or section 28C28.5.5.2 rev reverse byte order in a word section 28C28.5.5.7 rev16 reverse byte order in each halfword section 28C28.5.5.7 revsh reverse byte order in bottom halfword and sign extend section 28C28.5.5.7 rors rotate right section 28C28.5.5.3 rsbs reverse subtract section 28C28.5.5.1 sbcs subtract with carry section 28C28.5.5.1 subs subtract section 28C28.5.5.1 sxtb sign extend a byte section 28C28.5.5.8 sxth sign extend a halfword section 28C28.5.5.8 uxtb zero extend a byte section 28C28.5.5.8 uxth zero extend a halfword section 28C28.5.5.8 tst test section 28C28.5.5.9
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 484 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference 28.5.5.1 adc, add, rsb, sbc, and sub add with carry, add, reverse subtract , subtract with carry, and subtract. 28.5.5.1.1 syntax adcs { rd ,} rn , rm add{s} { rd ,} rn , rsbs { rd ,} rn , rm , #0 sbcs { rd ,} rn , rm sub{s} { rd ,} rn , where: s causes an add or sub instruction to update flags rd specifies the result register rn specifies the first source register rm specifies the second source register imm specifies a constant immediate value. when the optional rd register specifier is omitted, it is assumed to take the same value as rn , for example adds r1,r2 is identical to adds r1,r1,r2. 28.5.5.1.2 operation the adcs instruction adds the value in rn to the value in rm , adding a further one if the carry flag is set, places the result in the register specified by rd and updates the n, z, c, and v flags. the add instruction adds the value in rn to the value in rm or an immediate value specified by imm and places the result in the register specified by rd . the adds instruction performs the same operation as add and also updates the n, z, c and v flags. the rsbs instruction subtracts the value in rn from zero, producing the arithmetic negative of the value, and places the result in the register specified by rd and updates the n, z, c and v flags. the sbcs instruction subtracts the value of rm from the value in rn , deducts a further one if the carry flag is set. it places the resu lt in the register specified by rd and updates the n, z, c and v flags. the sub instruction subtracts the value in rm or the immediate specified by imm . it places the result in the register specified by rd . th e subs instruction performs the same operat ion as sub and also updates the n, z, c and v flags. use adc and sbc to synthesize multiword arithmetic, see section 28.5.5.1.4 .
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 485 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference see also section 28C28.5.4.1 . 28.5.5.1.3 restrictions table 436 lists the legal combinations of register specifiers and immediate values that can be used with each instruction. 28.5.5.1.4 examples the following shows two instructions that add a 64-bit integer contained in r0 and r1 to another 64-bit integer contained in r2 and r3, and place the result in r0 and r1. 64-bit addition: adds r0, r0, r2 ; add the least significant words adcs r1, r1, r3 ; add the most significant words with carry multiword values do not have to use consecutive re gisters. the following shows instructions that subtract a 96-bit integer contained in r1, r2, and r3 from another contained in r4, r5, and r6. the example stores the result in r4, r5, and r6. 96-bit subtraction: subs r4, r4, r1 ; subtract the least significant words sbcs r5, r5, r2 ; subtract the middle words with carry sbcs r6, r6, r3 ; subtract the most significant words with carry the following shows the rsbs inst ruction used to pe rform a 1's compleme nt of a single register. arithmetic negation: rsbs r7, r7, #0 ; subtract r7 from zero 28.5.5.2 and, orr, eor, and bic logical and, or, exclusive or, and bit clear. table 436. adc, add, rsb, sbc and sub operand restrictions instruction rd rn rm imm restrictions adcs r0-r7 r0-r7 r0-r7 - rd and rn must specify t he same register. add r0-r15 r0-r15 r0-pc - rd and rn must specify the same register. rn and rm must not both specify pc. r0-r7 sp or pc - 0-1020 immediate value must be an integer multiple of four. sp sp - 0-508 immediate value must be an integer multiple of four. adds r0-r7 r0-r7 - 0-7 - r0-r7 r0-r7 - 0-255 rd and rn must specify t he same register. r0-r7 r0-r7 r0-r7 - - rsbs r0-r7 r0-r7 - - - sbcs r0-r7 r0-r7 r0-r7 - rd and rn must specify t he same register. sub sp sp - 0-508 immediate value must be an integer multiple of four. subs r0-r7 r0-r7 - 0-7 - r0-r7 r0-r7 - 0-255 rd and rn must specify t he same register. r0-r7 r0-r7 r0-r7 - -
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 486 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference 28.5.5.2.1 syntax ands { rd, } rn , rm orrs { rd, } rn , rm eors { rd, } rn , rm bics { rd, } rn , rm where: rd is the destination register. rn is the register holding the first operand and is the same as the destination register. rm second register. 28.5.5.2.2 operation the and, eor, and orr instru ctions perform bitwise and, exclusive or, and inclusive or operations on the values in rn and rm . the bic instruction performs an and operation on the bits in rn with the logical negation of the corresponding bits in the value of rm . the condition code flags are updated on the result of the operation, see section 28.5.3.6.1 . 28.5.5.2.3 restrictions in these instructions, rd , rn , and rm must only specify r0-r7. 28.5.5.2.4 condition flags these instructions: ? update the n and z flags according to the result ? do not affect the c or v flag. 28.5.5.2.5 examples ands r2, r2, r1 orrs r2, r2, r5 ands r5, r5, r8 eors r7, r7, r6 bics r0, r0, r1 28.5.5.3 asr, lsl, lsr, and ror arithmetic shift right, logical shift left, logical shift right, and rotate right. 28.5.5.3.1 syntax asrs {rd,} rm , rs asrs {rd,} rm , # imm lsls {rd,} rm , rs lsls {rd,} rm , # imm
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 487 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference lsrs {rd,} rm , rs lsrs {rd,} rm , # imm rors {rd,} rm , rs where: rd is the destination register. if rd is omitted, it is assumed to take the same value as rm . rm is the register holding the value to be shifted. rs is the register holding the shift length to apply to the value in rm . imm is the shift length. the range of shift length depends on the instruction: asr ? shift length from 1 to 32 lsl ? shift length from 0 to 31 lsr ? shift length from 1 to 32. remark: movs rd, rm is a pseudonym for lsls rd, rm , #0. 28.5.5.3.2 operation asr, lsl, lsr, and ror perform an arithmetic-shift-left, logical-shift-left, logical-shift-right or a right-rotation of the bits in the register rm by the number of places specified by the immediate imm or the value in the least-significant byte of the register specified by rs . for details on what result is generated by the different instructions, see section 28C28.5.3.3 . 28.5.5.3.3 restrictions in these instructions, rd , rm , and rs must only specify r0-r 7. for non-immediate instructions, rd and rm must specify the same register. 28.5.5.3.4 condition flags these instructions update the n an d z flags according to the result. the c flag is updated to the last bit shifted out, except when the shift length is 0, see section 28C28.5.3.3 . the v flag is left unmodified. 28.5.5.3.5 examples asrs r7, r5, #9 ; arithmetic shift right by 9 bits lsls r1, r2, #3 ; logical shift left by 3 bits with flag update lsrs r4, r5, #6 ; logical shift right by 6 bits rors r4, r4, r6 ; rotate right by the value in the bottom byte of r6. 28.5.5.4 cmp and cmn compare and compare negative.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 488 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference 28.5.5.4.1 syntax cmn rn , rm cmp rn , #imm cmp rn , rm where: rn is the register holding the first operand. rm is the register to compare with. imm is the immediate value to compare with. 28.5.5.4.2 operation these instructions compare the value in a regist er with either the value in another register or an immediate value. they update the cond ition flags on the result, but do not write the result to a register. the cmp instruction subtracts either th e value in the register specified by rm , or the immediate imm from the value in rn and updates the flags. this is the same as a subs instruction, except that the result is discarded. the cmn instruction adds the value of rm to the value in rn and updates the flags. this is the same as an adds instruction, except that the result is discarded. 28.5.5.4.3 restrictions for the: ? cmn instruction rn , and rm must only specify r0-r7. ? cmp instruction: ? rn and rm can specify r0-r14 ? immediate must be in the range 0-255. 28.5.5.4.4 condition flags these instructions update the n, z, c and v flags according to the result. 28.5.5.4.5 examples cmp r2, r9 cmn r0, r2 28.5.5.5 mov and mvn move and move not. 28.5.5.5.1 syntax mov{s} rd , rm movs rd , # imm
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 489 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference mvns rd , rm where: s is an optional suffix. if s is specified, the condition code flags are updated on the result of the operation, see section 28C28.5.3.6 . rd is the destination register. rm is a register. imm is any value in the range 0-255. 28.5.5.5.2 operation the mov instruction copies the value of rm into rd . the movs instruction performs the same opera tion as the mov instruction, but also updates the n and z flags. the mvns instruction takes the value of rm , performs a bitwise logical negate operation on the value, and places the result into rd . 28.5.5.5.3 restrictions in these instructions, rd , and rm must only specify r0-r7. when rd is the pc in a mov instruction: ? bit[0] of the result is discarded. ? a branch occurs to the address created by fo rcing bit[0] of the result to 0. the t-bit remains unmodified. remark: though it is possible to use mov as a branch instruction, arm strongly recommends the use of a bx or blx instruct ion to branch for software portability. 28.5.5.5.4 condition flags if s is specified, these instructions: ? update the n and z flags according to the result ? do not affect the c or v flags. 28.5.5.5.5 example movs r0, #0x000b ; write value of 0x000b to r0, flags get updated movs r1, #0x0 ; write value of zero to r1, flags are updated mov r10, r12 ; write value in r12 to r10, flags are not updated movs r3, #23 ; write value of 23 to r3 mov r8, sp ; write value of stack pointer to r8 mvns r2, r0 ; write inverse of r0 to the r2 and update flags 28.5.5.6 muls multiply using 32-bit operands, and producing a 32-bit result. 28.5.5.6.1 syntax muls rd, rn , rm
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 490 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference where: rd is the destination register. rn, rm are registers holding the values to be multiplied. 28.5.5.6.2 operation the mul instruction multiplies the valu es in the registers specified by rn and rm , and places the least significant 32 bits of the result in rd . the condition code flags are updated on the result of the operation, see section 28C28.5.3.6 . the results of this instruction does not depend on whether the operands are signed or unsigned. 28.5.5.6.3 restrictions in this instruction: ? rd , rn , and rm must only specify r0-r7 ? rd must be the same as rm . 28.5.5.6.4 condition flags this instruction: ? updates the n and z flags according to the result ? does not affect the c or v flags. 28.5.5.6.5 examples muls r0, r2, r0 ; multiply with flag update, r0 = r0 x r2 28.5.5.7 rev, rev16, and revsh reverse bytes. 28.5.5.7.1 syntax rev rd, rn rev16 rd, rn revsh rd, rn where: rd is the destination register. rn is the source register. 28.5.5.7.2 operation use these instructions to change endianness of data: rev ? converts 32-bit big-endian data into little-endian data or 32-bit little-endian data into big-endian data. rev16 ? converts two packed 16-bit big-endian data into little-endian data or two packed 16-bit little-endian data into big-endian data.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 491 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference revsh ? converts 16-bit signed big-endian data into 32-bit signed little-endian data or 16-bit signed little-endian data into 32-bit signed big-endian data. 28.5.5.7.3 restrictions in these instructions, rd , and rn must only specify r0-r7. 28.5.5.7.4 condition flags these instructions do not change the flags. 28.5.5.7.5 examples rev r3, r7 ; reverse byte order of value in r7 and write it to r3 rev16 r0, r0 ; reverse byte order of each 16-bit halfword in r0 revsh r0, r5 ; reverse signed halfword 28.5.5.8 sxt and uxt sign extend and zero extend. 28.5.5.8.1 syntax sxtb rd, rm sxth rd, rm uxtb rd, rm uxth rd, rm where: rd is the destination register. rm is the register holding the value to be extended. 28.5.5.8.2 operation these instructions extract bits from the resulting value: ? sxtb extracts bits[7:0] and sign extends to 32 bits ? uxtb extracts bits[7:0] and zero extends to 32 bits ? sxth extracts bits[15:0] an d sign extends to 32 bits ? uxth extracts bits[15:0] and zero extends to 32 bits. 28.5.5.8.3 restrictions in these instructions, rd and rm must only specify r0-r7. 28.5.5.8.4 condition flags these instructions do not affect the flags.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 492 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference 28.5.5.8.5 examples sxth r4, r6 ; obtain the lower halfword of the ; value in r6 and then sign extend to ; 32 bits and write the result to r4. uxtb r3, r1 ; extract lowest byte of the value in r10 and zero ; extend it, and write the result to r3 28.5.5.9 tst test bits. 28.5.5.9.1 syntax tst rn , rm where: rn is the register holding the first operand. rm the register to test against. 28.5.5.9.2 operation this instruction tests the value in a regist er against another register. it updates the condition flags based on the result, but do es not write the result to a register. the tst instruction performs a bitwise and operation on the value in rn and the value in rm . this is the same as the ands instruct ion, except that it discards the result. to test whether a bit of rn is 0 or 1, use the tst instruction with a register that has that bit set to 1 and all other bits cleared to 0. 28.5.5.9.3 restrictions in these instructions, rn and rm must only specify r0-r7. 28.5.5.9.4 condition flags this instruction: ? updates the n and z flags according to the result ? does not affect the c or v flags. 28.5.5.9.5 examples tst r0, r1 ; perform bitwise and of r0 value and r1 value, ; condition code flags are updated but result is discarded 28.5.6 branch and control instructions table 437 shows the branch and control instructions: table 437. branch and control instructions mnemonic brief description see b{cc} branch {conditionally} section 28C28.5.6.1
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 493 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference 28.5.6.1 b, bl, bx, and blx branch instructions. 28.5.6.1.1 syntax b{ cond } label bl label bx rm blx rm where: cond is an optional condition code, see section 28C28.5.3.6 . label is a pc-relative expression. see section 28C28.5.3.5 . rm is a register providing the address to branch to. 28.5.6.1.2 operation all these instructions cause a bran ch to the address indicated by label or contained in the register specified by rm . in addition: ? the bl and blx instructions write the addres s of the next instruction to lr, the link register r14. ? the bx and blx instructions result in a hardfault exception if bit[0] of rm is 0. bl and blx instructions also set bit[0] of the lr to 1. this ensures that the value is suitable for use by a subsequent pop {pc} or bx instruction to perform a successful return branch. table 438 shows the ranges for the various branch instructions. 28.5.6.1.3 restrictions in these instructions: ? do not use sp or pc in the bx or blx instruction. bl branch with link section 28C28.5.6.1 blx branch indirect with link section 28C28.5.6.1 bx branch indirect section 28C28.5.6.1 table 437. branch and control instructions mnemonic brief description see table 438. branch ranges instruction branch range b label ? 2 kb to +2 kb bcond label ? 256 bytes to +254 bytes bl label ? 16 mb to +16 mb bx rm any value in register blx rm any value in register
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 494 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference ? for bx and blx, bit[0] of rm must be 1 for correct executio n. bit[0] is used to update the epsr t-bit and is discarde d from the target address. remark: b cond is the only conditional instruction on the cortex-m0 processor. 28.5.6.1.4 condition flags these instructions do not change the flags. 28.5.6.1.5 examples b loopa ; branch to loopa bl func ; branch with link (call) to function func, return address ; stored in lr bx lr ; return from function call blx r0 ; branch with link and exchange (call) to a address stored ; in r0 beq labeld ; conditionally branch to labeld if last flag setting ; instruction set the z flag, else do not branch. 28.5.7 miscellaneous instructions table 439 shows the remaining cortex-m0 instructions: table 439. miscellaneous instructions mnemonic brief description see bkpt breakpoint section 28C28.5.7. 1 cpsid change processor state, disable interrupts section 28C28.5.7. 2 cpsie change processor state, enable interrupts section 28C28.5.7. 2 dmb data memory barrier section 28C28.5.7. 3 dsb data synchronization barrier section 28C28.5.7. 4 isb instruction synchronization barrier section 28C28.5.7. 5 mrs move from special register to register section 28C28.5.7. 6 msr move from register to special register section 28C28.5.7. 7 nop no operation section 28C28.5.7. 8 sev send event section 28C28.5.7. 9
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 495 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference 28.5.7.1 bkpt breakpoint. 28.5.7.1.1 syntax bkpt # imm where: imm is an integer in the range 0-255. 28.5.7.1.2 operation the bkpt instruction causes the processor to enter debug state. debug tools can use this to investigate system state when the in struction at a particular address is reached. imm is ignored by the processor. if required, a debugger can use it to store additional information about the breakpoint. the processor might also produce a hardfault or go in to lockup if a debugger is not attached when a bkpt instruction is executed. see section 28C28.4.4.1 for more information. 28.5.7.1.3 restrictions there are no restrictions. 28.5.7.1.4 condition flags this instruction does not change the flags. 28.5.7.1.5 examples bkpt #0 ; breakpoint with immediate value set to 0x0. 28.5.7.2 cps change processor state. 28.5.7.2.1 syntax cpsid i cpsie i 28.5.7.2.2 operation cps changes the primask specia l register values. cpsid ca uses interrupts to be disabled by setting primask. cpsie cause interrupts to be enabled by clearing primask.see section 28C28.4.1.3.6 for more information about these registers. svc supervisor call section 28C28.5.7. 10 wfe wait for event section 28C28.5.7. 11 wfi wait for interrupt section 28C28.5.7. 12 table 439. miscellaneous instructions mnemonic brief description see
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 496 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference 28.5.7.2.3 restrictions there are no restrictions. 28.5.7.2.4 condition flags this instruction does not change the condition flags. 28.5.7.2.5 examples cpsid i ; disable all interrupts except nmi (set primask) cpsie i ; enable interrupts (clear primask) 28.5.7.3 dmb data memory barrier. 28.5.7.3.1 syntax dmb 28.5.7.3.2 operation dmb acts as a data memory barrier. it ensures that all explicit memory accesses that appear in program order before the dmb instruction are observed before any explicit memory accesses that appear in program orde r after the dmb instruction. dmb does not affect the ordering of instructions that do not access memory. 28.5.7.3.3 restrictions there are no restrictions. 28.5.7.3.4 condition flags this instruction does not change the flags. 28.5.7.3.5 examples dmb ; data memory barrier 28.5.7.4 dsb data synchronization barrier. 28.5.7.4.1 syntax dsb 28.5.7.4.2 operation dsb acts as a special data synchronization me mory barrier. instructions that come after the dsb, in program order, do not execute until the dsb instruction completes. the dsb instruction completes when all explicit memory access es before it complete. 28.5.7.4.3 restrictions there are no restrictions.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 497 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference 28.5.7.4.4 condition flags this instruction does not change the flags. 28.5.7.4.5 examples dsb ; data synchronisation barrier 28.5.7.5 isb instruction synchronization barrier. 28.5.7.5.1 syntax isb 28.5.7.5.2 operation isb acts as an instruction synchronization barrier. it flushes the pipeline of the processor, so that all instructions following the isb are fetched from cache or memory again, after the isb instruction has been completed. 28.5.7.5.3 restrictions there are no restrictions. 28.5.7.5.4 condition flags this instruction does not change the flags. 28.5.7.5.5 examples isb ; instruction synchronisation barrier 28.5.7.6 mrs move the contents of a special regi ster to a general-purpose register. 28.5.7.6.1 syntax mrs rd , spec_reg where: rd is the general-purpose destination register. spec_reg is one of the special- purpose registers: apsr, ipsr, epsr, iepsr, iapsr, eapsr, psr, msp, psp, primask, or control. 28.5.7.6.2 operation mrs stores the contents of a special-purpose register to a general-purpose register. the mrs instruction can be combined with the mr instruction to produce read-modify-write sequences, which are suitable for modifying a specific flag in the psr. see section 28C28.5.7.7 . 28.5.7.6.3 restrictions in this instruction, rd must not be sp or pc.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 498 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference 28.5.7.6.4 condition flags this instruction does not change the flags. 28.5.7.6.5 examples mrs r0, primask ; read primask value and write it to r0 28.5.7.7 msr move the contents of a general-purpose regi ster into the specif ied special register. 28.5.7.7.1 syntax msr spec_reg , rn where: rn is the general-purpose source register. spec_reg is the special- purpose destination regist er: apsr, ipsr, epsr, iepsr, iapsr, eapsr, psr, msp, psp , primask, or control. 28.5.7.7.2 operation msr updates one of the special registers with the value from the register specified by rn . see section 28C28.5.7.6 . 28.5.7.7.3 restrictions in this instruction, rn must not be sp and must not be pc. 28.5.7.7.4 condition flags this instruction updates the flags explicitly based on the value in rn . 28.5.7.7.5 examples msr control, r1 ; read r1 value and write it to the control register 28.5.7.8 nop no operation. 28.5.7.8.1 syntax nop 28.5.7.8.2 operation nop performs no operation and is not guaran teed to be time consuming. the processor might remove it from the pipeline bef ore it reaches the execution stage. use nop for padding, for example to place the subsequent instructions on a 64-bit boundary. 28.5.7.8.3 restrictions there are no restrictions.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 499 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference 28.5.7.8.4 condition flags this instruction does not change the flags. 28.5.7.8.5 examples nop ; no operation 28.5.7.9 sev send event. 28.5.7.9.1 syntax sev 28.5.7.9.2 operation sev causes an event to be si gnaled to all processors wi thin a multipro cessor system. it also sets the local event register, see section 28C28.4.5 . see also section 28C28.5.7.11 . 28.5.7.9.3 restrictions there are no restrictions. 28.5.7.9.4 condition flags this instruction does not change the flags. 28.5.7.9.5 examples sev ; send event 28.5.7.10 svc supervisor call. 28.5.7.10.1 syntax svc # imm where: imm is an integer in the range 0-255. 28.5.7.10.2 operation the svc instruction causes the svc exception. imm is ignored by the processor. if required, it can be retrieved by the exception handler to determine what service is being requested. 28.5.7.10.3 restrictions there are no restrictions. 28.5.7.10.4 condition flags this instruction does not change the flags.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 500 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference 28.5.7.10.5 examples svc #0x32 ; supervisor call (svc handler can extract the immediate value ; by locating it via the stacked pc) 28.5.7.11 wfe wait for event. remark: the wfe instruction is not implemented on the lpc111x/lpc11cxx 28.5.7.11.1 syntax wfe 28.5.7.11.2 operation if the event register is 0, wfe suspends execution until one of the following events occurs: ? an exception, unless masked by the exceptio n mask registers or the current priority level ? an exception enters the pending state, if sevonpend in the system control register is set ? a debug entry request, if debug is enabled ? an event signaled by a peripheral or anot her processor in a multiprocessor system using the sev instruction. if the event register is 1, wfe clears it to 0 and completes immediately. for more information see section 28C28.4.5 . remark: wfe is intended for power saving only. when writing software assume that wfe might behave as nop. 28.5.7.11.3 restrictions there are no restrictions. 28.5.7.11.4 condition flags this instruction does not change the flags. 28.5.7.11.5 examples wfe ; wait for event 28.5.7.12 wfi wait for interrupt. 28.5.7.12.1 syntax wfi
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 501 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference 28.5.7.12.2 operation wfi suspends execution until one of the following events occurs: ? an exception ? an interrupt becomes pending which would preempt if primask was clear ? a debug entry request, regardless of whether debug is enabled. remark: wfi is intended for power saving only. wh en writing software assume that wfi might behave as a nop operation. 28.5.7.12.3 restrictions there are no restrictions. 28.5.7.12.4 condition flags this instruction does not change the flags. 28.5.7.12.5 examples wfi ; wait for interrupt 28.6 peripherals 28.6.1 about the arm cortex-m0 the address map of the private peripheral bus (ppb) is: in register descriptions, the register type is described as follows: rw ? read and write. ro ? read-only. wo ? write-only. 28.6.2 nested vectored interrupt controller this section describes the nested vectored interrupt controller (nvic) and the registers it uses. the nvic supports: ? 32 interrupts. table 440. core peripheral register regions address core peripheral description 0xe000e008 - 0xe000e00f system control block table 28C449 0xe000e010 - 0xe000e01f system timer table 28C458 0xe000e100 - 0xe000e4ef nested vectored interrupt controller table 28C441 0xe000ed00 - 0xe000ed3f system control block table 28C449 0xe000ef00 - 0xe000ef03 nested vectored interrupt controller table 28C441
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 502 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference ? a programmable priority level of 0-3 for each interrupt. a higher level corresponds to a lower priority, so level 0 is the highest interrupt priority. ? level and pulse detection of interrupt signals. ? interrupt tail-chaining. ? an external non-maskable interrupt (nmi). see section 28.1 for implementation of the nmi for specific parts. the processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead. th is provides low latency exception handling. the hardware implementation of the nvic registers is: 28.6.2.1 accessing the cortex-m0 nvic registers using cmsis cmsis functions enable software portability between different cortex-m profile processors. to access the nvic registers when usin g cmsis, use the following functions: [1] the input parameter irqn is the irq number, see table 428 for more information. 28.6.2.2 interrupt set-enable register the iser enables interrupts, and shows which interrupts are enabled. see the register summary in table 441 for the register attributes. the bit assignments are: table 441. nvic register summary address name type reset value description 0xe000e100 iser rw 0x00000000 section 28C28.6.2.2 0xe000e180 icer rw 0x00000000 section 28C28.6.2.3 0xe000e200 ispr rw 0x00000000 section 28C28.6.2.4 0xe000e280 icpr rw 0x00000000 section 28C28.6.2.5 0xe000e400 - 0xe 000e41c ipr0-7 rw 0x00000000 section 28C28.6.2.6 table 442. cmisis access nvic functions cmsis function description void nvic_enableirq(irqn_type irqn) [1] enables an interrupt or exception. void nvic_disableirq(irqn_type irqn) [1] disables an interrupt or exception. void nvic_setpendingirq(irqn_type irqn) [1] sets the pending status of interrupt or exception to 1. void nvic_clearpendingirq(irqn_type irqn) [1] clears the pending status of interrupt or exception to 0. uint32_t nvic_getpendi ngirq(irqn_type irqn) [1] reads the pending status of interrupt or exception. this function returns non-zero value if the pending status is set to 1. void nvic_setpriority(irqn_type irqn, uint32_t priority) [1] sets the priority of an interrupt or exception with configurable priority level to 1. uint32_t nvic_getpriority(irqn_type irqn) [1] reads the priority of an interrupt or exception with configurable priority level. this function re turns the current priority level.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 503 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference if a pending interrupt is enabled, the nvic activa tes the interrupt based on its priority. if an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the nvic never activates th e interrupt, regardless of its priority. 28.6.2.3 interrupt clear-enable register the icer disables interrupts, and show whic h interrupts are enabled. see the register summary in table 28C441 for the register attributes. the bit assignments are: 28.6.2.4 interrupt set-pending register the ispr forces interrupts into the pending state, and shows which interrupts are pending. see the register summary in table 28C441 for the regist er attributes. the bit assignments are: remark: writing 1 to the ispr bit corresponding to: ? an interrupt that is pending has no effect table 443. iser bit assignments bits name function [31:0] setena interrupt set-enable bits. write: 0 = no effect 1 = enable interrupt. read: 0 = interrupt disabled 1 = interrupt enabled. table 444. icer bit assignments bits name function [31:0] clrena interrupt clear-enable bits. write: 0 = no effect 1 = disable interrupt. read: 0 = interrupt disabled 1 = interrupt enabled. table 445. ispr bit assignments bits name function [31:0] setpend interrupt set-pending bits. write: 0 = no effect 1 = changes interrupt state to pending. read: 0 = interrupt is not pending 1 = interrupt is pending.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 504 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference ? a disabled interrupt sets the state of that interrupt to pending. 28.6.2.5 interrupt clear-pending register the icpr removes the pending state from interrupts, and shows which interrupts are pending. see the register summary in table 28C441 for the regist er attributes. the bit assignments are: remark: writing 1 to an icpr bit does not affect the active state of the corresponding interrupt. 28.6.2.6 interrupt priority registers the ipr0-ipr7 registers provide an 2-bit priori ty field for each interrupt. these registers are only word-accessible. see the register summary in table 28C441 for their attributes. each register holds four priority fields as shown: table 446. icpr bit assignments bits name function [31:0] clrpend interrupt clear-pending bits. write: 0 = no effect 1 = removes pending state an interrupt. read: 0 = interrupt is not pending 1 = interrupt is pending. fig 107. ipr register 35,b 35,b 35,b 35,b ,35 35,bq 35,bq 35,bq 35,bq ,35q 35,b 35,b 35,b 35,b ,35 table 447. ipr bit assignments bits name function [31:24] priority, byte offset 3 each priority fi eld holds a priority value, 0-3. the lower the value, the greater the priority of the corresponding interrupt. the processor implements only bits[7:6] of each field, bits [5:0] read as zero and ignore writes. [23:16] priority, byte offset 2 [15:8] priority, byte offset 1 [7:0] priority, byte offset 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 505 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference see section 28C28.6.2.1 for more information about the a ccess to the interrupt priority array, which provides the software view of the interrupt priorities. find the ipr number and byte offset for interrupt m as follows: ? the corresponding ipr number, n , is given by n = n div 4 ? the byte offset of the required pr iority field in this register is m mod 4, where: ? byte offset 0 refers to register bits[7:0] ? byte offset 1 refers to register bits[15:8] ? byte offset 2 refers to register bits[23:16] ? byte offset 3 refers to register bits[31:24]. 28.6.2.7 level-sensitive and pulse interrupts the processor supports both level-sensitive and pulse interrupts. pulse interrupts are also described as edge-triggered interrupts. a level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. typically this happens because the isr accesses the peripheral, causing it to clear the interrupt request. a pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor clock. to en sure the nvic detects the interrupt, the peripheral must assert the interrupt signal for at least one clock cycle, during which the nvic detects the pulse and latches the interrupt. when the processor enters the isr, it auto matically removes the pending state from the interrupt, see section 28.6.2.7.1 . for a level-sensitive interrupt, if the signal is not deasserted before the processor returns from the isr, the interrupt becomes pending again, and the processor must execute its isr again. this means that the peripheral can hold the interrupt signal asserted until it no longer needs servicing. 28.6.2.7.1 hardware and software control of interrupts the cortex-m0 latches all interrupts. a peripheral interrupt becomes pending for one of the following reasons: ? the nvic detects that the interrupt signal is active and the corresponding interrupt is not active ? the nvic detects a rising edge on the interrupt signal ? software writes to the corresponding interrupt set-pending register bit, see section 28C28.6.2.4 . a pending interrupt remains pending until one of the following: ? the processor enters the isr for the interrupt. this changes the state of the interrupt from pending to active. then: ? for a level-sensitive interrupt, when the pr ocessor returns from the isr, the nvic samples the interrupt signal. if the signal is asserted, the state of the interrupt changes to pending, which might cause th e processor to immedi ately re-enter the isr. otherwise, the state of th e interrupt changes to inactive.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 506 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference ? for a pulse interrupt, the nvic continues to monitor the interrupt signal, and if this is pulsed the state of the interrupt changes to pending and active. in this case, when the processor returns from the isr the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the isr. if the interrupt signal is not pulsed while the processor is in the isr, when the processor returns from the isr the state of the interrupt changes to inactive. ? software writes to the corresponding interrupt clear-pending register bit. for a level-sensitive interrupt, if the interrupt signal is still asserted, t he state of the interrupt does not change. otherwise, the st ate of the interrupt changes to inactive. for a pulse interrupt, state of the interrupt changes to: ? inactive, if the state was pending ? active, if the state was active and pending. 28.6.2.8 nvic usage hints and tips ensure software uses correctly aligned register accesses. the processor does not support unaligned accesses to nvic registers. an interrupt can enter pending state even if it is disabled. disabling an interrupt only prevents the processor from taking that interrupt. 28.6.2.8.1 nvic programming hints software uses the cpsie i and cpsid i instructions to enable and disable interrupts. the cmsis provides the following intrinsic functions for these instructions: void __disable_irq(void) // disable interrupts void __enable_irq(void) // enable interrupts in addition, the cmsis provides a number of functions for nvic control, including: the input parameter irqn is the irq number, see table 28C428 for more information. for more information about these functi ons, see the cmsis documentation. 28.6.3 system control block the system control block (scb) provides system implementation information, and system control. this includes configuratio n, control, and reporting of the system exceptions. the scb registers are: table 448. cmsis functi ons for nvic control cmsis interrupt control function description void nvic_enableirq(irqn_t irqn) enable irqn void nvic_disableirq(irqn_t irqn) disable irqn uint32_t nvic_getpendingirq (irqn_t irqn) return true (1) if irqn is pending void nvic_setpendingirq (irqn_t irqn) set irqn pending void nvic_clearpendingirq (irqn_t irqn) clear irqn pending status void nvic_setpriority (irqn_t irqn, uint32_t priority) set priority for irqn uint32_t nvic_getpriority (irqn_t irqn) read priority of irqn void nvic_systemreset (void) reset the system
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 507 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference [1] see the register description for more information. 28.6.3.1 the cmsis mapping of the cortex-m0 scb registers to improve software efficiency, the cmsis simp lifies the scb register presentation. in the cmsis, the array shp[1] corresponds to the registers shpr2-shpr3. 28.6.3.2 cpuid register the cpuid register contains the processor part number, version, and implementation information. see the register summary in for its attributes. the bit assignments are: 28.6.3.3 interrupt control and state register the icsr: ? provides: ? a set-pending bit for the non-maskable interrupt (nmi) exception ? set-pending and clear-pending bits for the pendsv and systick exceptions ? indicates: ? the exception number of the exception being processed ? whether there are preempted active exceptions ? the exception number of the highest priority pending exception table 449. summary of the scb registers address name type reset value description 0xe000ed00 cpuid ro 0x410cc200 section 28.6.3.2 0xe000ed04 icsr rw [1] 0x00000000 section 28C28.6.3.3 0xe000ed0c aircr rw [1] 0xfa050000 section 28C28.6.3.4 0xe000ed10 scr rw 0x00000000 section 28C28.6.3.5 0xe000ed14 ccr ro 0x00000204 section 28C28.6.3.6 0xe000ed1c shpr2 rw 0x00000000 section 28C28.6.3.7.1 0xe000ed20 shpr3 rw 0x00000000 section 28C28.6.3.7.2 table 450. cpuid register bit assignments bits name function [31:24] implementer implementer code: 0x41 = arm [23:20] variant variant number, the r value in the r n p n product revision identifier: 0x0 = revision 0 [19:16] constant constant that defines the architecture of the processor:, reads as 0xc = armv6-m architecture [15:4] partno part number of the processor: 0xc20 = cortex-m0 [3:0] revision revision number, the p value in the r n p n product revision identifier: 0x0 = patch 0
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 508 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference ? whether any interrupts are pending. see the register summary in table 28C449 for the icsr attributes. the bit assignments are: table 451. icsr bit assignments bits name type function [31] nmipendset [2] rw nmi set-pending bit. write: 0 = no effect 1 = changes nmi exception state to pending. read: 0 = nmi exception is not pending 1 = nmi exception is pending. because nmi is the highest-priority exception, normally the processor enters the nmi exception handler as soon as it detects a write of 1 to this bit. entering the handler then clears this bit to 0. this means a read of this bit by the nmi exception handler returns 1 only if the nmi signal is reasserted while the processor is executing that handler. [30:29] - - reserved. [28] pendsvset rw pendsv set-pending bit. write: 0 = no effect 1 = changes pendsv exception state to pending. read: 0 = pendsv exception is not pending 1 = pendsv exception is pending. writing 1 to this bit is the only way to set the pendsv exception state to pending. [27] pendsvclr wo pendsv clear-pending bit. write: 0 = no effect 1 = removes the pending state from the pendsv exception. [26] pendstset rw systick exception set-pending bit. write: 0 = no effect 1 = changes systick exception state to pending. read: 0 = systick exception is not pending 1 = systick exception is pending.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 509 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference [1] this is the same value as ipsr bits[5:0], see table 28C423 . [2] see section 28.1 for implementation of the nmi for specific parts. when you write to the icsr, the effect is unpredictable if you: ? write 1 to the pendsvset bit and write 1 to the pendsvclr bit ? write 1 to the pendstset bit and write 1 to the pendstclr bit. 28.6.3.4 application interrupt and reset control register the aircr provides endian status for data ac cesses and reset control of the system. see the register summary in table 28C449 and table 28C452 for its attributes. to write to this register, you must write 0x05fa to the vectkey field, otherwise the processor ignores the write. the bit assignments are: [25] pendstclr wo systick exception clear-pending bit. write: 0 = no effect 1 = removes the pending state from the systick exception. this bit is wo. on a register read its value is unknown. [24:23] - - reserved. [22] isrpending ro interrupt pending flag, excluding nmi and faults: 0 = interrupt not pending 1 = interrupt pending. [21:18] - - reserved. [17:12] vectpending ro indicates the exce ption number of the highest priority pending enabled exception: 0 = no pending exceptions nonzero = the exception numbe r of the highest priority pending enabled exception. [11:6] - - reserved. [5:0] vectactive [1] ro contains the active exception number: 0 = thread mode nonzero = the exception number [1] of the currently active exception. remark: subtract 16 from this value to obtain the cmsis irq number that identifies the corresponding bit in the interrupt clear -enable, set-enable, clear-pending, set-pending, and priority register, see table 28C423 . table 451. icsr bit assignments bits name type function
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 510 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference 28.6.3.5 system control register the scr controls features of entry to and ex it from low power state. see the register summary in table 28C449 for its attributes. the bit assignments are: table 452. aircr bit assignments bits name type function [31:16] read: reserved write: vectkey rw register key: reads as unknown on writes, write 0x05fa to vectkey, otherwise the write is ignored. [15] endianess ro data endianness implemented: 0 = little-endian 1 = big-endian. [14:3] - - reserved [2] sysresetreq wo system reset request: 0 = no effect 1 = requests a system level reset. this bit reads as 0. [1] vectclractive wo reserved for debug use. this bit reads as 0. when writing to the register you must write 0 to this bit, otherwise behavior is unpredictable. [0] - - reserved. table 453. scr bit assignments bits name function [31:5] - reserved. [4] sevonpend send ev ent on pending bit: 0 = only enabled interrupts or events can wake-up the processor, disabled interrupts are excluded 1 = enabled events and all interrupts, including disabled interrupts, can wake-up the processor. when an event or interrupt enter s pending state, the event signal wakes up the processor from wfe. if the processor is not waiting for an event, the event is registered and affects the next wfe. the processor also wakes up on execution of an sev instruction. [3] - reserved. [2] sleepdeep controls whether the processor uses sleep or deep sleep as its low power mode: 0 = sleep 1 = deep sleep. [1] sleeponexit indicates slee p-on-exit when returning fr om handler mode to thread mode: 0 = do not sleep when returning to thread mode. 1 = enter sleep, or deep sleep, on return from an isr to thread mode. setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. [0] - reserved.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 511 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference 28.6.3.6 configuration and control register the ccr is a read-only register and indicates some aspects of the behavior of the cortex-m0 processor. see the register summary in table 28C449 for the ccr attributes. the bit assignments are: 28.6.3.7 system handler priority registers the shpr2-shpr3 registers set the priority leve l, 0 to 3, of the exception handlers that have configurable priority. shpr2-shpr3 are word accessible. see the register summary in table 28C449 for their attributes. to access to the system exception priority level using cmsis, use the following cmsis functions: ? uint32_t nvic_getpriority(irqn_type irqn) ? void nvic_setpriority(irqn_type irqn, uint32_t priority) the input parameter irqn is the irq number, see table 28C428 for more information. the system fault handlers, and the priority field and register for each handler are: each pri_n field is 8 bits wide, but the processor implements only bits[7:6] of each field, and bits[5:0] read as zero and ignore writes. 28.6.3.7.1 system handler priority register 2 the bit assignments are: table 454. ccr bit assignments bits name function [31:10] - reserved. [9] stkalign always reads as one, indicates 8-byte stack alignment on exception entry. on exception entry, the processor uses bit[9] of the stacked psr to indicate the stack alignment. on return from the exception it uses this stacked bit to restore the correct stack alignment. [8:4] - reserved. [3] unalign_trp always reads as one, indicates that all unaligned accesses generate a hardfault. [2:0] - reserved. table 455. system fault handler priority fields handler field register description svcall pri_11 section 28C28.6.3.7.1 pendsv pri_14 section 28C28.6.3.7.2 systick pri_15
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 512 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference 28.6.3.7.2 system handler priority register 3 the bit assignments are: 28.6.3.8 scb usage hints and tips ensure software uses aligned 32-bit word size transactions to access all the scb registers. 28.6.4 system timer, systick when enabled, the timer coun ts down from the current value (syst_cvr) to zero, reloads (wraps) to the value in the systic k reload value register (syst_rvr) on the next clock edge, then decrements on subsequent clocks. when the counter transitions to zero, the countflag status bit is set to 1. the countflag bit clears on reads. remark: the syst_cvr value is unknown on re set. software should write to the register to clear it to zero before enabling the feature. this ensures the timer will count from the syst_rvr value rather than an arbitrary value when it is enabled. remark: if the syst_rvr is zero, the timer will be maintained with a current value of zero after it is reloaded with this value. th is mechanism can be used to disable the feature independently from the timer enable bit. a write to the syst_cvr will clear the regist er and the countflag status bit. the write causes the syst_cvr to reload from the syst_rvr on the next timer clock, however, it does not trigger the systick exception logic. on a read, the current value is the value of the register at the time the register is accessed. remark: when the processor is halted for debu gging the counter does not decrement. the system timer registers are: [1] systick calibration value. table 456. shpr2 register bit assignments bits name function [31:24] pri_11 priority of system handler 11, svcall [23:0] - reserved table 457. shpr3 register bit assignments bits name function [31:24] pri_15 priority of system handler 15, systick exception [23:16] pri_14 priority of system handler 14, pendsv [15:0] - reserved table 458. system timer registers summary address name type reset value description 0xe000e010 syst_csr rw 0x00000000 section 28.6.4.1 0xe000e014 syst_rvr rw unknown section 28C28.6.4.2 0xe000e018 syst_cvr rw unknown section 28C28.6.4.3 0xe000e01c syst_calib ro 0x00000004 [1] section 28C28.6.4.4
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 513 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference 28.6.4.1 systick control and status register the syst_csr enables the systick features. see the register summary in for its attributes. the bit assignments are: 28.6.4.2 systick reload value register the syst_rvr specifies the start value to load into the syst_cvr . see the register summary in table 28C458 for its attributes. the bit assignments are: 28.6.4.2.1 calculating the reload value the reload value can be any value in the range 0x00000001 - 0x00ffffff . you can program a value of 0, but this has no effect bec ause the systick exception request and countflag are activated when counting from 1 to 0. to generate a multi-shot timer with a period of n processor clock cycles, use a reload value of n-1. for example, if the systick in terrupt is required every 100 clock pulses, set reload to 99. 28.6.4.3 systick current value register the syst_cvr contains the current value of the systick counter. see the register summary in table 28C458 for its attributes. the bit assignments are: table 459. syst_csr bit assignments bits name function [31:17] - reserved. [16] countflag returns 1 if timer counted to 0 since the last read of this register. [15:3] - reserved. [2] clksource selects the systick timer clock source: 0 = external reference clock. 1 = processor clock. [1] tickint enables systick exception request: 0 = counting down to zero does not assert the systick exception request. 1 = counting down to zero assert s the systick exception request. [0] enable enables the counter: 0 = counter disabled. 1 = counter enabled. table 460. syst_rvr bit assignments bits name function [31:24] - reserved. [23:0] reload value to load into the syst_cvr when the counter is enabled and when it reaches 0, see section 28.6.4.2.1 .
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 514 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference 28.6.4.4 systick calibration value register the syst_calib register indicates the systic k calibration properties. see the register summary in table 28C458 for its attributes. the bit assignments are: if calibration information is not known, calculate the calibration value required from the frequency of the processor clock or external clock. 28.6.4.5 systick usage hints and tips the interrupt controller clock up dates the systick co unter. if this clock signal is stopped for low power mode, the systick counter stops. ensure software uses word accesse s to access the systick registers. if the systick counter reload and current value are undefined at reset, the correct initialization sequence fo r the systick counter is: 1. program reload value. 2. clear current value. 3. program control and status register. table 461. syst_cvr bit assignments bits name function [31:24] - reserved. [23:0] current reads return the current value of the systick counter. a write of any value clears the field to 0, and also clears the syst_csr.countflag bit to 0. table 462. syst_calib register bit assignments bits name function [31] noref reads as one. indicates that no separate reference clock is provided. [30] skew reads as one. calibration value for the 10ms inexact timing is not known because tenms is not known. this can affect the suitability of systick as a software real time clock. [29:24] - reserved. [23:0] tenms reads as zero. indicate s calibration value is not known.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 515 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference 28.7 cortex-m0 instruction summary table 463. cortex m0- instruction summary operation description assembler cycles move 8-bit immediate movs rd, # 1 lo to lo movs rd, rm 1 any to any mov rd, rm 1 any to pc mov pc, rm 3 add 3-bit immediate adds rd, rn, # 1 all registers lo adds rd, rn, rm 1 any to any add rd, rd, rm 1 any to pc add pc, pc, rm 3 add 8-bit immediate adds rd, rd, # 1 with carry adcs rd, rd, rm 1 immediate to sp add sp, sp, # 1 form address from sp add rd, sp, # 1 form address from pc adr rd, 1 subtract lo and lo subs rd, rn, rm 1 3-bit immediate subs rd, rn, # 1 8-bit immediate subs rd, rd, # 1 with carry sbcs rd, rd, rm 1 immediate from sp sub sp, sp, # 1 negate rsbs rd, rn, #0 1 multiply multiply muls rd, rm, rd 1 compare compare cmp rn, rm 1 negative cmn rn, rm 1 immediate cmp rn, # 1 logical and ands rd, rd, rm 1 exclusive or eors rd, rd, rm 1 or orrs rd, rd, rm 1 bit clear bics rd, rd, rm 1 move not mvns rd, rm 1 and test tst rn, rm 1 shift logical shift left by immediate lsls rd, rm, # 1 logical shift left by register lsls rd, rd, rs 1 logical shift right by immediate lsrs rd, rm, # 1 logical shift right by register lsrs rd, rd, rs 1 arithmetic shift right asrs rd, rm, # 1 arithmetic shift right by register asrs rd, rd, rs 1 rotate rotate right by register rors rd, rd, rs 1
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 516 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference load word, immediate offset ldr rd, [rn, #] 2 halfword, immediate offset ldrh rd, [rn, #] 2 byte, immediate offset ldrb rd, [rn, #] 2 word, register offset ldr rd, [rn, rm] 2 halfword, register offset ldrh rd, [rn, rm] 2 signed halfword, register offset ldrsh rd, [rn, rm] 2 byte, register offset ldrb rd, [rn, rm] 2 signed byte, register offset ldrsb rd, [rn, rm] 2 pc-relative ldr rd, 2 sp-relative ldr rd, [sp, #] 2 multiple, excluding base ldm rn!, {} 1 + n [1] multiple, including base ldm rn, {} 1 + n [1] store word, immediate offset str rd, [rn, #] 2 store halfword, immediate offset strh rd, [rn, #] 2 byte, immediate offset strb rd, [rn, #] 2 word, register offset str rd, [rn, rm] 2 halfword, register offset strh rd, [rn, rm] 2 byte, register offset strb rd, [rn, rm] 2 sp-relative str rd, [sp, #] 2 multiple stm rn!, {} 1 + n [1] push push push {} 1 + n [1] push with link register push {, lr} 1 + n [1] pop pop pop {} 1 + n [1] pop and return pop {, pc} 4 + n [2] branch conditional b 1 or 3 [3] unconditional b 3 with link bl 4 with exchange bx rm 3 with link and exchange blx rm 3 extend signed halfword to word sxth rd, rm 1 signed byte to word sxtb rd, rm 1 unsigned halfword uxth rd, rm 1 unsigned byte uxtb rd, rm 1 reverse bytes in word rev rd, rm 1 bytes in both halfwords rev16 rd, rm 1 signed bottom half word revsh rd, rm 1 state change supervisor call svc - [4] disable interrupts cpsid i 1 enable interrupts cpsie i 1 read special register mrs rd, 4 write special register msr , rn 4 table 463. cortex m0- instruction summary operation description assembler cycles
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 517 of 543 nxp semiconductors um10398 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference [1] n is the number of elements. [2] n is the number of elements in the sta ck-pop list including pc and assumes load or store does not generate a hardfault exception. [3] 3 if taken, 1 if not taken. [4] cycle count depends on core and debug configuration. [5] excludes time spend waiting for an interrupt or event. [6] executes as nop. hint send event sev 1 wait for event wfe 2 [5] wait for interrupt wfi 2 [5] yield yield [6] 1 no operation nop 1 barriers instruction synchronization isb 4 data memory dmb 4 data synchronization dsb 4 table 463. cortex m0- instruction summary operation description assembler cycles
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 518 of 543 29.1 abbreviations 29.2 references [1] arm dui 0497a ? cortex-m0 devices generic user guide [2] arm ddi 0432c ? cortex-m0 revision r0p0 technical reference manual [3] pcf8576d ? pcf8576d data sheet. um10398 chapter 29: supplementary information rev. 12.1 ? 7 august 2013 user manual table 464. abbreviations acronym description adc analog-to-digital converter ahb advanced high-performance bus amba advanced microcontroller bus architecture apb advanced peripheral bus bod brownout detection gpio general purpose input/output pll phase-locked loop spi serial peripheral interface ssi serial synchronous interface ttl transistor-transistor logic uart universal asynchronous receiver/transmitter
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 519 of 543 nxp semiconductors um10398 chapter 29: supplementary information 29.3 legal information 29.3.1 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. 29.3.2 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customers sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customers applications and products planned, as well as fo r the planned application and use of customers third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customers applications or products, or the application or use by customers third party customer(s). customer is responsible for doing all necessary testing for the customers applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customers third party customer(s). nxp does not accept any liability in this respect. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from competent authorities. 29.3.3 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v.
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 520 of 543 nxp semiconductors um10398 chapter 29: supplementary information 29.4 tables table 1. lpc111x/lpc11cxx feature changes. . . . . . . . .5 table 2. ordering information . . . . . . . . . . . . . . . . . . . . .8 table 3. ordering options . . . . . . . . . . . . . . . . . . . . . . .10 table 4. lpc111x memory configuration . . . . . . . . . . . .17 table 5. lpc11cxx memory configuration . . . . . . . . . . .17 table 6. pin summary. . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 7. register overview: system control block (base address 0x4004 8000) . . . . . . . . . . . . . . . . . .22 table 8. system memory remap register (sysmemremap, address 0x4004 8000) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 9. peripheral reset control register (presetctrl, address 0x4004 8004) bit description. . . . . . . .25 table 10. system pll cont rol register (syspllctrl, address 0x4004 8008) bit description . . . . . . .25 table 11. system pll status register (syspllstat, address 0x4004 800c) bit description . . . . . . .26 table 12. system oscillator co ntrol register (sysoscctrl, address 0x4004 8020) bit description. . . . . . . .26 table 13. watchdog oscillator control register (wdtoscctrl, address 0x4004 8024) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 14. internal resonant crystal control register (ircctrl, address 0x4004 8028) bit description 27 table 15. system reset stat us register (sysrststat, address 0x4004 8030) bit description. . . . . . . .28 table 16. system pll clock source select register (syspllclksel, addre ss 0x4004 8040) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 17. system pll clock source update enable register (syspllclkuen, address 0x4004 8044) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 18. main clock source select register (mainclksel, address 0x4004 8070) bit description. . . . . . . .29 table 19. main clock source update enable register (mainclkuen, address 0x4004 8074) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 20. system ahb clock divider register (sysahbclkdiv, addre ss 0x4004 8078) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 21. system ahb clock control register (sysahbclkctrl, address 0x4004 8080) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 22. spi0 clock divide r register (ssp0clkdiv, address 0x4004 8094) bit description. . . . . . . .32 table 23. uart clock divider register (uartclkdiv, address 0x4004 8098) bit description. . . . . . . .32 table 24. spi1 clock divide r register (ssp1clkdiv, address 0x4004 809c) bit description . . . . . . .33 table 25. wdt clock source se lect register (wdtclksel, address 0x4004 80d0) bit description . . . . . . .33 table 26. wdt clock source update enable register (wdtclkuen, address 0x4004 80d4) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 27. wdt clock divider register (wdtclkdiv, address 0x4004 80d8) bit description . . . . . . . . . . . . . . 34 table 28. clkout clock so urce select register (clkoutclksel, address 0x4004 80e0) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 29. clkout clock source update enable register (clkoutuen, address 0x4004 80e4) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 30. clkout clo ck divider registers (clkoutclkdiv, address 0x4004 80e8) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 31. por captured pio status registers 0 (pioporcap0, address 0x4004 8100) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 32. por captured pio status registers 1 (pioporcap1, address 0x4004 8104) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 33. bod control register (bodctrl, address 0x4004 8150) bit description. . . . . . . . . . . . . . . . . . . . . 36 table 34. system tick timer calibration register (systckcal, addre ss 0x4004 8154) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 35. irq latency register (irqlatency, address 0x4004 8170) bit description . . . . . . . . . . . . . . 37 table 36. nmi source selection register (nmisrc, address 0x4004 8174) bit description . . . . . . . . . . . . . . 37 table 37. start logic edge cont rol register 0 (startaprp0, address 0x4004 8200) bit description . . . . . . 38 table 38. start logic signal enable register 0 (starterp0, address 0x4004 8204) bit description . . . . . . 38 table 39. start logic reset register 0 (startrsrp0clr, address 0x4004 8208) bit description . . . . . . 38 table 40. start logic status register 0 (startsrp0, address 0x4004 820c) bit description . . . . . . 39 table 41. allowed values for pdsleepcfg register . . . 39 table 42. deep-sleep configuration register (pdsleepcfg, address 0x4004 8230) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 43. wake-up configurat ion register (pdawakecfg, address 0x4004 8234) bit description . . . . . . 40 t a b le 44. power-down configuration register (pdruncfg, address 0x4004 8238) bit description . . . . . . 41 table 45. device id register (device_id, address 0x4004 83f4) bit description . . . . . . . . . . . . . . . . . . . . 43 table 46. pll frequency parameters. . . . . . . . . . . . . . . . 52 table 47. pll configuration examples. . . . . . . . . . . . . . . 53 table 48. flash configuration register (flashcfg, address 0x4003 c010) bit description . . . . . . . . . . . . . . 54 table 49. register overview: pmu (base address 0x4003 8000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 50. power control register (pcon, address 0x4003 8000) bit description . . . . . . . . . . . . . . . . . . . . 55 table 51. general purpose registers 0 to 3 (gpreg0 - gpreg3, address 0x4003 8004 to 0x4003 8010) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 52. general purpose r egister 4 (gpreg4, address 0x4003 8014) bit description . . . . . . . . . . . . . 56
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 521 of 543 nxp semiconductors um10398 chapter 29: supplementary information table 53. set_pll routine . . . . . . . . . . . . . . . . . . . . . . . . .60 table 54. set_power routine . . . . . . . . . . . . . . . . . . . . . .64 table 55. connection of interrupt sources to the vectored interrupt controller . . . . . . . . . . . . . . . . . . . . . .66 table 56. register overview: i/o configuration (base address 0x4004 4000) . . . . . . . . . . . . . . . . . . .71 table 57. i/o configuration re gisters ordered by port number 73 table 58. iocon_pio2_6 register (iocon_pio2_6, address 0x4004 4000) bit description . . . . . . .74 table 59. iocon_pio2_0 register (iocon_pio2_0, address 0x4004 4008) bit description . . . . . . .75 table 60. iocon_reset_pio0_0 register (iocon_reset_pio0_0, address 0x4004 400c) bit description. . . . . . . . . . . . . . . . . . . . .75 table 61. iocon_pio0_1 register (iocon_pio0_1, address 0x4004 4010) bit description . . . . . . .76 table 62. iocon_pio1_8 register (iocon_pio1_8, address 0x4004 4014) bit description . . . . . . .77 table 63. iocon_pio0_2 register (iocon_pio0_2, address 0x4004 401c) bit description . . . . . . .77 table 64. iocon_pio2_7 register (iocon_pio2_7, address 0x4004 4020) bit description . . . . . . .78 table 65. iocon_pio2_8 register (iocon_pio2_8, address 0x4004 4024) bit description . . . . . . .78 table 66. iocon_pio2_1 register (iocon_pio2_1, address 0x4004 4028) bit description . . . . . . .79 table 67. iocon_pio0_3 register (iocon_pio0_3, address 0x4004 402c) bit description . . . . . . .80 table 68. iocon_pio0_4 register (iocon_pio0_4, address 0x4004 4030) bit description . . . . . . .80 table 69. iocon_pio0_5 register (iocon_pio0_5, address 0x4004 4034) bit description . . . . . . .81 table 70. iocon_pio1_9 register (iocon_pio1_9, address 0x4004 4038) bit description . . . . . . .81 table 71. iocon_pio3_4 register (iocon_pio3_4, address 0x4004 403c) bit description . . . . . . .82 table 72. iocon_pio2_4 register (iocon_pio2_4, address 0x4004 4040) bit description . . . . . . .82 table 73. iocon_pio2_5 register (iocon_pio2_5, address 0x4004 4044) bit description . . . . . . .83 table 74. iocon_pio3_5 register (iocon_pio3_5, address 0x4004 4048) bit description . . . . . . .83 table 75. iocon_pio0_6 register (iocon_pio0_6, address 0x4004 404c) bit description . . . . . . .84 table 76. iocon_pio0_7 register (iocon_pio0_7, address 0x4004 4050) bit description. . . . . . . .84 table 77. iocon_pio2_9 register (iocon_pio2_9, address 0x4004 4054) bit description . . . . . . .85 table 78. iocon_pio2_10 re gister (iocon_pio2_10, address 0x4004 4058) bit description . . . . . . .86 table 79. iocon_pio2_2 register (iocon_pio2_2, address 0x4004 405c) bit description . . . . . . .86 table 80. iocon_pio0_8 register (iocon_pio0_8, address 0x4004 4060) bit description . . . . . . .87 table 81. iocon_pio0_9 register (iocon_pio0_9, address 0x4004 4064) bit description . . . . . . .87 table 82. iocon_swclk_pio0_10 register (iocon_swclk_pio0_10, address 0x4004 4068) bit description . . . . . . . . . . . . . . . . . . . . 88 table 83. iocon_pio1_10 re gister (iocon_pio1_10, address 0x4004 406c) bit description . . . . . . 89 table 84. iocon_pio2_11 register (iocon_pio2_11, address 0x4004 4070) bit description . . . . . . . 90 table 85. iocon_r_pio0_11 register (iocon_r_pio0_11, address 0x4004 4074) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 86. iocon_r_pio1_0 register (iocon_r_pio1_0, address 0x4004 4078) bit description . . . . . . . 91 table 87. iocon_r_pio1_1 register (iocon_r_pio1_1, address 0x4004 407c) bit description . . . . . . 92 table 88. iocon_r_pio1_2 register (iocon_r_pio1_2, address 0x4004 4080) bit description . . . . . . 92 table 89. iocon_pio3_0 re gister (iocon_pio3_0, address 0x4004 4084) bit description . . . . . . . 93 table 90. iocon_pio3_1 re gister (iocon_pio3_1, address 0x4004 4088) bit description . . . . . . . 94 table 91. iocon_pio2_3 re gister (iocon_pio2_3, address 0x4004 408c) bit description . . . . . . 94 table 92. iocon_swdio_pio1_3 register (iocon_swdio_pio1_3, address 0x4004 4090) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 93. iocon_pio1_4 re gister (iocon_pio1_4, address 0x4004 4094) bit description . . . . . . . 96 table 94. iocon_pio1_11 register (iocon_pio1_11, address 0x4004 4098) bit description . . . . . . 97 table 95. iocon_pio3_2 re gister (iocon_pio3_2, address 0x4004 409c) bit description . . . . . . 97 table 96. iocon_pio1_5 re gister (iocon_pio1_5, address 0x4004 40a0) bit description . . . . . . . 98 table 97. iocon_pio1_6 re gister (iocon_pio1_6, address 0x4004 40a4) bit description . . . . . . . 98 t a b le 98. iocon_pio1_7 re gister (iocon_pio1_7, address 0x4004 40a8) bit description . . . . . . . 99 table 99. iocon_pio3_3 re gister (iocon_pio3_3, address 0x4004 40ac) bit description . . . . . 100 table 100. iocon sck location register (iocon_sck_loc, address 0x4004 40b0) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 101. iocon dsr location register (iocon_dsr_loc, address 0x4004 40b4) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 102. iocon dcd location register (iocon_dcd_loc, address 0x4004 40b8) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 103. iocon ri location register (iocon_ri_loc, address 0x4004 40bc) bit description . . . . . 101 table 104. register overview: i/o configuration (base address 0x4004 4000) . . . . . . . . . . . . . . . . . . 105 table 105. i/o configuration registers ordered by port number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 106. iocon_pio2_6 register (iocon_pio2_6, address 0x4004 4000) bit description . . . . . . 108 table 107. iocon_pio2_0 register (iocon_pio2_0, address 0x4004 4008) bit description . . . . . . 109 table 108. iocon_reset_pio0_0 register
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 522 of 543 nxp semiconductors um10398 chapter 29: supplementary information (iocon_reset_pio0_0, address 0x4004 400c) bit description. . . . . . . . . . . . . . . . . . . .109 table 109. iocon_pio0_1 r egister (iocon_pio0_1, address 0x4004 4010) bit description . . . . . . 110 table 110. iocon_pio1_8 register (iocon_pio1_8, address 0x4004 4014) bit description . . . . . . 111 table 111. iocon_pio0_2 register (iocon_pio0_2, address 0x4004 401c) bit description . . . . . . 111 table 112. iocon_pio2_7 register (iocon_pio2_7, address 0x4004 4020) bit description . . . . . . 112 table 113. iocon_pio2_8 register (iocon_pio2_8, address 0x4004 4024) bit description . . . . . . 112 table 114. iocon_pio2_1 register (iocon_pio2_1, address 0x4004 4028) bit description . . . . . . 113 table 115. iocon_pio0_3 register (iocon_pio0_3, address 0x4004 402c) bit description . . . . . . 114 table 116. iocon_pio0_4 register (iocon_pio0_4, address 0x4004 4030) bit description . . . . . . 114 table 117. iocon_pio0_5 register (iocon_pio0_5, address 0x4004 4034) bit description . . . . . . 115 table 118. iocon_pio1_9 register (iocon_pio1_9, address 0x4004 4038) bit description . . . . . . 115 table 119. iocon_pio3_4 register (iocon_pio3_4, address 0x4004 403c) bit description . . . . . . 116 table 120. iocon_pio2_4 r egister (iocon_pio2_4, address 0x4004 4040) bit description . . . . . . 116 table 121. iocon_pio2_5 r egister (iocon_pio2_5, address 0x4004 4044) bit description . . . . . . 117 table 122. iocon_pio3_5 r egister (iocon_pio3_5, address 0x4004 4048) bit description . . . . . . 117 table 123. iocon_pio0_6 r egister (iocon_pio0_6, address 0x4004 404c) bit description . . . . . . 118 table 124. iocon_pio0_7 r egister (iocon_pio0_7, address 0x4004 4050) bit description. . . . . . . 119 table 125. iocon_pio2_9 r egister (iocon_pio2_9, address 0x4004 4054) bit description . . . . . . 119 table 126. iocon_pio2_10 register (iocon_pio2_10, address 0x4004 4058) bit description . . . . . .120 table 127. iocon_pio2_2 r egister (iocon_pio2_2, address 0x4004 405c) bit description . . . . . .120 table 128. iocon_pio0_8 r egister (iocon_pio0_8, address 0x4004 4060) bit description . . . . . .121 table 129. iocon_pio0_9 r egister (iocon_pio0_9, address 0x4004 4064) bit description . . . . . .121 table 130. iocon_swclk_pio0_10 register (iocon_swclk_pio0_10, address 0x4004 4068) bit description . . . . . . . . . . . . . . . . . . .122 table 131. iocon_pio1_10 register (iocon_pio1_10, address 0x4004 406c) bit description . . . . . .123 table 132. iocon_pio2_11 register (iocon_pio2_11, address 0x4004 4070) bit description . . . . . .123 table 133. iocon_r_pio0_11 register (iocon_r_pio0_11, address 0x4004 4074) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .124 table 134. iocon_r_pio1_0 re gister (iocon_r_pio1_0, address 0x4004 4078) bit description . . . . . .125 table 135. iocon_r_pio1_1 re gister (iocon_r_pio1_1, address 0x4004 407c) bit description . . . . . .125 table 136. iocon_r_pio1_2 register (iocon_r_pio1_2, address 0x4004 4080) bit description . . . . . 126 table 137. iocon_pio3_0 register (iocon_pio3_0, address 0x4004 4084) bit description . . . . . . 127 table 138. iocon_pio3_1 register (iocon_pio3_1, address 0x4004 4088) bit description . . . . . . 128 table 139. iocon_pio2_3 register (iocon_pio2_3, address 0x4004 408c) bit description . . . . . 128 table 140. iocon_swdio_pio1_3 register (iocon_swdio_pio1_3, address 0x4004 4090) bit description . . . . . . . . . . . . . . . . . . . . . . . . 129 table 141. iocon_pio1_4 register (iocon_pio1_4, address 0x4004 4094) bit description . . . . . . 130 table 142. iocon_pio1_11 register (iocon_pio1_11, address 0x4004 4098) bit description . . . . . 130 table 143. iocon_pio3_2 register (iocon_pio3_2, address 0x4004 409c) bit description . . . . . 131 table 144. iocon_pio1_5 register (iocon_pio1_5, address 0x4004 40a0) bit description . . . . . . 132 table 145. iocon_pio1_6 register (iocon_pio1_6, address 0x4004 40a4) bit description . . . . . . 132 table 146. iocon_pio1_7 register (iocon_pio1_7, address 0x4004 40a8) bit description . . . . . . 133 table 147. iocon_pio3_3 register (iocon_pio3_3, address 0x4004 40ac) bit description . . . . . 133 table 148. iocon sck0 location register (iocon_sck0_loc, address 0x4004 40b0) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 149. iocon dsr location register (iocon_dsr_loc, address 0x4004 40b4) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 150. iocon dcd location register (iocon_dcd_loc, address 0x4004 40b8) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 151. iocon ri location register (iocon_ri_loc, address 0x4004 40bc) bit description . . . . . 135 table 152. iocon ssel1 location register (iocon_ssel1_loc, address 0x4004 4018) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 153. iocon ct16b0_cap0 location register (iocon_ct16b0_cap0_loc, address 0x4004 40c0) bit description . . . . . . . . . . . . . . . . . . . 136 table 154. iocon sck1 location register (iocon_sck1_loc, address 0x4004 40c4) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 155. iocon miso1 location register (iocon_miso1_loc, address 0x4004 40c8) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 156. iocon mosi1 location register (iocon_mosi1_loc, address 0x4004 40cc) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 157. iocon ct32b0_cap0 location register (iocon_ct32b0_cap0_loc, address 0x4004 40d0) bit description . . . . . . . . . . . . . . . . . . . 137 table 158. iocon rxd location register (iocon_rxd_loc, address 0x4004 40d4) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 table 159. lpc11(d)1x/lpc11cxx pin configurations . . 139
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 523 of 543 nxp semiconductors um10398 chapter 29: supplementary information table 160. lpc1113/14 and lpc11c12/c14 pin description table (lqfp48 package) . . . . . . . . . . . . . . . .145 table 161. LPC1111/12/13/14 pin description table (hvqfn33 package) . . . . . . . . . . . . . . . . . .149 table 162. lpc1112fhn24 pin description table (hvqfn24 package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 table 163. lpc11c24/c22 pin description table (lqfp48 package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 table 164. lpc11d14 pin description table (lqfp100 package) . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 table 165. lpc11xx pin configurations for 20-pin and 28-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 table 166. lpc1110/11/12 pin description table (so20 and tssop20 package with i 2 c-bus pins) . . . . . .164 table 167. lpc1112 pin description table (tssop20 with v dda and v ssa pins) . . . . . . . . . . . . . . . . . . .167 table 168. lpc1112/14 pin description table (tssop28 and dip28 packages) . . . . . . . . . . . . . . . . . . . . . .170 table 169. lpc1100xl pin configurations. . . . . . . . . . . .173 table 170. lpc1100xl series: lpc1113/14/15 pin description table (lqfp48 and tfbga48 package) . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 table 171. LPC1111/12/13/14xl pin description table (hvqfn33 package) . . . . . . . . . . . . . . . . . .182 table 172. gpio configuration . . . . . . . . . . . . . . . . . . . .186 table 173. register overview: gpio (base address port 0: 0x5000 0000; port 1: 0x5001 0000, port 2: 0x5002 0000; port 3: 0x5003 0000) . . . . . . . . . . . . . .187 table 174. gpiondata register (gpio0data, address 0x5000 0000 to 0x5000 3ffc; gpio1data, address 0x5001 0000 to 0x5001 3ffc; gpio2data, address 0x5002 0000 to 0x5002 3ffc; gpio3data, address 0x5003 0000 to 0x5003 3ffc) bit description . . . . . . . . . . . .187 table 175. gpiondir register (gpio0dir, address 0x5000 8000 to gpio3dir, address 0x5003 8000) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .188 table 176. gpionis register (gpio0is, address 0x5000 8004 to gpio3is, address 0x5003 8004) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .188 table 177. gpionibe register (gpio0ibe, address 0x5000 8008 to gpio3ibe, address 0x5003 8008) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .189 table 178. gpioniev register (gpio0iev, address 0x5000 800c to gpio3iev, address 0x5003 800c) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .189 table 179. gpionie register (gpio0ie, address 0x5000 8010 to gpio3ie, address 0x5003 8010) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .189 table 180. gpionris register (gpio0ris, address 0x5000 8014 to gpio3ris, address 0x5003 8014) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .190 table 181. gpionmis register (gpio0mis, address 0x5000 8018 to gpio3mis, address 0x5003 8018) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .190 table 182. gpionic register (gpio0ic, address 0x5000 801c to gpio3ic, address 0x5003 801c) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .190 table 183. uart pin description . . . . . . . . . . . . . . . . . . 194 table 184. register overview: uart (base address: 0x4000 8000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 table 185. uart receiver buffer register (u0rbr - address 0x4000 8000 when dlab = 0, read only) bit description . . . . . . . . . . . . . . . . . . . 196 table 186. uart transmitter holding register (u0thr - address 0x4000 8000 when dlab = 0, write only) bit description . . . . . . . . . . . . . . . . . . . . 196 table 187. uart divisor latch lsb register (u0dll - address 0x4000 8000 when dlab = 1) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 table 188. uart divisor latch msb register (u0dlm - address 0x4000 8004 when dlab = 1) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 table 189. uart interrupt enable register (u0ier - address 0x4000 8004 when dlab = 0) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . 197 table 190. uart interrupt identification register (u0iir - address 0x4004 8008, read only) bit description 198 table 191. uart interrupt handling . . . . . . . . . . . . . . . . 199 table 192. uart fifo control register (u0fcr - address 0x4000 8008, write only) bit description . . . . 201 table 193. uart line control register (u0lcr - address 0x4000 800c) bit description . . . . . . . . . . . . 201 table 194. uart0 modem control register (u0mcr - address 0x4000 8010) bit description . . . . . . 202 table 195. modem status interrupt generation . . . . . . . . 204 table 196. uart line status register (u0lsr - address 0x4000 8014, read only) bit description . . . 205 table 197. uart modem status register (u0msr - address 0x4000 8018) bit description . . . . . . 207 table 198. uart scratch pad register (u0scr - address 0x4000 801c) bit description . . . . . . . . . . . . . 207 table 199. auto baud control register (u0acr - address 0x4000 8020) bit description . . . . . . . . . . . . . 208 table 200. uart fractional divider register (u0fdr - address 0x4000 8028) bit description . . . . . . 211 table 201. fractional divider setting look-up table . . . . . 214 table 202. uart transmit enable register (u0ter - address 0x4000 8030) bit description . . . . . . 215 table 203. uart rs485 control register (u0rs485ctrl - address 0x4000 804c) bit description . . . . . 215 table 204. uart rs485 address match register (u0rs485adrmatch - address 0x4000 8050) bit description. . . . . . . . . . . . . . . . . . . . . . . . . 216 table 205. uart rs485 delay value register (u0rs485dly - address 0x4000 8054) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 table 206. spi pin descriptions . . . . . . . . . . . . . . . . . . . 221 table 207. register overview: spi0 (base address 0x4004 0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 table 208. register overview: spi1 (base address 0x4005 8000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 table 209: spi/ssp control regi ster 0 (ssp0cr0 - address 0x4004 0000, ssp1cr0 - address 0x4005 8000) bit description. . . . . . . . . . . . . . . . . . . . . . . . . 223
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 524 of 543 nxp semiconductors um10398 chapter 29: supplementary information table 210: spi/ssp control regi ster 1 (ssp0cr1 - address 0x4004 0004, ssp1cr1 - address 0x4005 8004) bit description . . . . . . . . . . . . . . . . . . . . . . . . .224 table 211: spi/ssp data register (ssp0dr - address 0x4004 0008, ssp1dr - address 0x4005 8008) bit description . . . . . . . . . . . . . . . . . . . . . . . . .224 table 212: spi/ssp status r egister (ssp0sr - address 0x4004 000c, ssp1sr - address 0x4005 800c) bit description . . . . . . . . . . . . . . . . . . . . . . . . .225 table 213: spi/ssp clock presca le register (ssp0cpsr - address 0x4004 0010, ssp1cpsr - address 0x4005 8010) bit description . . . . . . . . . . . . .225 table 214: spi/ssp interrupt mask set/clear register (ssp0imsc - address 0x4004 0014, ssp1imsc - address 0x4005 8014) bit description. . . . . . .226 table 215: spi/ssp raw interrupt status register (ssp0ris - address 0x4004 0018, ssp1ris - address 0x4005 8018) bit description . . . . . . . . . . . . .226 table 216: spi/ssp masked in terrupt status register (ssp0mis - address 0x4004 001c, ssp1mis - address 0x4005 801c) bit description . . . . . .227 table 217: spi/ssp interrupt clear register (ssp0icr - address 0x4004 0020, ssp1icr - address 0x4005 8020) bit description . . . . . . . . . . . . .227 table 218. i 2 c-bus pin description. . . . . . . . . . . . . . . . . .237 table 219. register overview: i 2 c (base address 0x4000 0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237 table 220. i 2 c control set register (i2c0conset - address 0x4000 0000) bit description . . . . . . . . . . . . .238 table 221. i 2 c status register (i2c0stat - 0x4000 0004) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .240 table 222. i 2 c data register (i2c0dat - 0x4000 0008) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .240 table 223. i 2 c slave address register 0 (i2c0adr0- 0x4000 000c) bit description . . . . . . . . . . . . .241 table 224. i 2 c scl high duty cycle register (i2c0sclh - address 0x4000 0010) bit description. . . . . . .241 table 225. i 2 c scl low duty cycle r egister (i2c0scll - 0x4000 0014) bit description . . . . . . . . . . . . .241 table 226. scll + sclh values for selected i 2 c clock values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 table 227. i 2 c control clear register (i2c0conclr - 0x4000 0018) bit description . . . . . . . . . . . . .242 table 228. i 2 c monitor mode control register (i2c0mmctrl - 0x4000 001c) bit description . . . . . . . . . . . .243 table 229. i 2 c slave address registers (i2c0adr[1, 2, 3]- 0x4000 00[20, 24, 28]) bit description . . . . . .244 table 230. i 2 c data buffer register (i2c0data_buffer - 0x4000 002c) bit description . . . . . . . . . . . . .245 table 231. i 2 c mask registers (i2c0mask[0, 1, 2, 3] - 0x4000 00[30, 34, 38, 3c]) bit description . . .245 table 232. i2c0conset and i2c1conset used to configure master mode . . . . . . . . . . . . . . . . . .246 table 233. i2c0conset and i2c1conset used to configure slave mode . . . . . . . . . . . . . . . . . . .247 table 234. abbreviations used to describe an i 2 c operation. 253 table 235. i2c0conset used to initialize master transmitter mode . . . . . . . . . . . . . . . . . . . . . . 253 table 236. master transmitter mode . . . . . . . . . . . . . . . 255 table 237. master receiver mode . . . . . . . . . . . . . . . . . 258 table 238. i2c0adr and i2c1adr usage in slave receiver mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 table 239. i2c0conset and i2c1conset used to initialize slave receiver mode . . . . . . . . . . . . 260 table 240. slave receiver mode . . . . . . . . . . . . . . . . . 261 table 241. slave transmitter mode . . . . . . . . . . . . . . . . 265 table 242. miscellaneous states . . . . . . . . . . . . . . . . . . 267 table 243. can pin description (lpc11c12/c14) . . . . . 280 table 244. can pin description (lpc11c22/c24) . . . . . 280 table 245. register overview: ccan (base address 0x4005 0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 table 246. can control registers (cancntl, address 0x4005 0000) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 table 247. can status register (canstat, address 0x4005 0004) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 table 248. can error counter (canec, address 0x4005 0008) bit description . . . . . . . . . . . . 285 table 249. can bit timing register (canbt, address 0x4005 000c) bit description . . . . . . . . . . . . . 286 table 250. can interrupt register (canint, address 0x4005 0010) bit description . . . . . . . . . . . . . 287 table 251. can test register (cantest, address 0x4005 0014) bit description . . . . . . . . . . . . . 287 table 252. can baud rate prescaler extension register (canbrpe, address 0x4005 0018) bit description 288 table 253. message interface regi sters . . . . . . . . . . . . . 289 table 254. structure of a message object in the message ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 table 255. can message interface command request registers (canif1_cmdreq, address 0x4005 0020 and canif2_cmdreq, address 0x4005 0080) bit description . . . . . . . . . . . . . 290 table 256. can message interface command mask registers (canif1_cmdmsk_w, address 0x4005 0024 and canif2_cmdmsk_w, address 0x4005 0084) bit description for write direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 table 257. can message interface command mask registers (canif1_cmdmsk_r, address 0x4005 0024 and canif2_cmdmsk_r, address 0x4005 0084) bit description for read direction . 291 table 258. can message interface command mask 1 registers (canif1_msk1, address 0x4005 0028 and canif2_mask1, address 0x4005 0088) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 table 259. can message interface command mask 2 registers (canif1_msk2, address 0x4005 002c and canif2_mask2, address 0x4005 008c) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 table 260. can message interface command arbitration 1
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 525 of 543 nxp semiconductors um10398 chapter 29: supplementary information registers (canif1_arb1, address 0x4005 0030 and canif2_arb1, address 0x4005 0090) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .294 table 261. can message interface command arbitration 2 registers (canif1_arb2, address 0x4005 0034 and canif2_arb2, address 0x4005 0094) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .294 table 262. can message interface message control registers (canif1_mctrl, address 0x4005 0038 and canif2_mctrl, address 0x4005 0098) bit description . . . . . . . . . . . .295 table 263. can message interface data a1 registers (canif1_da1, address 0x4005 003c and canif2_da1, address 0x4005 009c) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .296 table 264. can message interface data a2 registers (canif1_da2, address 0x4005 0040 and canif2_da2, address 0x4005 00a0) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .296 table 265. can message interface data b1 registers (canif1_db1, address 0x4005 0044 and canif2_db1, address 0x4005 00a4) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .297 table 266. can message interface data b2 registers (canif1_db2, address 0x4005 0048 and canif2_db2, address 0x4005 00a8) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .297 table 267. can transmission request 1 register (cantxreq1, address 0x4005 0100) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .297 table 268. can transmission request 2 register (cantxreq2, address 0x4005 0104) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .298 table 269. can new data 1 register (cannd1, address 0x4005 0120) bit description . . . . . . . . . . . . .298 table 270. can new data 2 register (cannd2, address 0x4005 0124) bit description . . . . . . . . . . . . .298 table 271. can interrupt pending 1 register (canir1, address 0x4005 0140) bit description. . . . . . .299 table 272. can interrupt pending 2 register (canir2, addresses 0x4005 0144) bit description . . . . .299 table 273. can message valid 1 register (canmsgv1, addresses 0x4005 0160) bit description . . . . .299 table 274. can message valid 2 register (canmsgv2, address 0x4005 0164) bit description. . . . . . .300 table 275. can clock divider register (canclkdiv, address 0x4005 0180) bit description . . . . . . . . . . . . .300 table 276. initialization of a transmit object. . . . . . . . . . .309 table 277. initialization of a receiv e object . . . . . . . . . . .310 table 278. parameters of the c_ can bit time. . . . . . . . .314 table 279. counter/timer pin descrip tion . . . . . . . . . . . . .330 table 280. register overview: 16-bit counter/timer 0 ct16b0 (base address 0x4000 c000) . . . . .331 table 281. register overview: 16-bit counter/timer 1 ct16b1 (base address 0x4001 0000) . . . . .332 table 282. interrupt register (tmr16b0ir - address 0x4000 c000 and tmr16b1ir - address 0x4001 0000) bit description . . . . . . . . . . . . .333 table 283. timer control register (tmr16b0tcr - address 0x4000 c004 and tmr16b1tcr - address 0x4001 0004) bit description . . . . . . . . . . . . . 333 table 284: timer counter registers (tmr16b0tc, address 0x4000 c008 and tmr16b1tc 0x4001 0008) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 table 285: prescale registers (tmr16b0pr, address 0x4000 c00c and tmr16b1pr 0x4001 000c) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 table 286: prescale counter registers (tmr16b0pc, address 0x4001 c010 and tmr16b1pc 0x4000 0010) bit description . . . . . . . . . . . . . 334 table 287. match control register (tmr16b0mcr - address 0x4000 c014 and tmr16b1mcr - address 0x4001 0014) bit description . . . . . 334 table 288: match registers (tmr16b0mr0 to 3, addresses 0x4000 c018 to 24 and tmr16b1mr0 to 3, addresses 0x4001 0018 to 24) bit description 336 table 289. capture control register (tmr16b0ccr - address 0x4000 c028 and tmr16b1ccr - address 0x4001 0028) bit description . . . . . . 336 table 290: capture registers (tmr16b0cr0, address 0x4000 c02c and tmr16b1cr0, address 0x4001 002c) bit description . . . . . . . . . . . . . 336 table 291. external match register (tmr16b0emr - address 0x4000 c03c and tmr16b1emr - address 0x4001 003c) bit description . . . . . . 337 table 292. external match control . . . . . . . . . . . . . . . . . 338 table 293. count control register (tmr16b0ctcr - address 0x4000 c070 and tmr16b1ctcr - address 0x4001 0070) bit description . . . . . . 339 table 294. pwm control register (tmr16b0pwmc - address 0x4000 c074 and tmr16b1pwmc- address 0x4001 0074) bit description . . . . . . 339 table 295. counter/timer pin description . . . . . . . . . . . . 344 table 296. register overview: 16-bit counter/timer 0 ct16b0 (base address 0x4000 c000) . . . . 345 table 297. register overview: 16-bit counter/timer 1 ct16b1 (base address 0x4001 0000) . . . . . 346 table 298. interrupt register (tmr16b0ir - address 0x4000 c000 and tmr16b1ir - address 0x4001 0000) bit description . . . . . . . . . . . . . 347 table 299. timer control register (tmr16b0tcr - address 0x4000 c004 and tmr16b1tcr - address 0x4001 0004) bit description . . . . . . . . . . . . . 347 table 300: timer counter registers (tmr16b0tc, address 0x4000 c008 and tmr16b1tc 0x4001 0008) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 table 301: prescale registers (tmr16b0pr, address 0 x 4000 c00c and tmr16b1pr 0x4001 000c) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 table 302: prescale counter registers (tmr16b0pc, address 0x4001 c010 and tmr16b1pc 0x4000 0010) bit description . . . . . . . . . . . . . 348 table 303. match control register (tmr16b0mcr - address 0x4000 c014 and tmr16b1mcr - address 0x4001 0014) bit description . . . . . 348 table 304: match registers (tmr16b0mr0 to 3, addresses
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 526 of 543 nxp semiconductors um10398 chapter 29: supplementary information 0x4000 c018 to 24 and tmr16b1mr0 to 3, addresses 0x4001 0018 to 24) bit description 350 table 305. capture control register (tmr16b0ccr - address 0x4000 c028 and tmr16b1ccr - address 0x4001 0028) bit description. . . . . . .350 table 306: capture registers (tmr16b0cr0/1, address 0x4000 c02c/30 and tmr16b1cr0/1, address 0x4001 002c/30) bit description . . . . . . . . . . .351 table 307. external match register (tmr16b0emr - address 0x4000 c03c and tmr16b1emr - address 0x4001 003c) bit description . . . . . .351 table 308. external match control . . . . . . . . . . . . . . . . . .352 table 309. count control register (tmr16b0ctcr - address 0x4000 c070 and tmr16b1ctcr - address 0x4001 0070) bit description. . . . . . .353 table 310. pwm control register (tmr16b0pwmc - address 0x4000 c074 and tmr16b1pwmc- address 0x4001 0074) bit description. . . . . . .354 table 311. counter/timer pin descr iption . . . . . . . . . . . . .359 table 312. register overview: 32-bit counter/timer 0 ct32b0 (base address 0x4001 4000) . . . . .359 table 313. register overview: 32-bit counter/timer 1 ct32b1 (base address 0x4001 8000) . . . . .360 table 314: interrupt register (tmr32b0ir - address 0x4001 4000 and tmr32b1ir - address 0x4001 8000) bit description . . . . . . . . . . . . .361 table 315: timer control register (tmr32b0tcr - address 0x4001 4004 and tmr32b1tcr - address 0x4001 8004) bit description . . . . . . . . . . . . .362 table 316: timer counter registers (tmr32b0tc, address 0x4001 4008 and tmr32b1tc 0x4001 8008) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .362 table 317: prescale registers (tmr32b0pr, address 0x4001 400c and tmr32b1pr 0x4001 800c) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .362 table 318: prescale counter registers (tmr32b0pc, address 0x4001 4010 and tmr32b1pc 0x4001 8010) bit description . . . . . . . . . . . . .363 table 319: match control register (tmr32b0mcr - address 0x4001 4014 and tmr32b1mcr - address 0x4001 8014) bit description. . . . . . .363 table 320: match registers (tmr32b0mr0 to 3, addresses 0x4001 4018 to 24 and tmr32b1mr0 to 3, addresses 0x4001 8018 to 24) bit description 364 table 321: capture control register (tmr32b0ccr - address 0x4001 4028 and tmr32b1ccr - address 0x4001 8028) bit description. . . . . . .364 table 322: capture registers (tmr32b0cr0, addresses 0x4001 402c and tmr32b1cr0, addresses 0x4001 802c) bit description . . . . . . . . . . . . .365 table 323: external match register (tmr32b0emr - address 0x4001 403c and tmr32b1emr - address0x4001 803c) bit de scription . . . . . . .366 table 324. external match control . . . . . . . . . . . . . . . . . .367 table 325: count control register (tmr32b0ctcr - address 0x4001 4070 and tmr32b1tcr - address 0x4001 8070) bit description . . . . . .368 table 326: pwm control register (tmr32b0pwmc - 0x4001 4074 and tmr32b1pwmc - 0x4001 8074) bit description. . . . . . . . . . . . . . . . . . . . 368 table 327. counter/timer pin description . . . . . . . . . . . . 373 table 328. register overview: 32-bit counter/timer 0 ct32b0 (base address 0x4001 4000) . . . . . 374 table 329. register overview: 32-bit counter/timer 1 ct32b1 (base address 0x4001 8000) . . . . . 375 table 330: interrupt register (tmr32b0ir - address 0x4001 4000 and tmr32b1ir - address 0x4001 8000) bit description . . . . . . . . . . . . . 376 table 331: timer control register (tmr32b0tcr - address 0x4001 4004 and tmr32b1tcr - address 0x4001 8004) bit description . . . . . . . . . . . . . 376 table 332: timer counter registers (tmr32b0tc, address 0x4001 4008 and tmr32b1tc 0x4001 8008) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 table 333: prescale registers (tmr32b0pr, address 0x4001 400c and tmr32b1pr 0x4001 800c) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 table 334: prescale counter registers (tmr32b0pc, address 0x4001 4010 and tmr32b1pc 0x4001 8010) bit description . . . . . . . . . . . . . 377 table 335: match control register (tmr32b0mcr - address 0x4001 4014 and tmr32b1mcr - address 0x4001 8014) bit description . . . . . . 377 table 336: match registers (tmr32b0mr0 to 3, addresses 0x4001 4018 to 24 and tmr32b1mr0 to 3, addresses 0x4001 8018 to 24) bit description 379 table 337: capture control register (tmr32b0ccr - address 0x4001 4028 and tmr32b1ccr - address 0x4001 8028) bit description . . . . . . 379 table 338: capture registers (tmr32b0cr0/1, addresses 0x4001 402c/30 and tmr32b1cr0/1, addresses 0x4001 802c/30) bit description . . . . . . . . . . 380 table 339: external match register (tmr32b0emr - address 0x4001 403c and tmr32b1emr - address0x4001 803c) bit description . . . . . . 380 table 340. external match control . . . . . . . . . . . . . . . . . 381 table 341: count control register (tmr32b0ctcr - address 0x4001 4070 and tmr32b1tcr - address 0x4001 8070) bit description . . . . . 382 table 342: pwm control register (tmr32b0pwmc - 0x4001 4074 and tmr32b1pwmc - 0x4001 8074) bit description. . . . . . . . . . . . . . . . . . . . 383 table 343. register overview: watchdog timer (base address 0x4000 4000) . . . . . . . . . . . . . . . . . . 390 table 344: watchdog mode register (wdmod - 0x4000 4000) bit description . . . . . . . . . . . . . 390 table 345. watchdog operating modes selection . . . . . . 391 table 346: watchdog timer constant register (wdtc - 0x4000 4004) bit description . . . . . . . . . . . . . 392 table 347: watchdog feed register (wdfeed - 0x4000 4008) bit description . . . . . . . . . . . . . 392 table 348: watchdog timer value register (wdtv - 0x4000 400c) bit description . . . . . . . . . . . . . 392 table 349: watchdog timer warning interrupt register (wdwarnint - 0x4000 4014) bit description393 t a b le 350: watchdog timer window register (wdwindow
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 527 of 543 continued >> nxp semiconductors um10398 chapter 29: supplementary information - 0x4000 4018) bit description . . . . . . . . . . . .393 table 351. register overview: watchdog timer (base address 0x4000 4000) . . . . . . . . . . . . . . . . . .397 table 352. watchdog mode register (wdmod - address 0x4000 4000) bit description . . . . . . . . . . . . .397 table 353. watchdog operating modes selection . . . . . .398 table 354. watchdog constant register (wdtc - address 0x4000 4004) bit description . . . . . . . . . . . . .398 table 355. watchdog feed register (wdfeed - address 0x4000 4008) bit description . . . . . . . . . . . . .399 table 356. watchdog timer value register (wdtv - address 0x4000 000c) bit description . . . . . . . . . . . . .399 table 357. register overview: systick timer (base address 0xe000 e000). . . . . . . . . . . . . . . . . . . . . . . . .401 table 358. systick timer control and status register (syst_csr - 0xe000 e010) bit description .402 table 359. system timer reload value register (syst_rvr - 0xe000 e014) bit description . . . . . . . . . . . .402 table 360. system timer current value register (syst_cvr - 0xe000 e018) bit description .402 table 361. system timer calibration value register (syst_calib - 0xe000 e01c) bit description . . . 403 table 362. adc pin description . . . . . . . . . . . . . . . . . . . .405 table 363. register overview: adc (base address 0x4001 c000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405 table 364. a/d control register (ad0cr - address 0x4001 c000) bit description . . . . . . . . . . . . .406 table 365. a/d global data register (ad0gdr - address 0x4001 c004) bit description . . . . . . . . . . . . .407 table 366. a/d interrupt enable register (ad0inten - address 0x4001 c00c) bit description . . . . . .408 table 367. a/d data registers (ad0dr0 to ad0dr7 - addresses 0x4001 c010 to 0x4001 c02c) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .408 table 368. a/d status register (ad0stat - address 0x4001 c030) bit description . . . . . . . . . . . . .409 table 369. lpc111x/lpc11cx flash configurations. . . . .410 table 370. lpc111x flash configuration (lpc1100, lpc1100l, lpc1100c series) . . . . . . . . . . . .415 table 371. lpc1100xl flash configuration . . . . . . . . . . .415 table 372. code read protection options . . . . . . . . . . . .417 table 373. code read protection hardware/software interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . .417 table 374. isp commands allowed for different crp levels . 418 table 375. uart isp command summary . . . . . . . . . . .420 table 376. uart isp unlock command . . . . . . . . . . . . .421 table 377. uart isp set baud rate command . . . . . . .421 table 378. uart isp echo command . . . . . . . . . . . . . .421 table 379. uart isp write to ram command . . . . . . . .422 table 380. uart isp read memory command . . . . . . . 423 table 381. uart isp prepare sector(s) for write operation command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 table 382. uart isp copy ram to flash command . . . 424 table 383. uart isp go command . . . . . . . . . . . . . . . . 425 table 384. uart isp erase sector command . . . . . . . . 425 table 385. uart isp blank check sector command . . . 426 table 386. uart isp read part identification command. . . 426 table 387. lpc111x and lpc11cxx part identification numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 table 388. uart isp read boot code version number command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 table 389. uart isp compare command . . . . . . . . . . . 428 table 390. uart isp readuid command . . . . . . . . . . . 428 table 391. uart isp return codes summary . . . . . . . 429 table 392. c_can isp and uart isp command summary 430 table 393. c_can isp object directory . . . . . . . . . . . . . 431 table 394. c_can isp sdo abort codes. . . . . . . . . . . . 433 table 395. iap command summary . . . . . . . . . . . . . . . 435 table 396. iap prepare sector(s) for write operation command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436 table 397. iap copy ram to flash command. . . . . . . . . 437 table 398. iap erase sector(s) command . . . . . . . . . . . 437 table 399. iap blank check se ctor(s) command . . . . . . 438 table 400. iap read part identification command . . . . . 438 table 401. iap read boot code version number command 438 table 402. iap compare command . . . . . . . . . . . . . . . . 439 table 403. iap reinvoke isp . . . . . . . . . . . . . . . . . . . . . 440 table 404. iap readuid command . . . . . . . . . . . . . . . . 440 table 405. iap erase page command . . . . . . . . . . . . . . 440 table 406. iap status codes summary . . . . . . . . . . . . . 441 table 407. memory mapping in debug mode . . . . . . . . . 441 table 408. flash configuration register (flashcfg, address 0x4003 c010) bit description . . . . . . 442 table 409. register overview: fmc (base address 0x4003 c000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 table 410. flash module signature start register (fmsstart - 0x4003 c020) bit description . 444 table 411. flash module signature stop register (fmsstop - 0x4003 c024) bit description . . . . . . . . . . . . 444 table 412. fmsw0 register bit description (fmsw0, address: 0x4003 c02c) . . . . . . . . . . . . . . . . 444 table 413. fmsw1 register bit description (fmsw1, address: 0x4003 c030) . . . . . . . . . . . . . . . . . 444 table 414. fmsw2 register bit description (fmsw2, address: 0x4003 c034) . . . . . . . . . . . . . . . . . 444 table 415. fmsw3 register bit description (fmsw3, address: 0x4003 40c8) . . . . . . . . . . . . . . . . 444
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 528 of 543 nxp semiconductors um10398 chapter 29: supplementary information table 416. flash module status register (fmstat - 0x4003 cfe0) bit description . . . . . . . . . . . . . . . . . . .445 table 417. flash module status clear register (fmstatclr - 0x0x4003 cfe8) bit description . 445 table 418. serial wire debug pin description . . . . . . . . .447 table 419. summary of processor mode and stack use options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .451 table 420. core register set summar y. . . . . . . . . . . . . . .452 table 421. psr register combinations . . . . . . . . . . . . . .453 table 422. apsr bit assignments . . . . . . . . . . . . . . . . . .454 table 423. ipsr bit assignments. . . . . . . . . . . . . . . . . . .454 table 424. epsr bit assignments . . . . . . . . . . . . . . . . . .455 table 425. primask register bit assignments . . . . . . . .455 table 426. control register bit assignments . . . . . . .456 table 427. memory access behavior . . . . . . . . . . . . . . . .460 table 428. properties of different exception types. . . . . .462 table 429. exception return behavior . . . . . . . . . . . . . . .467 table 430. cortex-m0 instructions . . . . . . . . . . . . . . . . . .470 table 431. cmsis intrinsic functions to generate some cortex-m0 instructions . . . . . . . . . . . . . . . . . .471 table 432. cmsis intrinsic func tions to access the special registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .472 table 433. condition code suffixes . . . . . . . . . . . . . . . . .477 table 434. access instructions . . . . . . . . . . . . . . . . . . . .477 table 435. data processing instructions . . . . . . . . . . . . .483 table 436. adc, add, rsb, sbc and sub operand restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . .485 table 437. branch and control instructions . . . . . . . . . . .492 table 438. branch ranges . . . . . . . . . . . . . . . . . . . . . . . .493 table 439. miscellaneous instructions . . . . . . . . . . . . . . .494 table 440. core peripheral register regions . . . . . . . . . .501 table 441. nvic register summary . . . . . . . . . . . . . . . . .502 table 442. cmisis access nvic functions . . . . . . . . . .502 table 443. iser bit assignments. . . . . . . . . . . . . . . . . . .503 table 444. icer bit assignments . . . . . . . . . . . . . . . . . .503 table 445. ispr bit assignments. . . . . . . . . . . . . . . . . . .503 table 446. icpr bit assignments . . . . . . . . . . . . . . . . . .504 table 447. ipr bit assignments . . . . . . . . . . . . . . . . . . . .504 table 448. cmsis functions for nvic control . . . . . . . . .506 table 449. summary of the scb registers . . . . . . . . . . .507 table 450. cpuid register bit assignments. . . . . . . . . . .507 table 451. icsr bit assignments . . . . . . . . . . . . . . . . . .508 table 452. aircr bit assignments . . . . . . . . . . . . . . . . .510 table 453. scr bit assignments . . . . . . . . . . . . . . . . . . .510 table 454. ccr bit assignments . . . . . . . . . . . . . . . . . . . 511 table 455. system fault handler priority fields . . . . . . . . . 511 table 456. shpr2 register bit assignments . . . . . . . . . .512 table 457. shpr3 register bit assignments . . . . . . . . . .512 table 458. system timer registers summary . . . . . . . . . .512 table 459. syst_csr bit assignments . . . . . . . . . . . . .513 table 460. syst_rvr bit assignments . . . . . . . . . . . . .513 table 461. syst_cvr bit assignments . . . . . . . . . . . . .514 table 462. syst_calib register bit assignments . . . . .514 table 463. cortex m0- instruction summary . . . . . . . . . .515 table 464. abbreviations . . . . . . . . . . . . . . . . . . . . . . . .518
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 529 of 543 nxp semiconductors um10398 chapter 29: supplementary information 29.5 figures fig 1. lpc111x block diagram (lpc1100 and lpc1100l series) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 fig 2. lpc111x block diagram (lpc1100xl series) . . .13 fig 3. lpc11cxx/lpc11d14 block diagram (lpc1100c series and lpc11d14). . . . . . . . . . . . . . . . . . . . .14 fig 4. lpc11d14 block diagram . . . . . . . . . . . . . . . . . .15 fig 5. pcf8576d block diagram . . . . . . . . . . . . . . . . . .15 fig 6. lpc111x/lpc11cxx memory map (lpc1100 and lpc1100l series) . . . . . . . . . . . . . . . . . . . . . . . .18 fig 7. lpc111x memory map (lpc1100xl series) . . . .19 fig 8. lpc111x/lpc11cxx cgu block diagram . . . . . .22 fig 9. start-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . .45 fig 10. system pll block diagram . . . . . . . . . . . . . . . . .51 fig 11. power profiles pointer structure . . . . . . . . . . . . . .58 fig 12. lpc111x/102/202/302 clock configuration for power api use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 fig 13. power profiles usage . . . . . . . . . . . . . . . . . . . . . .63 fig 14. standard i/o pin configuration . . . . . . . . . . . . . . .69 fig 15. standard i/o pin configuration . . . . . . . . . . . . . .103 fig 16. pin configuration lqfp48 package . . . . . . . . . .140 fig 17. pin configuration hvqfn33 package . . . . . . . .141 fig 18. pin configuration hvqfn24 package . . . . . . . .141 fig 19. pin configuration lqfp48 package . . . . . . . . . .142 fig 20. pin configuration (lpc11c22/c24) . . . . . . . . . .143 fig 21. pin configuration lqfp100 package . . . . . . . . .144 fig 22. pin configuration so20 package . . . . . . . . . . . .163 fig 23. pin configuration tssop20 package with i 2 c-bus pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164 fig 24. pin configuration tssop20 package with v dda and v ssa pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 fig 25. pin configuration tssop28 package . . . . . . . .169 fig 26. pin configuration dip28 package. . . . . . . . . . . .169 fig 27. pin configuration lqfp48 package . . . . . . . . . .174 fig 28. lpc1100xl series pin configuration tfbga48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 fig 29. pin configuration hvqfn33 package . . . . . . . .176 fig 30. masked write operation to the gpiodata register . 191 fig 31. masked read operation . . . . . . . . . . . . . . . . . . .192 fig 32. auto-rts functional timing . . . . . . . . . . . . . . .204 fig 33. auto-cts functional timing . . . . . . . . . . . . . . .205 fig 34. auto-baud a) mode 0 and b) mode 1 waveform 210 fig 35. algorithm for setting uart dividers. . . . . . . . . .213 fig 36. uart block diagram . . . . . . . . . . . . . . . . . . . . .219 fig 37. texas instruments synchronous serial frame format: a) single and b) continuous/back-to-back two frames transfer. . . . . . . . . . . . . . . . . . . . .228 fig 38. spi frame format with cpol=0 and cpha=0 (a) single and b) continuous transfer) . . . . . . . . . .229 fig 39. spi frame format with cpol=0 and cpha=1 . .230 fig 40. spi frame format with cpol = 1 and cpha = 0 (a) single and b) continuous transfer) . . . . . . . . . .231 fig 41. spi frame format with cpol = 1 and cpha = 1 . . 232 fig 42. microwire frame format (single transfer) . . . . . .233 fig 43. microwire frame format (continuous transfers) .233 fig 44. microwire frame format setup and hold details . 234 fig 45. i 2 c-bus configuration. . . . . . . . . . . . . . . . . . . . . 236 fig 46. format in the master transmitter mode . . . . . . 246 fig 47. format of master receiver mode . . . . . . . . . . . 247 fig 48. a master receiver swit ches to master transmitter after sending repeated start . . . . . . . . . . . . 247 fig 49. format of slave receiver mode . . . . . . . . . . . . 248 fig 50. format of slave transmitter mode . . . . . . . . . . 248 fig 51. i 2 c serial interface block diag ram . . . . . . . . . . . 249 fig 52. arbitration procedure. . . . . . . . . . . . . . . . . . . . . 251 fig 53. serial clock synchronization . . . . . . . . . . . . . . . 251 fig 54. format and states in the master transmitter mode 256 fig 55. format and states in the master receiver mode . . 259 fig 56. format and states in the slave receiver mode 263 fig 57. format and states in the slave transmitter mode . 266 fig 58. simultaneous repeated start conditions from two masters. . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 fig 59. forced access to a busy i 2 c-bus . . . . . . . . . . . 268 fig 60. recovering from a bus obstruction caused by a low level on sda . . . . . . . . . . . . . . . . . . . . . . 269 fig 61. c_can block diagram. . . . . . . . . . . . . . . . . . . . 279 fig 62. can core in silent mode. . . . . . . . . . . . . . . . . . 303 fig 63. can core in loop-back mode . . . . . . . . . . . . . . 303 fig 64. can core in loop-back mode combined with silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 fig 65. block diagram of a message object transfer . . 306 fig 66. reading a message from the fifo buffer to the message buffer . . . . . . . . . . . . . . . . . . . . . . . . . 312 fig 67. bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 fig 68. can api pointer structure. . . . . . . . . . . . . . . . . 317 fig 69. sample pwm waveforms with a pwm cycle length of 100 (selected by mr2) and mat2:0 enabled as pwm outputs by the pwcm register. . . . . . . . . 341 fig 70. a timer cycle in whic h pr=2, mrx=6, and both interrupt and reset on match are enabled . . . . . 341 fig 71. a timer cycle in whic h pr=2, mrx=6, and both interrupt and stop on match are enabled . . . . . 341 fig 72. 16-bit counter/timer blo ck diagram . . . . . . . . . . 342 fig 73. sample pwm waveforms with a pwm cycle length of 100 (selected by mr2) and mat2:0 enabled as pwm outputs by the pwcm register. . . . . . . . . 355 fig 74. a timer cycle in whic h pr=2, mrx=6, and both interrupt and reset on match are enabled . . . . . 356 fig 75. a timer cycle in whic h pr=2, mrx=6, and both interrupt and stop on match are enabled . . . . . 356 fig 76. 16-bit counter/timer blo ck diagram . . . . . . . . . . 357 fig 77. sample pwm waveforms with a pwm cycle length of 100 (selected by mr2) and mat2:0 enabled as pwm outputs by the pwcm register. . . . . . . . . 370 fig 78. a timer cycle in whic h pr=2, mrx=6, and both interrupt and reset on match are enabled . . . . . 370 fig 79. a timer cycle in whic h pr=2, mrx=6, and both interrupt and stop on match are enabled . . . . . 370
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 530 of 543 nxp semiconductors um10398 chapter 29: supplementary information fig 80. 32-bit counter/timer block diagram. . . . . . . . . . .371 fig 81. a timer cycle in whic h pr=2, mrx=6, and both interrupt and reset on match are enabled . . . . .384 fig 82. a timer cycle in whic h pr=2, mrx=6, and both interrupt and stop on match are enabled . . . . . .385 fig 83. sample pwm waveforms with a pwm cycle length of 100 (selected by mr2) and mat2:0 enabled as pwm outputs by the pwmc register. . . . . . . . .385 fig 84. 32-bit counter/timer block diagram. . . . . . . . . . .386 fig 85. windowed watchdog timer (wwdt) block diagram 389 fig 86. early watchdog feed with windowed mode enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393 fig 87. correct watchdog feed with windowed mode enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .394 fig 88. watchdog warning interrupt . . . . . . . . . . . . . . .394 fig 89. watchdog block diagram . . . . . . . . . . . . . . . . . .399 fig 90. system tick timer block diagram . . . . . . . . . . . .400 fig 91. boot process flowchart . . . . . . . . . . . . . . . . . . .414 fig 92. iap parameter passing . . . . . . . . . . . . . . . . . . .436 fig 93. algorithm for generating a 128-bit signature . . .446 fig 94. connecting the swd pins to a standard swd connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .448 fig 95. cortex-m0 implementation. . . . . . . . . . . . . . . . .449 fig 96. processor core register se t . . . . . . . . . . . . . . . .452 fig 97. apsr, ipsr, epsr register bit assignments . .453 fig 98. generic arm cortex-m0 memory map . . . . . . .458 fig 99. memory ordering restrictions . . . . . . . . . . . . . . .459 fig 100. little-endian format . . . . . . . . . . . . . . . . . . . . . .461 fig 101. vector table . . . . . . . . . . . . . . . . . . . . . . . . . . . .464 fig 102. exception entry stack cont ents . . . . . . . . . . . . .466 fig 103. asr #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .473 fig 104. lsr #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .474 fig 105. lsl #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .474 fig 106. ror #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .475 fig 107. ipr register . . . . . . . . . . . . . . . . . . . . . . . . . . . .504
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 531 of 543 nxp semiconductors um10398 chapter 29: supplementary information 29.6 contents chapter 1: lpc111x/lpc11cxx introductory information 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 ordering information . . . . . . . . . . . . . . . . . . . . . 8 1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.5 arm cortex-m0 processor . . . . . . . . . . . . . . . 16 chapter 2: lpc111x/lpc11cxx memory mapping 2.1 how to read this chapter . . . . . . . . . . . . . . . . . 17 2.2 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . 17 chapter 3: lpc111x/lpc11cxx system configuration (syscon) 3.1 how to read this chapter . . . . . . . . . . . . . . . . . 20 device_id register . . . . . . . . . . . . . . . . . . . . .20 c_can controller . . . . . . . . . . . . . . . . . . . . . . .20 entering deep power-down m ode . . . . . . . . . .20 enabling sequence for uart clock . . . . . . . . .20 nmi source selection register . . . . . . . . . . . . . .20 3.2 general description . . . . . . . . . . . . . . . . . . . . . 20 3.3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4 clock generation . . . . . . . . . . . . . . . . . . . . . . . 21 3.5 register description . . . . . . . . . . . . . . . . . . . . 22 3.5.1 system memory remap register . . . . . . . . . . . 24 3.5.2 peripheral reset control register . . . . . . . . . . . 24 3.5.3 system pll control register . . . . . . . . . . . . . . 25 3.5.4 system pll status register. . . . . . . . . . . . . . . 25 3.5.5 system oscillator control register . . . . . . . . . . 26 3.5.6 watchdog oscillator control register . . . . . . . . 26 3.5.7 internal resonant crystal control register. . . . . 27 3.5.8 system reset status register . . . . . . . . . . . . . . 27 3.5.9 system pll clock source select register . . . . 28 3.5.10 system pll clock sour ce update enable register. 29 3.5.11 main clock source select register . . . . . . . . . . 29 3.5.12 main clock source update enable register . . . 29 3.5.13 system ahb clock divider register . . . . . . . . . 30 3.5.14 system ahb clock control register . . . . . . . . . 30 3.5.15 spi0 clock divider register . . . . . . . . . . . . . . . 32 3.5.16 uart clock divider register . . . . . . . . . . . . . . 32 3.5.17 spi1 clock divider register . . . . . . . . . . . . . . . 32 3.5.18 wdt clock source select register . . . . . . . . . . 33 3.5.19 wdt clock source update enable register . . . 33 3.5.20 wdt clock divider register . . . . . . . . . . . . . . . 33 3.5.21 clkout clock source select register. . . . . . . 34 3.5.22 clkout clock source update enable register 34 3.5.23 clkout clock divider register . . . . . . . . . . . . 35 3.5.24 por captured pio status register 0 . . . . . . . . 35 3.5.25 por captured pio status register 1 . . . . . . . . 35 3.5.26 bod control register . . . . . . . . . . . . . . . . . . . . 36 3.5.27 system tick counter calibration register . . . . . 36 3.5.28 irq latency register . . . . . . . . . . . . . . . . . . . . 36 3.5.29 nmi source selection register . . . . . . . . . . . . . 37 3.5.30 start logic edge control register 0 . . . . . . . . . . 37 3.5.31 start logic signal enable register 0 . . . . . . . . . 38 3.5.32 start logic reset register 0 . . . . . . . . . . . . . . . . 38 3.5.33 start logic status register 0 . . . . . . . . . . . . . . 39 3.5.34 deep-sleep mode configuration register . . . . 39 3.5.35 wake-up configuration register . . . . . . . . . . . 40 3.5.36 power-down configuration register . . . . . . . . 41 3.5.37 device id register . . . . . . . . . . . . . . . . . . . . . 42 3.6 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.7 start-up behavior. . . . . . . . . . . . . . . . . . . . . . . 44 3.8 brown-out detection . . . . . . . . . . . . . . . . . . . . 45 3.9 power management . . . . . . . . . . . . . . . . . . . . 45 3.9.1 active mode . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.9.1.1 power configuration in active mode. . . . . . . . 46 3.9.2 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.9.2.1 power configuration in sleep mode . . . . . . . . 46 3.9.2.2 programming sleep mode . . . . . . . . . . . . . . . 46 3.9.2.3 wake-up from sleep mode . . . . . . . . . . . . . . 47 3.9.3 deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 47 3.9.3.1 power configuration in deep-sleep mode . . . 47 3.9.3.2 programming deep-sleep mode . . . . . . . . . . 47 3.9.3.3 wake-up from deep-sleep mode . . . . . . . . . . 48 3.9.4 deep power-down mode . . . . . . . . . . . . . . . . 48 3.9.4.1 power configuration in deep power-down mode . 48 3.9.4.2 programming deep power-down mode . . . . . 48 3.9.4.3 wake-up from deep power-down mode . . . . 49 3.10 deep-sleep mode details . . . . . . . . . . . . . . . . 49 3.10.1 irc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.10.2 start logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.10.3 using the general purpose counter/timers to create a self-wake-up event. . . . . . . . . . . . . . 50 3.11 system pll functional description . . . . . . . . 50 3.11.1 lock detector . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.11.2 power-down control . . . . . . . . . . . . . . . . . . . . 51 3.11.3 divider ratio programming . . . . . . . . . . . . . . . 52 post divider . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 feedback divider . . . . . . . . . . . . . . . . . . . . . . . 52 changing the divider values. . . . . . . . . . . . . . . 52 3.11.4 frequency selection. . . . . . . . . . . . . . . . . . . . 52 3.11.4.1 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.11.4.2 power-down mode . . . . . . . . . . . . . . . . . . . . . 53 3.12 flash memory access. . . . . . . . . . . . . . . . . . . 53
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 532 of 543 nxp semiconductors um10398 chapter 29: supplementary information chapter 4: lpc111x/lpc11cxx power monitor unit (pmu) 4.1 how to read this chapter . . . . . . . . . . . . . . . . . 55 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.3 register description . . . . . . . . . . . . . . . . . . . . 55 4.3.1 power control register . . . . . . . . . . . . . . . . . . 55 4.3.2 general purpose registers 0 to 3 . . . . . . . . . 56 4.3.3 general purpose register 4 . . . . . . . . . . . . . . 56 4.4 functional description . . . . . . . . . . . . . . . . . . 57 chapter 5: lpc111x/lpc11cxx power profiles 5.1 how to read this chapter . . . . . . . . . . . . . . . . . 58 5.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.4 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.5 clocking routine . . . . . . . . . . . . . . . . . . . . . . . 59 5.5.1 set_pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.5.1.1 param0: system pll input frequency and param1: expected syst em clock . . . . . . . . . . . 60 5.5.1.2 param2: mode . . . . . . . . . . . . . . . . . . . . . . . . 60 5.5.1.3 param3: system pll lock time-out . . . . . . . . . 61 5.5.1.4 code examples. . . . . . . . . . . . . . . . . . . . . . . . 61 5.5.1.4.1 invalid frequency (device maximum clock rate exceeded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.5.1.4.2 invalid frequency se lection (system clock divider restrictions) . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.5.1.4.3 exact solution cannot be found (pll). . . . . . . 62 5.5.1.4.4 system clock less than or equal to the expected value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.5.1.4.5 system clock greater than or equal to the expected value. . . . . . . . . . . . . . . . . . . . . . . . 62 5.5.1.4.6 system clock approxim ately equal to the expected value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.6 power routine . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.6.1 set_power . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.6.1.1 param0: main clock . . . . . . . . . . . . . . . . . . . . 64 5.6.1.2 param1: mode . . . . . . . . . . . . . . . . . . . . . . . . 64 5.6.1.3 param2: system clock . . . . . . . . . . . . . . . . . . 64 5.6.1.4 code examples . . . . . . . . . . . . . . . . . . . . . . . 65 5.6.1.4.1 invalid frequency (device maximum clock rate exceeded) . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.6.1.4.2 an applicable power setup. . . . . . . . . . . . . . . 65 chapter 6: lpc111x/lpc11cxx nested vectored interrupt controller (nvic) 6.1 how to read this chapter . . . . . . . . . . . . . . . . . 66 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.4 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 66 chapter 7: lpc1100/lpc1100c/lpc1100l series: i/o configuration (ioconfig) 7.1 how to read this chapter . . . . . . . . . . . . . . . . . 68 pin configuration . . . . . . . . . . . . . . . . . . . . . . . .68 c_can pins . . . . . . . . . . . . . . . . . . . . . . . . . . .68 pseudo open-drain function . . . . . . . . . . . . . . .68 pull-up level . . . . . . . . . . . . . . . . . . . . . . . . . . .68 7.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.3 general description . . . . . . . . . . . . . . . . . . . . . 69 7.3.1 pin function. . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.3.2 pin mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.3.3 hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.3.4 a/d-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.3.5 i 2 c mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.3.6 open-drain mode . . . . . . . . . . . . . . . . . . . . . . 71 7.4 register description . . . . . . . . . . . . . . . . . . . . 71 7.4.1 iocon_pio2_6 . . . . . . . . . . . . . . . . . . . . . . . 74 7.4.2 iocon_pio2_0 . . . . . . . . . . . . . . . . . . . . . . . 75 7.4.3 iocon_pio_reset_pio0_0 . . . . . . . . . . . . 75 7.4.4 iocon_pio0_1 . . . . . . . . . . . . . . . . . . . . . . . 76 7.4.5 iocon_pio1_8 . . . . . . . . . . . . . . . . . . . . . . . 77 7.4.6 iocon_pio0_2 . . . . . . . . . . . . . . . . . . . . . . . 77 7.4.7 iocon_pio2_7 . . . . . . . . . . . . . . . . . . . . . . . 78 7.4.8 iocon_pio2_8 . . . . . . . . . . . . . . . . . . . . . . . 78 7.4.9 iocon_pio2_1 . . . . . . . . . . . . . . . . . . . . . . . 79 7.4.10 iocon_pio0_3 . . . . . . . . . . . . . . . . . . . . . . . 80 7.4.11 iocon_pio0_4 . . . . . . . . . . . . . . . . . . . . . . . 80 7.4.12 iocon_pio0_5 . . . . . . . . . . . . . . . . . . . . . . . 81 7.4.13 iocon_pio1_9 . . . . . . . . . . . . . . . . . . . . . . . 81 7.4.14 iocon_pio3_4 . . . . . . . . . . . . . . . . . . . . . . . 81 7.4.15 iocon_pio2_4 . . . . . . . . . . . . . . . . . . . . . . . 82 7.4.16 iocon_pio2_5 . . . . . . . . . . . . . . . . . . . . . . . 83 7.4.17 iocon_pio3_5 . . . . . . . . . . . . . . . . . . . . . . . 83 7.4.18 iocon_pio0_6 . . . . . . . . . . . . . . . . . . . . . . . 84 7.4.19 iocon_pio0_7 . . . . . . . . . . . . . . . . . . . . . . . 84 7.4.20 iocon_pio2_9 . . . . . . . . . . . . . . . . . . . . . . . 85 7.4.21 iocon_pio2_10 . . . . . . . . . . . . . . . . . . . . . . 86 7.4.22 iocon_pio2_2 . . . . . . . . . . . . . . . . . . . . . . . 86 7.4.23 iocon_pio0_8 . . . . . . . . . . . . . . . . . . . . . . . 87 7.4.24 iocon_pio0_9 . . . . . . . . . . . . . . . . . . . . . . . 87 7.4.25 iocon_swclk_pio0_10 . . . . . . . . . . . . . . 88 7.4.26 iocon_pio1_10 . . . . . . . . . . . . . . . . . . . . . . 89 7.4.27 iocon_pio2_11 . . . . . . . . . . . . . . . . . . . . . . 90 7.4.28 iocon_r_pio0_11. . . . . . . . . . . . . . . . . . . . 90 7.4.29 iocon_r_pio1_0 . . . . . . . . . . . . . . . . . . . . 91 7.4.30 iocon_r_pio1_1 . . . . . . . . . . . . . . . . . . . . 92 7.4.31 iocon_r_pio1_2 . . . . . . . . . . . . . . . . . . . . 92 7.4.32 iocon_pio3_0 . . . . . . . . . . . . . . . . . . . . . . . 93 7.4.33 iocon_pio3_1 . . . . . . . . . . . . . . . . . . . . . . . 94 7.4.34 iocon_pio2_3 . . . . . . . . . . . . . . . . . . . . . . . 94 7.4.35 iocon_swdio_pio1_3. . . . . . . . . . . . . . . . 95
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 533 of 543 nxp semiconductors um10398 chapter 29: supplementary information 7.4.36 iocon_pio1_4 . . . . . . . . . . . . . . . . . . . . . . . 96 7.4.37 iocon_pio1_11 . . . . . . . . . . . . . . . . . . . . . . 97 7.4.38 iocon_pio3_2 . . . . . . . . . . . . . . . . . . . . . . . 97 7.4.39 iocon_pio1_5 . . . . . . . . . . . . . . . . . . . . . . . 98 7.4.40 iocon_pio1_6 . . . . . . . . . . . . . . . . . . . . . . . 98 7.4.41 iocon_pio1_7 . . . . . . . . . . . . . . . . . . . . . . . 99 7.4.42 iocon_pio3_3 . . . . . . . . . . . . . . . . . . . . . . 100 7.4.43 iocon_sck_loc . . . . . . . . . . . . . . . . . . . 100 7.4.44 iocon_dsr_loc . . . . . . . . . . . . . . . . . . . 101 7.4.45 iocon_dcd_loc . . . . . . . . . . . . . . . . . . . 101 7.4.46 iocon_ri_loc . . . . . . . . . . . . . . . . . . . . . 101 chapter 8: lpc1100xl series: i/o configuration (ioconfig) 8.1 how to read this chapter . . . . . . . . . . . . . . . . 102 8.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 8.3 general description . . . . . . . . . . . . . . . . . . . . 102 8.3.1 pin function. . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.3.2 pin mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.3.3 hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8.3.4 a/d-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8.3.5 i 2 c mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8.3.6 open-drain mode . . . . . . . . . . . . . . . . . . . . . 104 8.4 register description . . . . . . . . . . . . . . . . . . . 104 8.4.1 iocon_pio2_6 . . . . . . . . . . . . . . . . . . . . . . 108 8.4.2 iocon_pio2_0 . . . . . . . . . . . . . . . . . . . . . . 109 8.4.3 iocon_pio_reset_pio0_0 . . . . . . . . . . . 109 8.4.4 iocon_pio0_1 . . . . . . . . . . . . . . . . . . . . . . 110 8.4.5 iocon_pio1_8 . . . . . . . . . . . . . . . . . . . . . . 111 8.4.6 iocon_pio0_2 . . . . . . . . . . . . . . . . . . . . . . 111 8.4.7 iocon_pio2_7 . . . . . . . . . . . . . . . . . . . . . . 112 8.4.8 iocon_pio2_8 . . . . . . . . . . . . . . . . . . . . . . 112 8.4.9 iocon_pio2_1 . . . . . . . . . . . . . . . . . . . . . . 113 8.4.10 iocon_pio0_3 . . . . . . . . . . . . . . . . . . . . . . 114 8.4.11 iocon_pio0_4 . . . . . . . . . . . . . . . . . . . . . . 114 8.4.12 iocon_pio0_5 . . . . . . . . . . . . . . . . . . . . . . 115 8.4.13 iocon_pio1_9 . . . . . . . . . . . . . . . . . . . . . . 115 8.4.14 iocon_pio3_4 . . . . . . . . . . . . . . . . . . . . . . 115 8.4.15 iocon_pio2_4 . . . . . . . . . . . . . . . . . . . . . . 116 8.4.16 iocon_pio2_5 . . . . . . . . . . . . . . . . . . . . . . 117 8.4.17 iocon_pio3_5 . . . . . . . . . . . . . . . . . . . . . . 117 8.4.18 iocon_pio0_6 . . . . . . . . . . . . . . . . . . . . . . 118 8.4.19 iocon_pio0_7 . . . . . . . . . . . . . . . . . . . . . . 119 8.4.20 iocon_pio2_9 . . . . . . . . . . . . . . . . . . . . . . 119 8.4.21 iocon_pio2_10 . . . . . . . . . . . . . . . . . . . . . 120 8.4.22 iocon_pio2_2 . . . . . . . . . . . . . . . . . . . . . . 120 8.4.23 iocon_pio0_8 . . . . . . . . . . . . . . . . . . . . . . 121 8.4.24 iocon_pio0_9 . . . . . . . . . . . . . . . . . . . . . . 121 8.4.25 iocon_swclk_pio0_10 . . . . . . . . . . . . . 122 8.4.26 iocon_pio1_10 . . . . . . . . . . . . . . . . . . . . . 123 8.4.27 iocon_pio2_11 . . . . . . . . . . . . . . . . . . . . . 123 8.4.28 iocon_r_pio0_11. . . . . . . . . . . . . . . . . . . 124 8.4.29 iocon_r_pio1_0 . . . . . . . . . . . . . . . . . . . 125 8.4.30 iocon_r_pio1_1 . . . . . . . . . . . . . . . . . . . 125 8.4.31 iocon_r_pio1_2 . . . . . . . . . . . . . . . . . . . 126 8.4.32 iocon_pio3_0 . . . . . . . . . . . . . . . . . . . . . . 127 8.4.33 iocon_pio3_1 . . . . . . . . . . . . . . . . . . . . . . 128 8.4.34 iocon_pio2_3 . . . . . . . . . . . . . . . . . . . . . . 128 8.4.35 iocon_swdio_pio1_3. . . . . . . . . . . . . . . 129 8.4.36 iocon_pio1_4 . . . . . . . . . . . . . . . . . . . . . . 130 8.4.37 iocon_pio1_11 . . . . . . . . . . . . . . . . . . . . . 130 8.4.38 iocon_pio3_2 . . . . . . . . . . . . . . . . . . . . . . 131 8.4.39 iocon_pio1_5 . . . . . . . . . . . . . . . . . . . . . . 132 8.4.40 iocon_pio1_6 . . . . . . . . . . . . . . . . . . . . . . 132 8.4.41 iocon_pio1_7 . . . . . . . . . . . . . . . . . . . . . . 133 8.4.42 iocon_pio3_3 . . . . . . . . . . . . . . . . . . . . . . 133 8.4.43 iocon_sck0_loc . . . . . . . . . . . . . . . . . . 134 8.4.44 iocon_dsr_loc . . . . . . . . . . . . . . . . . . . 135 8.4.45 iocon_dcd_loc . . . . . . . . . . . . . . . . . . . 135 8.4.46 iocon_ri_loc . . . . . . . . . . . . . . . . . . . . . 135 8.4.47 iocon_ssel1_loc. . . . . . . . . . . . . . . . . . 136 8.4.48 iocon_ct16b0_cap0_loc . . . . . . . . . . . 136 8.4.49 iocon_sck1_loc . . . . . . . . . . . . . . . . . . 136 8.4.50 iocon_miso1_loc. . . . . . . . . . . . . . . . . . 137 8.4.51 iocon_mosi1_loc. . . . . . . . . . . . . . . . . . 137 8.4.52 iocon_ct32b0_cap0_loc . . . . . . . . . . . 137 8.4.53 iocon_rxd_loc . . . . . . . . . . . . . . . . . . . 138 chapter 9: lpc111x/lpc11cxx pin configuration (lpc1100, lpc1100c, and lpc1100l series, hvqfn/lqfp packages) 9.1 how to read this chapter . . . . . . . . . . . . . . . . 139 9.2 lpc111x pin configuration . . . . . . . . . . . . . . 140 9.3 lpc11cxx pin configuration. . . . . . . . . . . . . 142 9.4 lpc11d14 pin configuration . . . . . . . . . . . . 144 9.5 lpc111x/lpc11cxx pin description . . . . . . 145 chapter 10: lpc111x pin configuration (lpc1100l series, tssop, dip, so packages) 10.1 how to read this chapter . . . . . . . . . . . . . . . . 163 10.2 pin configuration (lpc1110/11/12) . . . . . . . . 163 10.3 pin configuration (lpc1112) . . . . . . . . . . . . 166 10.4 pin configuration (lpc1112/14) . . . . . . . . . . 169 chapter 11: lpc111x pin configuration (lpc1100xl series, hvqfn/lqfp/tfbga48 packages) 11.1 how to read this chapter . . . . . . . . . . . . . . . . 173 11.2 lpc111x pin configuration . . . . . . . . . . . . . . 174 11.3 lpc1100xl pin description . . . . . . . . . . . . . 176
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 534 of 543 nxp semiconductors um10398 chapter 29: supplementary information chapter 12: lpc111x/lpc11cxx general purpose i/o (gpio) 12.1 how to read this chapter . . . . . . . . . . . . . . . . 186 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 186 12.2.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 12.3 register description . . . . . . . . . . . . . . . . . . . 187 12.3.1 gpio data register . . . . . . . . . . . . . . . . . . . . 187 12.3.2 gpio data direction register . . . . . . . . . . . . . 188 12.3.3 gpio interrupt sense register . . . . . . . . . . . . 188 12.3.4 gpio interrupt both edg es sense register . . 189 12.3.5 gpio interrupt event register . . . . . . . . . . . . 189 12.3.6 gpio interrupt mask regist er . . . . . . . . . . . . 189 12.3.7 gpio raw interrupt status register . . . . . . . . 189 12.3.8 gpio masked interrupt status register. . . . . 190 12.3.9 gpio interrupt clear regist er . . . . . . . . . . . . 190 12.4 functional description . . . . . . . . . . . . . . . . . 191 12.4.1 write/read data operation. . . . . . . . . . . . . . . 191 write operation. . . . . . . . . . . . . . . . . . . . . . . . 191 read operation . . . . . . . . . . . . . . . . . . . . . . . 192 chapter 13: lpc111x/lpc11cxx uart 13.1 how to read this chapter . . . . . . . . . . . . . . . . 193 13.2 basic configuration . . . . . . . . . . . . . . . . . . . . 193 13.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 13.4 pin description . . . . . . . . . . . . . . . . . . . . . . . . 194 13.5 register description . . . . . . . . . . . . . . . . . . . 194 13.5.1 uart receiver buffer register (u0rbr - 0x4000 8000, when dlab = 0, read only) . 196 13.5.2 uart transmitter holding register (u0thr - 0x4000 8000 when dlab = 0, write only). . 196 13.5.3 uart divisor latch lsb and msb registers (u0dll - 0x4000 8000 and u0dlm - 0x4000 8004, when dlab = 1). . . . . . . . . . . 196 13.5.4 uart interrupt enable register (u0ier - 0x4000 8004, when dlab = 0). . . . . . . . . . . 197 13.5.5 uart interrupt identi fication register (u0iir - 0x4004 8008, read only). . . . . . . . . . . . . . . 198 13.5.6 uart fifo control register (u0fcr - 0x4000 8008, write only) . . . . . . . . . . . . . . . 200 13.5.7 uart line control register (u0lcr - 0x4000 800c) . . . . . . . . . . . . . . . . . . . . . . . . 201 13.5.8 uart modem control register . . . . . . . . . . 202 13.5.8.1 auto-flow control . . . . . . . . . . . . . . . . . . . . . . 203 13.5.8.1.1 auto-rts . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 13.5.8.1.2 auto-cts . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 13.5.9 uart line status register (u0lsr - 0x4000 8014, read only). . . . . . . . . . . . . . . 205 13.5.10 uart modem status register . . . . . . . . . . . 207 13.5.11 uart scratch pad register (u0scr - 0x4000 801c) . . . . . . . . . . . . . . . . . . . . . . . . 207 13.5.12 uart auto-baud control register (u0acr - 0x4000 8020) . . . . . . . . . . . . . . . . . . . . . . . . 208 13.5.13 auto-baud . . . . . . . . . . . . . . . . . . . . . . . . . . 208 13.5.14 auto-baud modes. . . . . . . . . . . . . . . . . . . . . 209 13.5.15 uart fractional divider register (u0fdr - 0x4000 8028) . . . . . . . . . . . . . . . . . . . . . . . . . 211 13.5.15.1 baud rate calculation . . . . . . . . . . . . . . . . . . 212 13.5.15.1.1 example 1: uart _pclk = 14.7456 mhz, br = 9600 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 13.5.15.1.2 example 2: uart_pclk = 12 mhz, br = 115200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 13.5.16 uart transmit enable register (u0ter - 0x4000 8030) . . . . . . . . . . . . . . . . . . . . . . . . 214 13.5.17 uart rs485 control register (u0rs485ctrl - 0x4000 804c) . . . . . . . . . . . . . . . . . . . . . . . 215 13.5.18 uart rs485 address match register (u0rs485adrmatch - 0x4000 8050) . . . . 216 13.5.19 uart1 rs485 delay value register (u0rs485dly - 0x4000 8054) . . . . . . . . . . 216 13.5.20 rs-485/eia-485 modes of operation . . . . . . 216 rs-485/eia-485 normal multidrop mode (nmm) 217 rs-485/eia-485 auto address detection (aad) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 rs-485/eia-485 auto direction control. . . . . 217 rs485/eia-485 driver delay time. . . . . . . . . . 218 rs485/eia-485 output inversion . . . . . . . . . . 218 13.6 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 218 chapter 14: lpc111x/lpc11cxx spi0/1 with ssp 14.1 how to read this chapter . . . . . . . . . . . . . . . . 220 14.2 basic configuration . . . . . . . . . . . . . . . . . . . . 220 14.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 14.4 general description . . . . . . . . . . . . . . . . . . . . 220 14.5 pin description . . . . . . . . . . . . . . . . . . . . . . . . 221 14.6 register description . . . . . . . . . . . . . . . . . . . 222 14.6.1 spi/ssp control register 0 . . . . . . . . . . . . . 222 14.6.2 spi/ssp0 contro l register 1 . . . . . . . . . . . . 223 14.6.3 spi/ssp data regi ster . . . . . . . . . . . . . . . . 224 14.6.4 spi/ssp status r egister . . . . . . . . . . . . . . . 225 14.6.5 spi/ssp clock pr escale register . . . . . . . . 225 14.6.6 spi/ssp interrupt mask set/clear register 225 14.6.7 spi/ssp raw interrupt status register . . . 226 14.6.8 spi/ssp masked interrupt status register . 226 14.6.9 spi/ssp interrupt clear register . . . . . . . . 227 14.7 functional description . . . . . . . . . . . . . . . . . 227 14.7.1 texas instruments synchronous serial frame format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 14.7.2 spi frame format . . . . . . . . . . . . . . . . . . . . . 228 14.7.2.1 clock polarity (cpol) and phase (cpha) control 228 14.7.2.2 spi format with cpol=0 ,cpha=0. . . . . . . . 229
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 535 of 543 nxp semiconductors um10398 chapter 29: supplementary information 14.7.2.3 spi format with cpol=0,cpha=1 . . . . . . . . 230 14.7.2.4 spi format with cpol = 1,cpha = 0 . . . . . . 230 14.7.2.5 spi format with cpol = 1,cpha = 1 . . . . . . 232 14.7.3 semiconductor microwire frame format . . . . 232 14.7.3.1 setup and hold time requirements on cs with respect to sk in microwire mode . . . . . . . . . 234 chapter 15: lpc111x/lpc11cxx i2c-bus controller 15.1 how to read this chapter . . . . . . . . . . . . . . . . 235 15.2 basic configuration . . . . . . . . . . . . . . . . . . . . 235 15.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 15.4 applications . . . . . . . . . . . . . . . . . . . . . . . . . . 235 15.5 general description . . . . . . . . . . . . . . . . . . . . 236 15.5.1 i 2 c fast-mode plus . . . . . . . . . . . . . . . . . . . 236 15.6 pin description . . . . . . . . . . . . . . . . . . . . . . . . 237 15.7 register description . . . . . . . . . . . . . . . . . . . 237 15.7.1 i 2 c control set regist er (i2c0conset - 0x4000 0000) . . . . . . . . . . . . . . . . . . . . . . . . 238 15.7.2 i 2 c status register (i2c0stat - 0x4000 0004) . . . 240 15.7.3 i 2 c data register (i2c0dat - 0x4000 0008) . 240 15.7.4 i 2 c slave address register 0 (i2c0adr0- 0x4000 000c) . . . . . . . . . . . . . . . . . . . . . . . . 240 15.7.5 i 2 c scl high and low duty cycle registers (i2c0sclh - 0x4000 0010 and i2c0scll- 0x4000 0014) . . . . . . . . . . . . . . . . . . . . . . . . 241 15.7.5.1 selecting the appropriate i 2 c data rate and duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 15.7.6 i 2 c control clear register (i2c0conclr - 0x4000 0018) . . . . . . . . . . . . . . . . . . . . . . . . 242 15.7.7 i 2 c monitor mode control register (i2c0mmctrl - 0x4000 001c). . . . . . . . . . . . . . . . . . . . . . . 242 15.7.7.1 interrupt in monitor mode . . . . . . . . . . . . . . . 243 15.7.7.2 loss of arbitration in monitor mode . . . . . . . 244 15.7.8 i 2 c slave address register s (i2c0adr[1, 2, 3] - 0x4000 00[20, 24, 28]) . . . . . . . . . . . . . . . . . 244 15.7.9 i 2 c data buffer register (i2c0data_buffer - 0x4000 002c) . . . . . . . . . . . . . . . . . . . . . . . . 244 15.7.10 i 2 c mask registers (i2c0m ask[0, 1, 2, 3] - 0x4000 00[30, 34, 38, 3c]) . . . . . . . . . . . . . . 245 15.8 i 2 c operating modes . . . . . . . . . . . . . . . . . . . 245 15.8.1 master transmitter mode . . . . . . . . . . . . . . . 245 15.8.2 master receiver mode . . . . . . . . . . . . . . . . . 246 15.8.3 slave receiver mode . . . . . . . . . . . . . . . . . . 247 15.8.4 slave transmitter mode . . . . . . . . . . . . . . . . 248 15.9 i 2 c implementation and operation . . . . . . . . 248 15.9.1 input filters and output stages. . . . . . . . . . . . 249 15.9.2 address registers, addr0 to addr3 . . . . . 250 15.9.3 address mask register s, mask0 to mask3. 250 15.9.4 comparator. . . . . . . . . . . . . . . . . . . . . . . . . . 250 15.9.5 shift register, dat. . . . . . . . . . . . . . . . . . . . . 250 15.9.6 arbitration and synchronization logic . . . . . . 250 15.9.7 serial clock generator . . . . . . . . . . . . . . . . . . 251 15.9.8 timing and control . . . . . . . . . . . . . . . . . . . . 252 15.9.9 control register, conset and conclr . . . 252 15.9.10 status decoder and status register . . . . . . . . 252 15.10 details of i 2 c operating modes. . . . . . . . . . . 252 15.10.1 master transmitter mode . . . . . . . . . . . . . . . 253 15.10.2 master receiver mode . . . . . . . . . . . . . . . . . 257 15.10.3 slave receiver mode. . . . . . . . . . . . . . . . . . 260 15.10.4 slave transmitter mode . . . . . . . . . . . . . . . . 264 15.10.5 miscellaneous states . . . . . . . . . . . . . . . . . . 266 15.10.5.1 stat = 0xf8 . . . . . . . . . . . . . . . . . . . . . . . . 266 15.10.5.2 stat = 0x00 . . . . . . . . . . . . . . . . . . . . . . . . 266 15.10.6 some special cases . . . . . . . . . . . . . . . . . . . 267 15.10.6.1 simultaneous repeated start conditions from two masters . . . . . . . . . . . . . . . . . . . . . . . . . 267 15.10.6.2 data transfer after loss of arbitration . . . . . . 268 15.10.6.3 forced access to the i 2 c-bus. . . . . . . . . . . . 268 15.10.6.4 i 2 c-bus obstructed by a low level on scl or sda 269 15.10.6.5 bus error . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 15.10.7 i 2 c state service routines . . . . . . . . . . . . . . . 269 15.10.8 initialization . . . . . . . . . . . . . . . . . . . . . . . . . 270 15.10.9 i 2 c interrupt service . . . . . . . . . . . . . . . . . . . 270 15.10.10 the state service routines . . . . . . . . . . . . . . 270 15.10.11 adapting state services to an application. . . 270 15.11 software example . . . . . . . . . . . . . . . . . . . . . 270 15.11.1 initialization routine . . . . . . . . . . . . . . . . . . . 270 15.11.2 start master transmit function . . . . . . . . . . . 270 15.11.3 start master receive func tion . . . . . . . . . . . 271 15.11.4 i 2 c interrupt routine . . . . . . . . . . . . . . . . . . . 271 15.11.5 non mode specific states. . . . . . . . . . . . . . . 271 15.11.5.1 state: 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . . 271 15.11.5.2 master states . . . . . . . . . . . . . . . . . . . . . . . . 271 15.11.5.3 state: 0x08 . . . . . . . . . . . . . . . . . . . . . . . . . . 271 15.11.5.4 state: 0x10 . . . . . . . . . . . . . . . . . . . . . . . . . . 272 15.11.6 master transmitter states . . . . . . . . . . . . . . 272 15.11.6.1 state: 0x18 . . . . . . . . . . . . . . . . . . . . . . . . . . 272 15.11.6.2 state: 0x20 . . . . . . . . . . . . . . . . . . . . . . . . . . 272 15.11.6.3 state: 0x28 . . . . . . . . . . . . . . . . . . . . . . . . . . 272 15.11.6.4 state: 0x30 . . . . . . . . . . . . . . . . . . . . . . . . . . 273 15.11.6.5 state: 0x38 . . . . . . . . . . . . . . . . . . . . . . . . . . 273 15.11.7 master receive states . . . . . . . . . . . . . . . . . 273 15.11.7.1 state: 0x40 . . . . . . . . . . . . . . . . . . . . . . . . . . 273 15.11.7.2 state: 0x48 . . . . . . . . . . . . . . . . . . . . . . . . . . 273 15.11.7.3 state: 0x50 . . . . . . . . . . . . . . . . . . . . . . . . . . 273 15.11.7.4 state: 0x58 . . . . . . . . . . . . . . . . . . . . . . . . . . 274 15.11.8 slave receiver states . . . . . . . . . . . . . . . . . 274 15.11.8.1 state: 0x60 . . . . . . . . . . . . . . . . . . . . . . . . . . 274 15.11.8.2 state: 0x68 . . . . . . . . . . . . . . . . . . . . . . . . . . 274 15.11.8.3 state: 0x70 . . . . . . . . . . . . . . . . . . . . . . . . . . 274 15.11.8.4 state: 0x78 . . . . . . . . . . . . . . . . . . . . . . . . . . 275 15.11.8.5 state: 0x80 . . . . . . . . . . . . . . . . . . . . . . . . . . 275 15.11.8.6 state: 0x88 . . . . . . . . . . . . . . . . . . . . . . . . . . 275 15.11.8.7 state: 0x90 . . . . . . . . . . . . . . . . . . . . . . . . . . 275 15.11.8.8 state: 0x98 . . . . . . . . . . . . . . . . . . . . . . . . . . 276 15.11.8.9 state: 0xa0. . . . . . . . . . . . . . . . . . . . . . . . . . 276 15.11.9 slave transmitter states . . . . . . . . . . . . . . . 276 15.11.9.1 state: 0xa8. . . . . . . . . . . . . . . . . . . . . . . . . . 276 15.11.9.2 state: 0xb0. . . . . . . . . . . . . . . . . . . . . . . . . . 276
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 536 of 543 nxp semiconductors um10398 chapter 29: supplementary information 15.11.9.3 state: 0xb8 . . . . . . . . . . . . . . . . . . . . . . . . . . 276 15.11.9.4 state: 0xc0 . . . . . . . . . . . . . . . . . . . . . . . . . . 277 15.11.9.5 state: 0xc8 . . . . . . . . . . . . . . . . . . . . . . . . . 277 chapter 16: lpc111x/lpc11cxx c_can controller 16.1 how to read this chapter . . . . . . . . . . . . . . . . 278 16.2 basic configuration . . . . . . . . . . . . . . . . . . . . 278 16.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 16.4 general description . . . . . . . . . . . . . . . . . . . . 279 16.5 pin description . . . . . . . . . . . . . . . . . . . . . . . . 280 16.6 register description . . . . . . . . . . . . . . . . . . . 280 16.6.1 can protocol registers . . . . . . . . . . . . . . . . . 282 16.6.1.1 can control register . . . . . . . . . . . . . . . . . . . 282 16.6.1.2 can status register . . . . . . . . . . . . . . . . . . . 283 16.6.1.3 can error counter . . . . . . . . . . . . . . . . . . . . 285 16.6.1.4 can bit timing register . . . . . . . . . . . . . . . . . 286 baud rate prescaler . . . . . . . . . . . . . . . . . . . .286 time segments 1 and 2 . . . . . . . . . . . . . . . . .286 synchronization jump width . . . . . . . . . . . . . .286 16.6.1.5 can interrupt register . . . . . . . . . . . . . . . . . 287 16.6.1.6 can test register . . . . . . . . . . . . . . . . . . . . . 287 16.6.1.7 can baud rate prescaler extension register 288 16.6.2 message interface registers . . . . . . . . . . . . . 288 16.6.2.1 message objects . . . . . . . . . . . . . . . . . . . . . 289 16.6.2.2 can message interface command request registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 16.6.2.3 can message interface command mask registers 290 16.6.2.4 if1 and if2 message buffer registers. . . . . . 292 16.6.2.4.1 can message interface command mask 1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 16.6.2.4.2 can message interface command mask 2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 16.6.2.4.3 can message interface command arbitration 1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 16.6.2.4.4 can message interface command arbitration 2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 16.6.2.4.5 can message interface message control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 16.6.2.4.6 can message interface data a1 registers . 296 16.6.2.4.7 can message interface data a2 registers . . 296 16.6.2.4.8 can message interface data b1 registers . 297 16.6.2.4.9 can message interface data b2 registers . 297 16.6.3 message handler registers . . . . . . . . . . . . . . 297 16.6.3.1 can transmission request 1 register . . . . . . 297 16.6.3.2 can transmission request 2 register . . . . . . 297 16.6.3.3 can new data 1 register . . . . . . . . . . . . . . . 298 16.6.3.4 can new data 2 register . . . . . . . . . . . . . . . 298 16.6.3.5 can interrupt pending 1 register . . . . . . . . 299 16.6.3.6 can interrupt pending 2 register . . . . . . . . 299 16.6.3.7 can message valid 1 regi ster . . . . . . . . . . 299 16.6.3.8 can message valid 2 regi ster . . . . . . . . . . 300 16.6.4 can timing register . . . . . . . . . . . . . . . . . . . 300 16.6.4.1 can clock divider register . . . . . . . . . . . . . . 300 16.7 functional description . . . . . . . . . . . . . . . . . 300 16.7.1 c_can controller state after reset . . . . . . . . 300 16.7.2 c_can operating modes . . . . . . . . . . . . . . . 301 16.7.2.1 software initialization . . . . . . . . . . . . . . . . . . 301 16.7.2.2 can message transfer. . . . . . . . . . . . . . . . . 301 16.7.2.3 disabled automatic retransmission (dar) . 302 16.7.2.4 test modes. . . . . . . . . . . . . . . . . . . . . . . . . . 302 16.7.2.4.1 silent mode . . . . . . . . . . . . . . . . . . . . . . . . . 302 16.7.2.4.2 loop-back mode . . . . . . . . . . . . . . . . . . . . . 303 16.7.2.4.3 loop-back mode combined with silent mode 303 16.7.2.4.4 basic mode . . . . . . . . . . . . . . . . . . . . . . . . . 304 16.7.2.4.5 software control of pin can_txd . . . . . . . . 304 16.7.3 can message handler . . . . . . . . . . . . . . . . 305 16.7.3.1 management of message objects . . . . . . . . 306 16.7.3.2 data transfer between ifx registers and the message ram . . . . . . . . . . . . . . . . . . . . . . . 307 16.7.3.3 transmission of messages between the shift registers in the can core and the message buffer 307 16.7.3.4 acceptance filtering of received messages . 307 16.7.3.4.1 reception of a data frame . . . . . . . . . . . . . . 308 16.7.3.4.2 reception of a remote frame . . . . . . . . . . . . 308 16.7.3.5 receive/transmit priority . . . . . . . . . . . . . . . 308 16.7.3.6 configuration of a trans mit object . . . . . . . . 308 16.7.3.7 updating a transmit object . . . . . . . . . . . . . . 309 16.7.3.8 configuration of a receive object . . . . . . . . . 309 16.7.3.9 handling of received messages. . . . . . . . . . 310 16.7.3.10 configuration of a fifo buffer . . . . . . . . . . . . 311 16.7.3.10.1 reception of messages with fifo buffers. . 311 16.7.3.10.2 reading from a fifo buffer . . . . . . . . . . . . . 311 16.7.4 interrupt handling . . . . . . . . . . . . . . . . . . . . . 312 16.7.5 bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 16.7.5.1 bit time and bit rate . . . . . . . . . . . . . . . . . . . 314 chapter 17: lpc11cxx c_can on-chip drivers 17.1 how to read this chapter . . . . . . . . . . . . . . . . 316 17.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 17.3 general description . . . . . . . . . . . . . . . . . . . . 316 17.3.1 differences to fully-compliant canopen . . . . 316 17.4 api description . . . . . . . . . . . . . . . . . . . . . . . 317 17.4.1 calling the c_can api. . . . . . . . . . . . . . . . . 317 17.4.2 can initialization . . . . . . . . . . . . . . . . . . . . . 318 17.4.3 can interrupt handler . . . . . . . . . . . . . . . . . . 318 17.4.4 can rx message object configuration . . . . 318 17.4.5 can receive. . . . . . . . . . . . . . . . . . . . . . . . . 319 17.4.6 can transmit . . . . . . . . . . . . . . . . . . . . . . . . 319 17.4.7 canopen configuration . . . . . . . . . . . . . . . . 320 17.4.8 canopen handler . . . . . . . . . . . . . . . . . . . . 322 17.4.9 can/canopen callback f unctions . . . . . . . . 322 17.4.10 can message received ca llback . . . . . . . . . 323 17.4.11 can message transmit ca llback . . . . . . . . . 323 17.4.12 can error callback. . . . . . . . . . . . . . . . . . . . 324
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 537 of 543 nxp semiconductors um10398 chapter 29: supplementary information 17.4.13 canopen sdo expedited read callback. . . . 324 17.4.14 canopen sdo expedited write callback . . . 325 17.4.15 canopen sdo segmented read callback . . 325 17.4.16 canopen sdo segmented write callback . . 326 17.4.17 canopen fall-back sdo handler callback . . 328 chapter 18: lpc1100/lpc1100c/lpc1100l series: 16-bit counter/timer ct16b0/1 18.1 how to read this chapter . . . . . . . . . . . . . . . . 329 pin-out variations . . . . . . . . . . . . . . . . . . . . . .329 18.2 basic configuration . . . . . . . . . . . . . . . . . . . . 329 18.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 18.4 applications . . . . . . . . . . . . . . . . . . . . . . . . . . 330 18.5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 18.6 pin description . . . . . . . . . . . . . . . . . . . . . . . . 330 18.7 register description . . . . . . . . . . . . . . . . . . . 330 18.7.1 interrupt register (tmr16b0ir and tmr16b1ir) 332 18.7.2 timer control register (tmr16b0tcr and tmr16b1tcr) . . . . . . . . . . . . . . . . . . . . . . . 333 18.7.3 timer counter (tmr16b0tc - address 0x4000 c008 and tmr16b1tc - address 0x4001 0008) 333 18.7.4 prescale register (tmr16b0pr - address 0x4000 c00c and tmr16b1pr - address 0x4001 000c) . . . . . . . . . . . . . . . . . . . . . . . . 333 18.7.5 prescale counter register (tmr16b0pc - address 0x4000 c010 and tmr16b1pc - address 0x4001 0010) . . . . . . . . . . . . . . . . . 334 18.7.6 match control register (tmr16b0mcr and tmr16b1mcr) . . . . . . . . . . . . . . . . . . . . . . 334 18.7.7 match registers (tmr16b0mr0/1/2/3 - addresses 0x4000 c018/1c/20/24 and tmr16b1mr0/1/2/3 - addresses 0x4001 0018/1c/20/24) . . . . . . . . . . . . . . . . . . . . . . 335 18.7.8 capture control register (tmr16b0ccr and tmr16b1ccr) . . . . . . . . . . . . . . . . . . . . . . 336 18.7.9 capture register (ct16b0cr0 - address 0x4000 c02c and ct16b1cr0 - address 0x4001 002c) 336 18.7.10 external match register (tmr16b0emr and tmr16b1emr) . . . . . . . . . . . . . . . . . . . . . . 337 18.7.11 count control register (tmr16b0ctcr and tmr16b1ctcr) . . . . . . . . . . . . . . . . . . . . . 338 18.7.12 pwm control register (tmr16b0pwmc and tmr16b1pwmc) . . . . . . . . . . . . . . . . . . . . 339 18.7.13 rules for single edge controlled pwm outputs . . 340 18.8 example timer operation . . . . . . . . . . . . . . . 341 18.9 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 342 chapter 19: lpc1100xl series: 16-bit counter/timer ct16b0/1 19.1 how to read this chapter . . . . . . . . . . . . . . . . 343 19.2 basic configuration . . . . . . . . . . . . . . . . . . . . 343 19.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 19.4 applications . . . . . . . . . . . . . . . . . . . . . . . . . . 344 19.5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 19.6 pin description . . . . . . . . . . . . . . . . . . . . . . . . 344 19.7 register description . . . . . . . . . . . . . . . . . . . 344 19.7.1 interrupt register (tmr16b0ir and tmr16b1ir) 347 19.7.2 timer control register (tmr16b0tcr and tmr16b1tcr) . . . . . . . . . . . . . . . . . . . . . . . 347 19.7.3 timer counter (tmr16b0tc - address 0x4000 c008 and tmr16b1tc - address 0x4001 0008) 347 19.7.4 prescale register (tmr16b0pr - address 0x4000 c00c and tmr16b1pr - address 0x4001 000c) . . . . . . . . . . . . . . . . . . . . . . . . 348 19.7.5 prescale counter register (tmr16b0pc - address 0x4000 c010 and tmr16b1pc - address 0x4001 0010) . . . . . . . . . . . . . . . . . 348 19.7.6 match control register (tmr16b0mcr and tmr16b1mcr) . . . . . . . . . . . . . . . . . . . . . . 348 19.7.7 match registers (tmr16b0mr0/1/2/3 - addresses 0x4000 c018/1c/20/24 and tmr16b1mr0/1/2/3 - addresses 0x4001 0018/1c/20/24) . . . . . . . . . . . . . . . . . . . . . . 349 19.7.8 capture control register (tmr16b0ccr and tmr16b1ccr) . . . . . . . . . . . . . . . . . . . . . . 350 19.7.9 capture register (ct16b0cr0/1 - address 0x4000 c02c/30 and ct16b1cr0/1 - address 0x4001 002c/30) . . . . . . . . . . . . . . . . . . . . . 351 19.7.10 external match register (tmr16b0emr and tmr16b1emr) . . . . . . . . . . . . . . . . . . . . . . 351 19.7.11 count control register (tmr16b0ctcr and tmr16b1ctcr) . . . . . . . . . . . . . . . . . . . . . 353 19.7.12 pwm control register (tmr16b0pwmc and tmr16b1pwmc) . . . . . . . . . . . . . . . . . . . . 354 19.7.13 rules for single edge controlled pwm outputs . . 355 19.8 example timer operation . . . . . . . . . . . . . . . 356 19.9 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 356 chapter 20: lpc1100/lpc1100c/lpc1100l series: 32-bit counter/timer ct32b0/1 20.1 how to read this chapter . . . . . . . . . . . . . . . . 358 20.2 basic configuration . . . . . . . . . . . . . . . . . . . . 358 20.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 20.4 applications. . . . . . . . . . . . . . . . . . . . . . . . . . 358 20.5 description . . . . . . . . . . . . . . . . . . . . . . . . . . 359 20.6 pin description . . . . . . . . . . . . . . . . . . . . . . . 359
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 538 of 543 nxp semiconductors um10398 chapter 29: supplementary information 20.7 register description . . . . . . . . . . . . . . . . . . . 359 20.7.1 interrupt register (tmr32b0ir and tmr32b1ir) 361 20.7.2 timer control register (tmr32b0tcr and tmr32b1tcr) . . . . . . . . . . . . . . . . . . . . . . . 361 20.7.3 timer counter (tmr32b0tc - address 0x4001 4008 and tmr32b1tc - address 0x4001 8008) . . . . . . . . . . . . . . . . . . . . . . . . 362 20.7.4 prescale register (tmr32b0pr - address 0x4001 400c and tmr32b1pr - address 0x4001 800c) . . . . . . . . . . . . . . . . . . . . . . . . 362 20.7.5 prescale counter register (tmr32b0pc - address 0x4001 4010 and tmr32b1pc - address 0x4001 8010) . . . . . . . . . . . . . . . . . . . . . . . . 362 20.7.6 match control register (tmr32b0mcr and tmr32b1mcr) . . . . . . . . . . . . . . . . . . . . . . 363 20.7.7 match registers (tmr32b0mr0/1/2/3 - addresses 0x4001 4018/1c/20/24 and tmr32b1mr0/1/2/3 addresses 0x4001 8018/1c/20/24) . . . . . . . . . . . . . . . . . . . . . . 364 20.7.8 capture control register (tmr32b0ccr and tmr32b1ccr) . . . . . . . . . . . . . . . . . . . . . . 364 20.7.9 capture register (tmr32b0cr0 - address 0x4001 402c and tmr32b1cr0 - address 0x4001 802c) . . . . . . . . . . . . . . . . . . . . . . . 365 20.7.10 external match register (tmr32b0emr and tmr32b1emr) . . . . . . . . . . . . . . . . . . . . . . 365 20.7.11 count control register (tmr32b0ctcr and tmr32b1tcr) . . . . . . . . . . . . . . . . . . . . . . 367 20.7.12 pwm control register (tmr32b0pwmc and tmr32b1pwmc) . . . . . . . . . . . . . . . . . . . . 368 20.7.13 rules for single edge controlled pwm outputs . . 369 20.8 example timer operation . . . . . . . . . . . . . . . 370 20.9 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 371 chapter 21: lpc1100xl series: 32-bit counter/timer ct32b0/1 21.1 how to read this chapter . . . . . . . . . . . . . . . . 372 21.2 basic configuration . . . . . . . . . . . . . . . . . . . . 372 21.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 21.4 applications . . . . . . . . . . . . . . . . . . . . . . . . . . 373 21.5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 21.6 pin description . . . . . . . . . . . . . . . . . . . . . . . . 373 21.7 register description . . . . . . . . . . . . . . . . . . . 373 21.7.1 interrupt register (tmr32b0ir and tmr32b1ir) 376 21.7.2 timer control register (tmr32b0tcr and tmr32b1tcr) . . . . . . . . . . . . . . . . . . . . . . . 376 21.7.3 timer counter (tmr32b0tc - address 0x4001 4008 and tmr32b1tc - address 0x4001 8008) . . . . . . . . . . . . . . . . . . . . . . . . 376 21.7.4 prescale register (tmr32b0pr - address 0x4001 400c and tmr32b1pr - address 0x4001 800c) . . . . . . . . . . . . . . . . . . . . . . . . 377 21.7.5 prescale counter register (tmr32b0pc - address 0x4001 4010 and tmr32b1pc - address 0x4001 8010) . . . . . . . . . . . . . . . . . . . . . . . . 377 21.7.6 match control register (tmr32b0mcr and tmr32b1mcr) . . . . . . . . . . . . . . . . . . . . . . 377 21.7.7 match registers (tmr32b0mr0/1/2/3 - addresses 0x4001 4018/1c/20/24 and tmr32b1mr0/1/2/3 addresses 0x4001 8018/1c/20/24) . . . . . . . . . . . . . . . . . . . . . . 378 21.7.8 capture control register (tmr32b0ccr and tmr32b1ccr) . . . . . . . . . . . . . . . . . . . . . . 379 21.7.9 capture register (tmr32b0cr0/1 - address 0x4001 402c/30 and tmr32b1cr0/1 - address 0x4001 802c/30) . . . . . . . . . . . . . . . . . . . . . 380 21.7.10 external match register (tmr32b0emr and tmr32b1emr) . . . . . . . . . . . . . . . . . . . . . . 380 21.7.11 count control register (tmr32b0ctcr and tmr32b1tcr) . . . . . . . . . . . . . . . . . . . . . . 382 21.7.12 pwm control register (tmr32b0pwmc and tmr32b1pwmc) . . . . . . . . . . . . . . . . . . . . 383 21.8 functional description . . . . . . . . . . . . . . . . . 384 21.8.1 example timer operation . . . . . . . . . . . . . . . 384 21.8.2 rules for single edge controlled pwm outputs . . 385 21.9 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 386 chapter 22: lpc111x/lpc11cxx windowed watchdog timer (wdt) 22.1 how to read this chapter . . . . . . . . . . . . . . . . 387 22.2 basic configuration . . . . . . . . . . . . . . . . . . . . 387 22.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 22.4 applications . . . . . . . . . . . . . . . . . . . . . . . . . . 388 22.5 general description . . . . . . . . . . . . . . . . . . . . 388 22.6 clock control . . . . . . . . . . . . . . . . . . . . . . . . . 389 22.7 register description . . . . . . . . . . . . . . . . . . . 390 22.7.1 watchdog mode register . . . . . . . . . . . . . . . 390 22.7.2 watchdog timer constant register . . . . . . . 391 22.7.3 watchdog feed register . . . . . . . . . . . . . . . 392 22.7.4 watchdog timer value regi ster . . . . . . . . . . 392 22.7.5 watchdog timer warning interrupt register 392 22.7.6 watchdog timer window register . . . . . . . . 393 22.7.7 watchdog timing examples . . . . . . . . . . . . . 393 chapter 23: lpc111x/lpc11cxx watchdog timer (wdt) 23.1 how to read this chapter . . . . . . . . . . . . . . . . 395 23.2 basic configuration. . . . . . . . . . . . . . . . . . . . 395
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 539 of 543 nxp semiconductors um10398 chapter 29: supplementary information 23.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 23.4 applications . . . . . . . . . . . . . . . . . . . . . . . . . . 396 23.5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 23.6 wdt clocking . . . . . . . . . . . . . . . . . . . . . . . . . 396 23.7 register description . . . . . . . . . . . . . . . . . . . 397 23.7.1 watchdog mode register (wdmod - 0x4000 0000) . . . . . . . . . . . . . . . . . . . . . . . . 397 23.7.2 watchdog timer constant register (wdtc - 0x4000 4004) . . . . . . . . . . . . . . . . . . . . . . . . 398 23.7.3 watchdog feed register (wdfeed - 0x4000 4008) . . . . . . . . . . . . . . . . . . . . . . . . 398 23.7.4 watchdog timer va lue register (wdtv - 0x4000 400c) . . . . . . . . . . . . . . . . . . . . . . . 399 23.8 block diagram . . . . . . . . . . . . . . . . . . . . . . . . 399 chapter 24: lpc111x/lpc11cxx system tick timer (systick) 24.1 how to read this chapter . . . . . . . . . . . . . . . . 400 24.2 basic configuration . . . . . . . . . . . . . . . . . . . . 400 24.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 24.4 general description . . . . . . . . . . . . . . . . . . . . 400 24.5 register description . . . . . . . . . . . . . . . . . . . 401 24.5.1 system timer control and status register . . 401 24.5.2 system timer reload value register . . . . . . 402 24.5.3 system timer current value register . . . . . 402 24.5.4 system timer calibration value register (syst_calib - 0xe000 e01c) . . . . . . . . . . 403 24.6 functional description . . . . . . . . . . . . . . . . . 403 24.7 example timer calculations . . . . . . . . . . . . . 403 example (system clock = 50 mhz). . . . . . . . . 403 chapter 25: lpc111x/lpc11cxx adc 25.1 how to read this chapter . . . . . . . . . . . . . . . . 404 25.2 basic configuration . . . . . . . . . . . . . . . . . . . . 404 25.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 25.4 pin description . . . . . . . . . . . . . . . . . . . . . . . . 404 25.5 register description . . . . . . . . . . . . . . . . . . . 405 25.5.1 a/d control register (ad0cr - 0x4001 c000). . . 406 25.5.2 a/d global data register (ad0gdr - 0x4001 c004) . . . . . . . . . . . . . . . . . . . . . . . . 407 25.5.3 a/d interrupt enable register (ad0inten - 0x4001 c00c) . . . . . . . . . . . . . . . . . . . . . . . 408 25.5.4 a/d data registers (ad0dr0 to ad0dr7 - 0x4001 c010 to 0x4001 c02c) . . . . . . . . . . 408 25.5.5 a/d status register (ad0stat - 0x4001 c030) . 409 25.6 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 25.6.1 hardware-triggered conver sion . . . . . . . . . . 409 25.6.2 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 25.6.3 accuracy vs. digital receiv er . . . . . . . . . . . . 409 chapter 26: lpc111x/lpc11cxx flash programming firmware 26.1 how to read this chapter . . . . . . . . . . . . . . . . 410 26.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 26.3 general description . . . . . . . . . . . . . . . . . . . . 411 26.3.1 bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . 411 26.3.2 memory map after any reset. . . . . . . . . . . . . 412 26.3.3 criterion for valid user code . . . . . . . . . . . . 412 26.3.4 boot process flowchart . . . . . . . . . . . . . . . . . 414 26.3.5 flash configuration for lpc1100, lpc1100c, lpc1100l series . . . . . . . . . . . . . . . . . . . . . 415 26.3.6 flash configuration for lpc1100xl series . . 415 26.3.7 flash content protection mechanism . . . . . . 416 26.3.8 code read protection (crp) . . . . . . . . . . . . 416 26.3.8.1 isp entry protection . . . . . . . . . . . . . . . . . . . 418 26.4 uart communication protocol . . . . . . . . . . 419 26.4.1 uart isp command format . . . . . . . . . . . . . 419 26.4.2 uart isp response format . . . . . . . . . . . . . 419 26.4.3 uart isp data format . . . . . . . . . . . . . . . . . 419 26.4.4 uart isp flow control . . . . . . . . . . . . . . . . . 419 26.4.5 uart isp command abort . . . . . . . . . . . . . . 419 26.4.6 interrupts during uart isp . . . . . . . . . . . . . 419 26.4.7 interrupts during iap. . . . . . . . . . . . . . . . . . . 420 26.4.8 ram used by isp command handler (for lpc11cxx parts). . . . . . . . . . . . . . . . . . . . . . 420 26.4.9 ram used by isp command handler (for lpc111x parts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 26.4.10 ram used by iap command handler. . . . . . 420 26.5 uart isp commands . . . . . . . . . . . . . . . . . . 420 26.5.1 unlock (uart isp) . . . . . . . 421 26.5.2 set baud rate (uart isp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 26.5.3 echo (uart isp) . . . . . . . . . . . . . 421 26.5.4 write to ram (uart isp) . . . . . . . . . . . . . . . . . . . . . . . . . 422 26.5.5 read memory

(uart isp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 26.5.6 prepare sector(s) for wr ite operation (uart isp) 423 26.5.7 copy ram to flash (uart isp) . . . . . . 423 26.5.8 go

(uart isp) . . . . . . 424 26.5.9 erase sector(s) (uart isp) . . . . . . . . . . . . 425 26.5.10 blank check sector(s) (uart isp) . . . . . . . . . . . . 426 26.5.11 read part identification number (uart isp) 426 26.5.12 read boot code version number (uart isp) 428
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 540 of 543 nxp semiconductors um10398 chapter 29: supplementary information 26.5.13 compare (uart isp). . . . . . . . . . . . . . . . . . . . . . . . . . 428 26.5.14 readuid (uart isp) . . . . . . . . . . . . . . . . . . 428 26.5.15 uart isp return codes . . . . . . . . . . . . . . . 429 26.6 c_can communication protocol . . . . . . . . . 429 26.6.1 c_can isp sdo communication. . . . . . . . . 430 26.6.2 c_can isp object directory . . . . . . . . . . . . . 431 26.6.3 unlock (c_can isp) . . . . . . . . . . . . . . . . . . 432 26.6.4 write to ram (c_can isp) . . . . . . . . . . . . . 432 26.6.5 read memory (c_can isp). . . . . . . . . . . . . 432 26.6.6 prepare sectors for write operation (c_can isp) 432 26.6.7 copy ram to flash (c_can isp) . . . . . . . . . 432 26.6.8 go (c_can isp) . . . . . . . . . . . . . . . . . . . . . 432 26.6.9 erase sectors (c_can isp) . . . . . . . . . . . . . 432 26.6.10 blank check sectors (c_can isp) . . . . . . . . 432 26.6.11 read partid (c_can isp) . . . . . . . . . . . . . . 432 26.6.12 read boot code version (c_can isp) . . . . . 433 26.6.13 read serial number (c_can isp) . . . . . . . . 433 26.6.14 compare (c_can isp). . . . . . . . . . . . . . . . . 433 26.6.15 c_can isp sdo abort codes . . . . . . . . . . . 433 26.6.16 differences to fully-compliant canopen . . . . 434 26.7 iap commands . . . . . . . . . . . . . . . . . . . . . . . . 434 26.7.1 prepare sector(s) for write operation (iap) . . 436 26.7.2 copy ram to flash (iap) . . . . . . . . . . . . . . . 436 26.7.3 erase sector(s) (iap) . . . . . . . . . . . . . . . . . . 437 26.7.4 blank check sector(s) (iap) . . . . . . . . . . . . . 438 26.7.5 read part identification number (iap) . . . . . 438 26.7.6 read boot code version number (iap) . . . . 438 26.7.7 compare (iap). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 26.7.8 reinvoke isp (iap) . . . . . . . . . . . . . . . . . . . 440 26.7.9 readuid (iap) . . . . . . . . . . . . . . . . . . . . . . . 440 26.7.10 erase page. . . . . . . . . . . . . . . . . . . . . . . . . . 440 26.7.11 iap status codes . . . . . . . . . . . . . . . . . . . . . 441 26.8 debug notes . . . . . . . . . . . . . . . . . . . . . . . . . 441 26.8.1 comparing flash images . . . . . . . . . . . . . . . 441 26.8.2 serial wire debug (swd) flash programming interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 26.9 flash memory access. . . . . . . . . . . . . . . . . . 442 26.10 flash signature generation . . . . . . . . . . . . . 443 26.10.1 register description for signature generation 443 26.10.1.1 signature generat ion address and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 26.10.1.2 signature gener ation result registers . . . . . . 444 26.10.1.3 flash module status regi ster . . . . . . . . . . . 445 26.10.1.4 flash module status clear register . . . . . . . 445 26.10.2 algorithm and procedur e for signature generation 445 signature generation . . . . . . . . . . . . . . . . . . . 445 content verification . . . . . . . . . . . . . . . . . . . . 446 chapter 27: lpc111x/lpc11cxx serial wire debug (swd) 27.1 how to read this chapter . . . . . . . . . . . . . . . . 447 27.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 27.3 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 447 27.4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 27.5 pin description . . . . . . . . . . . . . . . . . . . . . . . 447 27.6 debug notes . . . . . . . . . . . . . . . . . . . . . . . . . 448 27.6.1 debug limitations . . . . . . . . . . . . . . . . . . . . . 448 27.6.2 debug connections . . . . . . . . . . . . . . . . . . . 448 chapter 28: lpc111x/lpc11cxx appendix: arm cortex-m0 reference 28.1 how to read this chapter . . . . . . . . . . . . . . . . 449 28.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 449 28.3 about the cortex-m0 processor and core peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 28.3.1 system-level interface . . . . . . . . . . . . . . . . . 450 28.3.2 integrated configurable debug . . . . . . . . . . . 450 28.3.3 cortex-m0 processor features summary . . . 450 28.3.4 cortex-m0 core peripherals . . . . . . . . . . . . . 451 28.4 processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 28.4.1 programmers model . . . . . . . . . . . . . . . . . . . 451 28.4.1.1 processor modes . . . . . . . . . . . . . . . . . . . . . 451 28.4.1.2 stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 28.4.1.3 core registers . . . . . . . . . . . . . . . . . . . . . . . 451 28.4.1.3.1 general-purpose registers . . . . . . . . . . . . . . 452 28.4.1.3.2 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . 452 28.4.1.3.3 . . . . . . . . . . . . . . . . . . . . . . . . .link register 453 28.4.1.3.4 program counter . . . . . . . . . . . . . . . . . . . . . 453 28.4.1.3.5 program status register . . . . . . . . . . . . . . . 453 28.4.1.3.6 exception mask register . . . . . . . . . . . . . . . . 455 28.4.1.3.7 control register . . . . . . . . . . . . . . . . . . . . 455 28.4.1.4 exceptions and interrupts . . . . . . . . . . . . . . . 456 28.4.1.5 data types . . . . . . . . . . . . . . . . . . . . . . . . . . 456 28.4.1.6 the cortex microcontroller software interface standard. . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 28.4.2 memory model . . . . . . . . . . . . . . . . . . . . . . . 457 28.4.2.1 memory regions, types and attributes . . . . . 458 28.4.2.2 memory system orde ring of memory accesses . . 459 28.4.2.3 behavior of memory accesses . . . . . . . . . . 459 28.4.2.4 software ordering of memory accesses. . . . 460 28.4.2.5 memory endianness. . . . . . . . . . . . . . . . . . . 461 28.4.2.5.1 little-endian format . . . . . . . . . . . . . . . . . . . 461 28.4.3 exception model . . . . . . . . . . . . . . . . . . . . . 461 28.4.3.1 exception states. . . . . . . . . . . . . . . . . . . . . . 461 28.4.3.2 exception types . . . . . . . . . . . . . . . . . . . . . . 462 28.4.3.3 exception handlers . . . . . . . . . . . . . . . . . . . 463 28.4.3.4 vector table . . . . . . . . . . . . . . . . . . . . . . . . . 463 28.4.3.5 exception priorities. . . . . . . . . . . . . . . . . . . . 464 28.4.3.6 exception entry and return . . . . . . . . . . . . . . 465 28.4.3.6.1 exception entry . . . . . . . . . . . . . . . . . . . . . . 465 28.4.3.6.2 exception return. . . . . . . . . . . . . . . . . . . . . . 466 28.4.4 fault handling . . . . . . . . . . . . . . . . . . . . . . . 467 28.4.4.1 lockup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 541 of 543 nxp semiconductors um10398 chapter 29: supplementary information 28.4.5 power management . . . . . . . . . . . . . . . . . . . 468 28.4.5.1 entering sleep mode. . . . . . . . . . . . . . . . . . . 468 28.4.5.1.1 wait for interrupt . . . . . . . . . . . . . . . . . . . . . . 468 28.4.5.1.2 wait for event . . . . . . . . . . . . . . . . . . . . . . . . 468 28.4.5.1.3 sleep-on-exit . . . . . . . . . . . . . . . . . . . . . . . . 469 28.4.5.2 wake-up from sleep mode . . . . . . . . . . . . . . 469 28.4.5.2.1 wake-up from wfi or sleep-on-exit . . . . . . . 469 28.4.5.2.2 wake-up from wfe . . . . . . . . . . . . . . . . . . . 469 28.4.5.3 power management programming hints. . . . 469 28.5 instruction set . . . . . . . . . . . . . . . . . . . . . . . . 469 28.5.1 instruction set summary . . . . . . . . . . . . . . . . 469 28.5.2 intrinsic functions . . . . . . . . . . . . . . . . . . . . . 471 28.5.3 about the inst ruction descriptions. . . . . . . . . 472 28.5.3.1 operands . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 28.5.3.2 restrictions when using pc or sp . . . . . . . . 472 28.5.3.3 shift operations . . . . . . . . . . . . . . . . . . . . . . 473 28.5.3.3.1 asr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 28.5.3.3.2 lsr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 28.5.3.3.3 lsl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 28.5.3.3.4 ror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 28.5.3.4 address alignment . . . . . . . . . . . . . . . . . . . . 475 28.5.3.5 pc-relative expressions . . . . . . . . . . . . . . . . 475 28.5.3.6 conditional execution . . . . . . . . . . . . . . . . . . 476 28.5.3.6.1 the condition flags . . . . . . . . . . . . . . . . . . . . 476 28.5.3.6.2 condition code suffixes . . . . . . . . . . . . . . . . 476 28.5.4 memory access instructions . . . . . . . . . . . . . 477 28.5.4.1 adr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 28.5.4.1.1 syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 28.5.4.1.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 28.5.4.1.3 restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . 478 28.5.4.1.4 condition flags . . . . . . . . . . . . . . . . . . . . . . . 478 28.5.4.1.5 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 28.5.4.2 ldr and str, immediate offset . . . . . . . . . . 478 28.5.4.2.1 syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 28.5.4.2.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 28.5.4.2.3 restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . 479 28.5.4.2.4 condition flags . . . . . . . . . . . . . . . . . . . . . . . 479 28.5.4.2.5 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 28.5.4.3 ldr and str, register offset . . . . . . . . . . . . 479 28.5.4.3.1 syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 28.5.4.3.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 28.5.4.3.3 restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . 480 28.5.4.3.4 condition flags . . . . . . . . . . . . . . . . . . . . . . . 480 28.5.4.3.5 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 28.5.4.4 ldr, pc-relative. . . . . . . . . . . . . . . . . . . . . . 480 28.5.4.4.1 syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 28.5.4.4.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 28.5.4.4.3 restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . 480 28.5.4.4.4 condition flags . . . . . . . . . . . . . . . . . . . . . . . 480 28.5.4.4.5 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 28.5.4.5 ldm and stm . . . . . . . . . . . . . . . . . . . . . . . 481 28.5.4.5.1 syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 28.5.4.5.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 28.5.4.5.3 restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . 481 28.5.4.5.4 condition flags . . . . . . . . . . . . . . . . . . . . . . . 482 28.5.4.5.5 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 482 28.5.4.5.6 incorrect examples . . . . . . . . . . . . . . . . . . . . 482 28.5.4.6 push and pop . . . . . . . . . . . . . . . . . . . . . . 482 28.5.4.6.1 syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482 28.5.4.6.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 482 28.5.4.6.3 restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 482 28.5.4.6.4 condition flags . . . . . . . . . . . . . . . . . . . . . . . 483 28.5.4.6.5 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 28.5.5 general data processing instructions. . . . . . 483 28.5.5.1 adc, add, rsb, sbc, and sub. . . . . . . . . 484 28.5.5.1.1 syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 28.5.5.1.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 28.5.5.1.3 restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 485 28.5.5.1.4 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 28.5.5.2 and, orr, eor, and bic. . . . . . . . . . . . . . 485 28.5.5.2.1 syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 28.5.5.2.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 28.5.5.2.3 restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 486 28.5.5.2.4 condition flags . . . . . . . . . . . . . . . . . . . . . . . 486 28.5.5.2.5 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 28.5.5.3 asr, lsl, lsr, and ror . . . . . . . . . . . . . . 486 28.5.5.3.1 syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 28.5.5.3.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 28.5.5.3.3 restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 487 28.5.5.3.4 condition flags . . . . . . . . . . . . . . . . . . . . . . . 487 28.5.5.3.5 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 28.5.5.4 cmp and cmn. . . . . . . . . . . . . . . . . . . . . . . 487 28.5.5.4.1 syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 28.5.5.4.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 28.5.5.4.3 restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 488 28.5.5.4.4 condition flags . . . . . . . . . . . . . . . . . . . . . . . 488 28.5.5.4.5 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 28.5.5.5 mov and mvn. . . . . . . . . . . . . . . . . . . . . . . 488 28.5.5.5.1 syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 28.5.5.5.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 28.5.5.5.3 restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 489 28.5.5.5.4 condition flags . . . . . . . . . . . . . . . . . . . . . . . 489 28.5.5.5.5 example. . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 28.5.5.6 muls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 28.5.5.6.1 syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 28.5.5.6.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 28.5.5.6.3 restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 490 28.5.5.6.4 condition flags . . . . . . . . . . . . . . . . . . . . . . . 490 28.5.5.6.5 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 28.5.5.7 rev, rev16, and revsh . . . . . . . . . . . . . . 490 28.5.5.7.1 syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 28.5.5.7.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 28.5.5.7.3 restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 491 28.5.5.7.4 condition flags . . . . . . . . . . . . . . . . . . . . . . . 491 28.5.5.7.5 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 28.5.5.8 sxt and uxt. . . . . . . . . . . . . . . . . . . . . . . . 491 28.5.5.8.1 syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 28.5.5.8.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 28.5.5.8.3 restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 491 28.5.5.8.4 condition flags . . . . . . . . . . . . . . . . . . . . . . . 491 28.5.5.8.5 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 28.5.5.9 tst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 28.5.5.9.1 syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 28.5.5.9.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 28.5.5.9.3 restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 492 28.5.5.9.4 condition flags . . . . . . . . . . . . . . . . . . . . . . . 492
um10398 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. user manual rev. 12.1 ? 7 august 2013 542 of 543 nxp semiconductors um10398 chapter 29: supplementary information 28.5.5.9.5 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 28.5.6 branch and control instructions . . . . . . . . . . 492 28.5.6.1 b, bl, bx, and blx . . . . . . . . . . . . . . . . . . . 493 28.5.6.1.1 syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 28.5.6.1.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 28.5.6.1.3 restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . 493 28.5.6.1.4 condition flags . . . . . . . . . . . . . . . . . . . . . . . 494 28.5.6.1.5 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 28.5.7 miscellaneous instructions . . . . . . . . . . . . . . 494 28.5.7.1 bkpt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 28.5.7.1.1 syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 28.5.7.1.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 28.5.7.1.3 restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . 495 28.5.7.1.4 condition flags . . . . . . . . . . . . . . . . . . . . . . . 495 28.5.7.1.5 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 28.5.7.2 cps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 28.5.7.2.1 syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 28.5.7.2.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 28.5.7.2.3 restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . 496 28.5.7.2.4 condition flags . . . . . . . . . . . . . . . . . . . . . . . 496 28.5.7.2.5 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 28.5.7.3 dmb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 28.5.7.3.1 syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 28.5.7.3.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 28.5.7.3.3 restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . 496 28.5.7.3.4 condition flags . . . . . . . . . . . . . . . . . . . . . . . 496 28.5.7.3.5 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 28.5.7.4 dsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 28.5.7.4.1 syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 28.5.7.4.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 28.5.7.4.3 restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . 496 28.5.7.4.4 condition flags . . . . . . . . . . . . . . . . . . . . . . . 497 28.5.7.4.5 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 28.5.7.5 isb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 28.5.7.5.1 syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 28.5.7.5.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 28.5.7.5.3 restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . 497 28.5.7.5.4 condition flags . . . . . . . . . . . . . . . . . . . . . . . 497 28.5.7.5.5 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 28.5.7.6 mrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 28.5.7.6.1 syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 28.5.7.6.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 28.5.7.6.3 restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . 497 28.5.7.6.4 condition flags . . . . . . . . . . . . . . . . . . . . . . . 498 28.5.7.6.5 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 28.5.7.7 msr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 28.5.7.7.1 syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 28.5.7.7.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 28.5.7.7.3 restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . 498 28.5.7.7.4 condition flags . . . . . . . . . . . . . . . . . . . . . . . 498 28.5.7.7.5 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 28.5.7.8 nop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 28.5.7.8.1 syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 28.5.7.8.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 28.5.7.8.3 restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . 498 28.5.7.8.4 condition flags . . . . . . . . . . . . . . . . . . . . . . . 499 28.5.7.8.5 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 28.5.7.9 sev . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 28.5.7.9.1 syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 28.5.7.9.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 28.5.7.9.3 restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 499 28.5.7.9.4 condition flags . . . . . . . . . . . . . . . . . . . . . . . 499 28.5.7.9.5 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 28.5.7.10 svc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 28.5.7.10.1 syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 28.5.7.10.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . 499 28.5.7.10.3 restrictions . . . . . . . . . . . . . . . . . . . . . . . . 499 28.5.7.10.4 condition flags . . . . . . . . . . . . . . . . . . . . . . 499 28.5.7.10.5 examples . . . . . . . . . . . . . . . . . . . . . . . . . . 500 28.5.7.11 wfe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 28.5.7.11.1 syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 28.5.7.11.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . 500 28.5.7.11.3 restrictions . . . . . . . . . . . . . . . . . . . . . . . . 500 28.5.7.11.4 condition flags . . . . . . . . . . . . . . . . . . . . . . 500 28.5.7.11.5 examples . . . . . . . . . . . . . . . . . . . . . . . . . . 500 28.5.7.12 wfi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 28.5.7.12.1 syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 28.5.7.12.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . 501 28.5.7.12.3 restrictions . . . . . . . . . . . . . . . . . . . . . . . . 501 28.5.7.12.4 condition flags . . . . . . . . . . . . . . . . . . . . . . 501 28.5.7.12.5 examples . . . . . . . . . . . . . . . . . . . . . . . . . . 501 28.6 peripherals. . . . . . . . . . . . . . . . . . . . . . . . . . . 501 28.6.1 about the arm cortex-m0. . . . . . . . . . . . . . 501 28.6.2 nested vectored interru pt controller . . . . . . 501 28.6.2.1 accessing the cort ex-m0 nvic registers using cmsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 28.6.2.2 interrupt set-enable register. . . . . . . . . . . . 502 28.6.2.3 interrupt clear-enable register . . . . . . . . . . 503 28.6.2.4 interrupt set-pending register. . . . . . . . . . . 503 28.6.2.5 interrupt clear-pending register . . . . . . . . . 504 28.6.2.6 interrupt priority register s . . . . . . . . . . . . . . 504 28.6.2.7 level-sensitive and pulse interrupts. . . . . . . 505 28.6.2.7.1 hardware and softwa re control of interrupts 505 28.6.2.8 nvic usage hints and tips . . . . . . . . . . . . . . 506 28.6.2.8.1 nvic programming hints . . . . . . . . . . . . . . . 506 28.6.3 system control block. . . . . . . . . . . . . . . . . . 506 28.6.3.1 the cmsis mapping of the cortex-m0 scb registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 28.6.3.2 cpuid register . . . . . . . . . . . . . . . . . . . . . . 507 28.6.3.3 interrupt co ntrol and state register . . . . . . 507 28.6.3.4 application interrupt and reset control register. 509 28.6.3.5 system control register . . . . . . . . . . . . . . . 510 28.6.3.6 configuration and control register . . . . . . . . 511 28.6.3.7 system handler priority registers . . . . . . . . . 511 28.6.3.7.1 system handler priority register 2 . . . . . . . . 511 28.6.3.7.2 system handler priority register 3 . . . . . . . 512 28.6.3.8 scb usage hints and tips. . . . . . . . . . . . . . . 512 28.6.4 system timer, systick . . . . . . . . . . . . . . . . . 512 28.6.4.1 systick control and status register . . . . . . 513 28.6.4.2 systick reload value register . . . . . . . . . . 513 28.6.4.2.1 calculating the reload value . . . . . . . . . . 513 28.6.4.3 systick curre nt value register . . . . . . . . . . 513 28.6.4.4 systick calibration val ue regist er . . . . . . . 514 28.6.4.5 systick usage hints and tips . . . . . . . . . . . . 514 28.7 cortex-m0 instruction su mmary . . . . . . . . . 515
nxp semiconductors um10398 chapter 29: supplementary information ? nxp b.v. 2013. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 7 august 2013 document identifier: um10398 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 543 chapter 29: supplementary information 29.1 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 518 29.2 references . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 29.3 legal information. . . . . . . . . . . . . . . . . . . . . . 519 29.3.1 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 29.3.2 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 519 29.3.3 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 519 29.4 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 29.5 figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 29.6 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531

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